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V363EPC A0 Data Sheet V363EPC A0 Local Bus to PCI Bridge
for Embedded Processors
1.0 About the V363EPC
w Direct interface to these processors: * AMD(R) AM29030/40TM * IBM(R) PowerPC 401TM Gx * Intel(R) i960(R) Cx/Hx/Jx/Sx w Fully compliant with PCI Local Bus Specification, Revision 2.1 w Configurable for system master, PCI bus master, or PCI target operation w Type 0 and Type 1 PCI configuration cycles w Up to 1 kB burst access on the PCI or the local bus w 640 bytes of programmable FIFO storage with Dynamic Bandwidth AllocationTM architecture w 64-byte read FIFO in each direction w Enhanced support for 8-bit/16-bit local bus devices with programmable region sizes w Dual bi-directional address space remapping w 10-bit bus watch timer w On-the-fly byte order (endian) conversion w Low-cost 160-pin EIAJ PQFP package (Electronic Industries Association of Japan Plastic Quad Flat Pack) w I2O-ReadyTM ATU and messaging unit, including hardware controlled circular queues w Two-channel DMA, multiprocessor DMA chaining, and demand mode DMA w Hot Swap CapableTM according to the PICMG(R) Hot Swap Specification, version 2.1 w Sixteen 8-bit bi-directional mailbox registers with doorbell interrupts w Support for real-mode MS-DOS(R) holes w Flexible PCI and local interrupt management w Optional power-on serial EEPROM initialization w Up to 50 MHz on both PCI and local bus clocks w 3.3 V operation; 5 V tolerant input w Industrial temperature range (-40C to +85C)
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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About the V363EPC
The V363EPC offers the highest performance, most flexible, and most economical solution for interfacing either 32-bit or 16-bit local bus applications to the PCI bus. It is also an ideal candidate for a variety of high-performance applications based on Motorola, IBM, DEC, Hitachi, and other popular embedded processors where only a minimal amount of glue logic is needed. V363EPC is the 3.3 V enhanced version of the V350EPC and V360EPC Rev A1 devices and supports powerful features like Hot Swap and DMA chaining. The PCI bus operates at up to 50 MHz, independent of local bus clock frequency. The overall throughput of the system is dramatically improved by using our unique Dynamic Bandwidth AllocationTM architecture. Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are provided for PCI-to-local bus accesses. There are 64 bytes of read FIFOs in each direction, 32 bytes dedicated for each aperture. Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer engine for bulk data transfers. Mailbox registers and flexible PCI interrupt controllers also provide a simple mechanism to emulate PCI device control ports. The part is available in a 160-pin, low-cost PQFP package. This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V363EPC. Detailed functional information is contained in the User's Manual.
Note: V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Product Codes
Figure 1: Example Applications
V380SDC SDRAM Controller SDRAM
Graphics Engine
Frame Buffer and RAMDAC
To Monitor
V363EPC V363EPC I2O Ready
Card is never a bus master and receives video data from other masters PCI Bus
PCI Edge Connector
CPU CPU SCSI Controller Hard Disk
V363EPC
V363EPC I2O Ready
Card acts as a bus master; it receives and transmits data on the PCI bus
PCI Bus
PCI Edge Connector
PCI Target Add-In Card
PCI Target Add-In Card
PCI Target Add-In Card
2.0 Product Codes
Table 1: Product Codes
Product Code V363EPC-50 REV A0 Package 160-pin EIAJ PQFP Frequency 50 MHz
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
3.0 Pin Descriptions and Pinouts
Table 2 lists the pin types found on the V363EPC. Together, Table 3 and Table 4 describe the function of each pin on the V363EPC. Table 5 lists the RESET state for test mode pins. Section 3.2 lists processor-mode-specific pin assignments and shows the pinouts for the 160-pin EIAJ PQFP package. Figure 6 shows the mechanical dimensions of the package. Table 2: Pin Types
Pin Type PCI I PCI O PCI I/O PCI I/OD I/O4 I O4 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 4 mA output drive. TTL input only pin. TTL output pin with 4 mA output drive. Description
Table 3: Signal Descriptions: Non-Processor Mode Dependent
Signal Type Reset State Description PCI Bus Interface Signals AD[31:0] C/BE[3:0] PAR FRAME IRDY TRDY STOP PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O Z Z Z Z Z Z Z Address and Data multiplexed on the same pins. Bus Command and Byte Enables multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates that the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected.
DEVSEL
PCI I/O
Z
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Pin Descriptions and Pinouts
Table 3: Signal Descriptions: Non-Processor Mode Dependent
Signal Type Reset State Description Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. Z Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCI Clock provides timing for all transactions on the PCI bus. Z/L PCI Reset acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal EPC operation to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Interrupt is used to receive or generate level-sensitive interrupt requests. Serial EEPROM Interface Signals SCL/LPERR SDA O4 I/O4 X X
EEPROM Clock, Local Parity Error.
IDSEL
PCI I
REQ GNT PCLK PRST
PCI O PCI I PCI I PCI I/O
PERR
PCI I/O
Z
SERR
PCI I/OD
Z
INT[A:D]
PCI I/OD
Z
EEPROM Data. Configuration Signal
RDIR
I
Reset Direction: tie low to drive PRST out and LRST in; tie high to drive LRST out and PRST in. Power and Ground Signals
VCC GND
-- --
Power leads for external connection to a 3.3 V VCC board plane. Ground leads for external connection to a GND board plane.
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Table 4: Signal Descriptions: Processor Mode Dependent
De-Multiplexed A/D AM29030/40 ID[31:0] LA[31:2] BWE[3:0] R/W -- LREQ RDY LBREQ LBGRT LPAR[3:0] BURST ERR LINT LRST MEMCLK i960Cx/Hx LD[31:0] LA[31:2] BE[3:0] W/R -- ADS READY HOLD HOLDA LPAR[3:0] BLAST BTERM LINT LRST LCLK Multiplexed A/D Type i960Jx LAD[31:0] LA[5:2] BE[3:0] W/R ALE ADS RDYRCY HOLD HOLDA LPAR[3:0] BLAST BTERM LINT LRST LCLK i960Sx LAD[15:0] LA[31:16] LA[5:2] BE[1:0] W/R ALE AS READY HOLD HOLDA LPAR[1:0] BLAST -- LINT LRST LCLK I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 O4 I I/O4 I/O4 I/O4 O4 I/O4 I Z Z Z H L/Z Reset State Z Z Z Z Z Z Z L1 Description De-multiplexed data bus. Multiplexed address and data bus. Address Bus LA[5:2] are output only in Multiplexed A/D mode. Byte Enables Read-Write strobe. Address Latch Enable
Address Strobe is asserted low to indicate the beginning of a bus cycle; interpreted as LREQ in AM29030/40 mode.
Data Ready Bus Mastership Request Bus Mastership Grant Data Parity BURST: Burst Request BLAST: Burst Last ERR: Bus Time-out BTERM: Burst Terminate Local Interrupt Request
Local Bus RESET
Local Bus Clock
1. The reset state is `H' in AM29030/40 mode.
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Pin Descriptions and Pinouts
Test Mode Pins
3.1
Test Mode Pins
Several device pins are used during the manufacturing test to put the V363EPC device into various test modes.
Note: These pins must be maintained at proper levels during reset to insure proper operation.
This is typically handled through pull-up or pull-down resistors (typically 1-10 k) on the signal pins if they are not guaranteed to be at the proper level during reset. Table 5 shows the reset states for test mode pins. Table 5: RESET State for Test Mode Pins
Mode Pin 134 Pin 135 Pin 153
i960 Cx/Hx AMD 2930/40 i960 Jx i960 Sx
Pull up Pull down Pull down Pull down
Pull up Pull up Pull up Pull down
Pull up Pull up Pull down Pull down
3.2
Processor-mode Specific Pin Assignments
The following tables and diagrams describe the pin assignments for the V363EPC A0 in its various processor modes. * AM29030/040 mode: Table 6 and Figure 2 * i960 Cx/Hx mode: Table 7 and Figure 3 * i960 Jx mode: Table 8 and Figure 4 * i960 Sx mode: Table 9 and Figure 5
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Table 6: Pin Assignments for AM29030/40 Mode
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Signal
VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 GND
PIN #
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Signal
VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND ID0 LA31 ID1 LA30 ID2 LA29 ID3 LA28 ID4 LA27 ID5 LA26 ID6 LA25 ID7 LA24 LPAR0 LPAR1 GND
PIN #
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Signal
VCC LA23 ID8 LA22 ID9 LA21 ID10 LA20 ID11 LA19 ID12 LA18 ID13 LA17 ID14 LA16 ID15 LA15 ID16 VCC GND LA14 ID17 LA13 ID18 LA12 ID19 LA11 ID20 LA10 ID21 LA9 ID22 LA8 ID23 LA7 LPAR2 LPAR3 ID24 GND
PIN #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Signal
VCC LA6 ID25 LA5 ID26 LA4 ID27 LA3 ID28 LA2 ID29 ID30 ID31 `0' ERR RDY LBREQ LBGNT LREQ VCC GND MEMCLK NC VCC BWE3 BWE2 BWE1 BWE0 BURST R/W RDIR LRST `1' LINT SDA SCL/LPERR INTA INTB INTC GND
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Figure 2: Pinout for AM29030/40 Mode (top view)
GND ID24 LPAR3 LPAR2 LA7 ID23 LA8 ID22 LA9 ID21 LA10 ID20 LA11 ID19 LA12 ID18 LA13 ID17 LA14 GND Vcc ID16 LA15 ID15 LA16 ID14 LA17 ID13 LA18 ID12 LA19 ID11 LA20 ID10 LA21 ID9 LA22 ID8 LA23 Vcc
120 81
160
Vcc INTD# PRST# PCLK GNT# REQ# AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
1
40
Vcc LA6 ID25 LA5 ID26 LA4 ID27 LA3 ID28 LA2 ID29 ID30 ID31 `0' ERR# RDY# LBREQ# LBGNT# LREQ# Vcc GND MEMCLK NC Vcc BWE3# BWE2# BWE1# BWE0# BURST# R/W# RDIR LRST# `1' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND
121
80
V363EPC
AM29030/40 Mode
41
GND LPAR1 LPAR0 LA24 ID7 LA25 ID6 LA26 ID5 LA27 ID4 LA28 ID3 LA29 ID2 LA30 ID1 LA31 ID0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Table 7: Pin Assignments for i960 Cx/Hx Mode
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Signal
VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 GND
PIN #
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Signal
VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LD0 LA31 LD1 LA30 LD2 LA29 LD3 LA28 LD4 LA27 LD5 LA26 LD6 LA25 LD7 LA24 LPAR0 LPAR1 GND
PIN #
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Signal
VCC LA23 LD8 LA22 LD9 LA21 LD10 LA20 LD11 LA19 LD12 LA18 LD13 LA17 LD14 LA16 LD15 LA15 LD16 VCC GND LA14 LD17 LA13 LD18 LA12 LD19 LA11 LD20 LA10 LD21 LA9 LD22 LA8 LD23 LA7 LPAR2 LPAR3 LD24 GND
PIN #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Signal
VCC LA6 LD25 LA5 LD26 LA4 LD27 LA3 LD28 LA2 LD29 LD30 LD31 `1' BTERM READY HOLD HOLDA ADS VCC GND LCLK NC VCC BE3 BE2 BE1 BE0 BLAST W/R RDIR LRST `1' LINT SDA SCL/LPERR INTA INTB INTC GND
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Figure 3: Pinout for i960 Cx/Hx Mode (top view)
120
81
GND LD24 LPAR3 LPAR2 LA7 LD23 LA8 LD22 LA9 LD21 LA10 LD20 LA11 LD19 LA12 LD18 LA13 LD17 LA14 GND Vcc LD16 LA15 LD15 LA16 LD14 LA17 LD13 LA18 LD12 LA19 LD11 LA20 LD10 LA21 LD9 LA22 LD8 LA23 Vcc
160
Vcc INTD# PRST# PCLK GNT# REQ# AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
1
40
Vcc LA6 LD25 LA5 LD26 LA4 LD27 LA3 LD28 LA2 LD29 LD30 LD31 `1' BTERM# READY# HOLD HOLDA ADS# Vcc GND LCLK NC Vcc BE3# BE2# BE1# BE0# BLAST# W/R# RDIR LRST# `1' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND
121
80
V363EPC
i960 Cx/Hx Mode
41
GND LPAR1 LPAR0 LA24 LD7 LA25 LD6 LA26 LD5 LA27 LD4 LA28 LD3 LA29 LD2 LA30 LD1 LA31 LD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Table 8: Pin Assignments for i960 Jx Mode
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Signal
VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 GND
PIN #
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Signal
VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LAD0 NC LAD1 NC LAD2 NC LAD3 NC LAD4 NC LAD5 NC LAD6 NC LAD7 NC LPAR0 LPAR1 GND
PIN #
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Signal
VCC NC LAD8 NC LAD9 NC LAD10 NC LAD11 NC LAD12 NC LAD13 NC LAD14 NC LAD15 NC LAD16 VCC GND NC LAD17 NC LAD18 NC LAD19 NC LAD20 NC LAD21 NC LAD22 NC LAD23 NC LPAR2 LPAR3 LAD24 GND
PIN #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Signal
VCC NC LAD25 LA5 LAD26 LA4 LAD27 LA3 LAD28 LA2 LAD29 LAD30 LAD31 ALE BTERM RDYRCV HOLD HOLDA ADS VCC GND LCLK NC VCC BE3 BE2 BE1 BE0 BLAST W/R RDIR LRST `0' LINT SDA SCL/LPERR INTA INTB INTC GND
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Figure 4: Pinout for i960 Jx Mode (top view)
120
81
GND LAD24 LPAR3 LPAR2 NC LAD23 NC LAD22 NC LAD21 NC LAD20 NC LAD19 NC LAD18 NC LAD17 NC GND Vcc LAD16 NC LAD15 NC LAD14 NC LAD13 NC LAD12 NC LAD11 NC LAD10 NC LAD9 NC LAD8 NC Vcc
160
Vcc INTD# PRST# PCLK GNT# REQ# AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
1
40
Vcc NC LAD25 LA5 LAD26 LA4 LAD27 LA3 LAD28 LA2 LAD29 LAD30 LAD31 ALE BTERM# RDYRCV# HOLD HOLDA ADS# Vcc GND LCLK NC Vcc BE3# BE2# BE1# BE0# BLAST# W/R# RDIR LRST# `0' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND
121
80
V363EPC
i960 Jx Mode
41
GND LPAR1 LPAR0 NC LAD7 NC LAD6 NC LAD5 NC LAD4 NC LAD3 NC LAD2 NC LAD1 NC LAD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Table 9: Pin Assignments for i960 Sx Mode
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Signal
VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 GND
PIN #
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Signal
VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LAD0 NC LAD1 NC LAD2 NC LAD3 NC LAD4 NC LAD5 NC LAD6 NC LAD7 NC LPAR0 LPAR1 GND
PIN #
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Signal
VCC NC LAD8 NC LAD9 NC LAD10 NC LAD11 NC LAD12 NC LAD13 NC LAD14 NC LAD15 NC LA16 VCC GND NC LA17 NC LA18 NC LA19 NC LA20 NC LA21 NC LA22 NC LA23 NC NC NC LA24 GND
PIN #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Signal
VCC NC LA25 LA5 LA26 LA4 LA27 LA3 LA28 LA2 LA29 LA30 LA31 ALE `0' READY HOLD HOLDA AS VCC GND LCLK NC VCC LA1 NC BE1 BE0 BLAST W/R RDIR LRST `0' LINT SDA SCL/LPERR INTA INTB INTC GND
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Processor-mode Specific Pin Assignments
Figure 5: Pinout for i960 Sx Mode (top view)
120
81
GND LAD24 NC NC NC LAD23 NC LAD22 NC LAD21 NC LAD20 NC LAD19 NC LAD18 NC LAD17 NC GND Vcc LAD16 NC LAD15 NC LAD14 NC LAD13 NC LAD12 NC LAD11 NC LAD10 NC LAD9 NC LAD8 NC Vcc
160
Vcc INTD# PRST# PCLK GNT# REQ# AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
1
40
Vcc NC LA25 LA5 LA26 LA4 LA27 LA3 LA28 LA2 LA29 LA30 LA31 ALE `0' READY# HOLD HOLDA AS# Vcc GND LCLK NC Vcc LA1 NC BE1# BE0# BLAST# W/R# RDIR LRST# `0' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND
121
80
V363EPC
i960 Sx Mode
41
GND LPAR1 LPAR0 NC LAD7 NC LAD6 NC LAD5 NC LAD4 NC LAD3 NC LAD2 NC LAD1 NC LAD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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Pin Descriptions and Pinouts
Mechanical Details
3.3
Mechanical Details
Figure 6: 160-pin EIAJ PQFP mechanical details
31.20.4SQ 28.00.2SQ
120 81
3.56MAX
121
80
0.15
INDEX
160 41
"P"
010
40
PIN 1 0.650.10 0.300.10
Unit of Measurement = millimeters
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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0.80.2
0.170.05
1.6TYP
DC Specifications
Mechanical Details
4.0 DC Specifications
The DC specifications for the PCI bus signals reference those given in the PCI Local Bus Specification, Revision 2.1, Section 4.2.2.1. For more information on the PCI DC specifications, see the PCI Local Bus Specification. Table 10: Absolute Maximum Ratings
Symbol VCC VIN TSTG Parameter Supply voltage DC input voltage Storage temperature range Value Units V V C
-0.3 to 3.8 -0.3 to 5.75 -55 to 125
Table 11: Guaranteed Operating Conditions
Symbol VCC Jmax
JA JC
Parameter Supply voltage 3.3 volt Maximum Junction temperature Junction-to-ambient thermal resistance Junction-to-case thermal resistance Ambient temperature range
Value 3.0 to 3.6 125 50 11
Units V C C/w C/w C
TA
-40 to 85
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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DC Specifications
PCI Bus DC Specifications
4.1
PCI Bus DC Specifications
Table 12: PCI Bus Signals DC Operating Specifications
Symbol VIH VIL IIL VOH VOL CIN CCLK CIDSEL Parameter Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Input pin capacitance PCLK pin capacitance IDSEL pin capacitance 5 0 < VIN < VCC IOUT = -500 A IOUT = 1500 A 0.9 VCC 0.1 VCC 10 12 8 Condition Min 0.5 VCC Max 5.75 0.3 VCC 10 Units V V
A
2
Notes
1
-0.5
V V pF pF pF
4 3
1. Custom 5 V tolerant PCI buffers are used in the design. 2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 3. Absolute maximum pin capacitance for a PCI unit is 10 pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
4.2
Local Bus DC Specifications
Table 13: Local Bus Signals DC Operating Specifications
Symbol VIL VIH IIL IIH VOL4 VOH4 IOZL IOZH ICC (max) ICC (typ) CIO Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4 mA outputs and I/O pins High level output voltage for 4 mA outputs and I/O pins Low level float input leakage High level float input leakage Maximum supply current Typical supply current Input and output capacitance VIN = GND VIN = VCC IOL = 4 mA IOH = -4 mA VIN = GND VIN = VCC VCC = 3.6 V PCLK = LCLK = 33 MHz VCC = 3.3 V PCLK = LCLK = 33 MHz 2.4 2.0 Conditions Min Max 0.8 Units V V
A
-10
10 0.4
A
V V
A
-10
10 55 44 10
A
mA mA pF
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
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AC Specifications
PCI Bus Timings
5.0 AC Specifications
The AC specifications for the PCI bus signals match those given in the PCI Local Bus Specification, Revision 2.1, Section 4.2.2.2. For more information on the PCI AC specifications, including the V/I curves for 3.3 V signalling, see the PCI Local Bus Specification.
5.1
PCI Bus Timings
Table 14: PCI Bus Signals AC Operating Specifications
Symbol Parameter Switching current high (Test point) Switching current low (Test point) ICL ICH Low clamp current High clamp current Unloaded output rise time Unloaded output fall time Condition 0 < VOUT 0.3 VCC IOH(AC) 0.3 VCC < VOUT < 0.9 VCC 0.7 VCC < VOUT < VCC VOUT = 0.7 VCC VCC > VOUT 0.6 VCC IOL(AC) 0.6 VCC > VOUT > 0.1 VCC 0.18 VCC > VOUT > 0 VOUT = 0.18 VCC 16 VCC 26.7 VOUT Equation D 38 VCC mA mA mA Min Max Units mA mA Equation C
-12 VCC -17.1 (VCC - VOUT) -32 VCC
mA mA mA
-3 < VIN -1
VCC + 4 > VIN VCC + 1 0.2 VCC - 0.6 VCC load
-25 + (VIN + 1) / 0.015
25 + (VIN - VCC - 1) / 0.015
tR
1
4
V/ns
tF
0.6 VCC - 0.2 VCC load
1
4
V/ns
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
19
AC Specifications
Local Bus Timings
5.2
Local Bus Timings
Table 15: Local Bus AC Test Conditions
Symbol VCC VIN COUT Parameter Supply voltage, 3.3 volt operation Input low and high voltages Capacitive load on output and I/O pins Limits 3.0 to 3.60 0.4 and 2.0 50 Units V V pF
Table 16: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4 mA Supply voltage 3.3 volt Derating +0.046 ns/pF for loads > 50pF
Figure 7: Clock and Synchronous Signals
TC TCH TSU TH TCL
LOCAL CLOCK INPUT SETUP/HOLD OUTPUT VALID
Tczo VALID TCOV VALID
OUTPUT DRIVE
TCOZ
VALID
OUTPUT FLOAT
20
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
AC Specifications
Local Bus Timings
Table 17: Local Bus Timing Parameters for VCC = 3.3 Volts 10%
# 1 2 3 4 4a 4b 5 6 6a 7 8 9 Symbol TC TCH TCL TSU TSU TSU TH TCOV TCOV TCZO TCOZ TRST Description LCLK/MEMCLK period LCLK/MEMCLK high time LCLK/MEMCLK low time Synchronous input setup Synchronous input setup (AS/ADS/LREQ) Synchronous input setup for HOLDA (LBGRT) Synchronous input hold LCLK/MEMCLK to output valid delay LCLK/MEMCLK to output valid delay (address, data) LCLK/MEMCLK to output driving delay LCLK/MEMCLK to output float delay Reset period when LRST used as input
5 4 1 2 3
Notes
Min 20 9 9 6 4 3 2 4 4 4 4 16 TC
Max Units ns ns ns ns ns ns ns 11 12 11 11 ns ns ns ns ns
1. Measured at 1.5 V. 2. Measured at 1.5 V. 3. All local bus signals except those in 4a and 4b. 4. All local bus signals except those in 6a. 5. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 18: PCI Bus Timing Parameters for VCC = 3.3 Volts 10%
# 1 2 2a 3 4 4a 5 6 7 Symbol TC TSU TSU TH TCOV TCOV TCZO TCOZ TRST Description PCLK period Synchronous input setup to PCLK Synchronous input setup to PCLK (GNT) Synchronous input hold from PCLK PCLK to output valid delay PCLK to output valid delay (REQ) PCLK to output driving delay PCLK to output float delay Reset period when PRST used as input
2 1
Notes
Min 20 7 9 0 3 3 3 4 16 TC
Max
Units ns ns ns ns
11 12 11 18
ns ns ns ns
1. All PCI bus signals except those in 2a. 2. All PCI bus signals except those in 4a.
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
21
Getting Help from V3 Semiconductor
Serial EEPROM Port TImings
5.3
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 8. Figure 8: Serial EEPROM Waveforms and Timings
512 PCI Bus Clocks
START CONDITION
STOP CONDITION
SCL SDA
256 PCI Bus Clocks
256 PCI Bus Clocks
6.0 Getting Help from V3 Semiconductor
If you need assistance with a technical question, please contact us. E-mail is the quickest and most efficient way to get technical support from V3. The V3 Web site also contains much technical support information as well as the most up-to-date technical documents. Visit us on the Web at: http://www.vcubed.com. Corporate Office 250 Consumers Road, Suite 901 Toronto, Ontario, Canada M2J 4V6 Telephone: 1-877-283-7364 (416) 497-8884 Fax: (416) 497-1160 E-mail: V3help@vcubed.com Sales Office 2348G Walsh Avenue Santa Clara, California 95051 USA Telephone: 1-800-488-8410 (408) 988-1050 Fax: (408) 988-2601
22
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
(c) 2000 V3 Semiconductor Corp.
Revision History
7.0 Revision History
Table 19: Revision History
Revision Number 1.01 1.00 Date Comments and Changes
10/00 Updated power consumption & JC. 07/00 Preliminary presilicon revision of data sheet.
Copyright (c) 2000 V3 Semiconductor Inc. All rights reserved. V3 and V3 Semiconductor are trademarks and/or registered trademarks of V3 Semiconductor Inc. in the United States and Canada. All other trademarks and/or registered trademarks are properties of their respective owners. V3 Semiconductor retains the right to change the documentation, specifications, and/or the component without notice.
(c) 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
23

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