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V380SDC A0 Datasheet
V380SDC High Performance SDRAM Controller
for 32-bit and 64-bit Embedded Processors
1.0 About the V380SDC
w Direct interface to these processors: * AMD(R) AM29030/40TM * IBM(R) PowerPC 401TM Gx * IDT(R) 79RC32364TM * Intel(R) i960(R) Cx/Hx/Jx/Rx/Vx * Motorola(R) M68040TM and 68K/ColdFire(R) * PowerPCTM 750/60x w Up to 75 MHz local bus clock w 8-bit bus watch timer w Up to 2 Kbytes of continuous burst access for 64-bit processors and 1 Kbyte for 32-bit processors w Zero-wait-state bursting w Dynamic bus protocol switching w User-customized processor bus interface w Support for up to 2 Gbytes of (Enhanced) SDRAM w Compatible with PC66, PC100, PC133 SDRAM w Supports a wide range of synchronous DRAMs, from 16 Mbit to 256 Mbit w System heartbeat and watchdog timers w Two 32-bit general purpose timers with pulsewidth modulation capability--useful for RTOS w 16-bytes of general purpose registers w Designed to work with the EPC family of PCI bridges from V3 Semiconductor w 3.3 V operation with 5 V tolerant inputs w Industrial temperature range (-40C to +85C) w Low-cost 100-pin PQFP package w Support for up to 4 single-bank or 2 dual-bank industry standard 168-pin SDRAM DIMM(s) or 144-pin SO-DIMM(s) w I2C EEPROM interface for Serial Presence Detect (SPD) on DIMM w Optional EEPROM initialization
(c) 2000 V3 Semiconductor Corp.
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About the V380SDC
The V380SDC High Performance SDRAM Controller provides all aspects of SDRAM control for high performance embedded systems. The V380SDC enables system designers to replace many lower integration support components with a single, high-integration device. This saves design time, board space, and manufacturing cost. The V380SDC from V3 Semiconductor provides the necessary (Enhanced) SDRAM access protocol and bus timing resources to work with the latest (E)SDRAM devices. The processor interface on the V380SDC implements the bus protocol of many popular RISC CPUs (AM29030/40, PowerPC 401 Gx, IDT 79RC32364, i960 Cx/Hx/Jx/Rx/Vx, M68040, 68K/ColdFire, PowerPC 750/60x). The V380SDC is also fully compatible with the EPC family of PCI bridges available from V3 Semiconductor. The V380SDC supports a total SDRAM memory subsystem size of up to 2 Gbytes. Standard memory devices from 16 Mbit to 256 Mbit are supported; 8-, 16-, 32-bit and 64-bit accesses are allowed. Four single-bank or two dualbank industry standard 168-pin PC SDRAM DIMM(s) or 144-pin SO-DIMM(s) with Serial Presence Detect (SPD) are also supported. The V380SDC provides an 8-bit bus watch timer to detect and recover from accesses to unpopulated memory regions. Two on-chip, general purpose, 32-bit timers can be individually configured as a pulse width modulator or they may be used in other modes such as retriggerable or one-shot. The V380SDC is packaged in a low-cost 100-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 75 MHz speed grade. This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V380SDC. Detailed functional information is contained in the User's Manual. Figure 1: Example Application
Note:
V3 Semiconductor retains the rights to change the documentation, the specifications, or device functionality at any time without notice. Contact V3 and verify that you have the latest copy of all documents before finalizing a design.
i960Cx/Hx/Jx/Rx/Vx, PowerPC 401Gx, IDT 79RC32364, M68040/ColdFire/68K, PowerPC 750, or Am29030/40 Processor
V380SDC
SDRAM DIMM(s)
Flash
Local Bus
V3 Local-to-PCI Bridge
PCI Bus
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Product Codes
2.0 Product Codes
Table 1: Product Code
Product Code V380SDC-75 REV A0 Package 100-pin EIAJ PQFP Frequency 75 MHz
3.0 Pin Description
Table 2 lists the pin types found on the V380SDC; Table 3 describes the function of each pin. Table 2: Pin Types
Pin Type I/O8 I/OD I OD O8 O12 Description TTL I/O pin with 8 mA output drive. TTL input with open drain output. TTL input only pin. TTL open drain output. TTL output pin with 8 mA output drive. TTL output pin with 12 mA output drive.
(c) 2000 V3 Semiconductor Corp.
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Pin Description
Table 3: Signal Descriptions
Signal Type Ra Description Processor Bus Interface A[31:2] I Address Bus For demultiplexed processors, A[31:2] is used. For multiplexed processors, only A[31:8] is used; A[2] is used as ALE (Address Latch Enable) input. Byte Enables (BE, BWE), Transfer Size (SIZ, TSIZ), or Address (A[1:0]) are multiplexed on these pins depending on processor mode. Z Address (Data) Bus For demultiplexed processors, AD[7:0] is used as D[7:0]. For multiplexed processors, AD[7:0] is used as the multiplexed address/data bus. Address Strobe Asserted low to indicate the beginning of a bus cycle: It can be interpreted as REQ or TS depending on processor mode. Write/Read It can be interpreted as RNW or RD depending on processor mode. Burst Last It can be interpreted as BURST, TBST, or LAST depending on processor mode. Z Data Ready It can be interpreted as RDY, TA, RDYRCV, or ACK depending on processor mode. Address Retry for PPC750 processor. During reset, the state of the pin along with the processor mode also determine the default value of the SDC_REG_BASE register. Z Address Acknowledge for PPC750 processor or Data Enable output in other processor modes intended for buffer control. This DEN output is not to be connected to the processor. Transfer Type SDRAM Interface CS[3:0] MA[14:0] RAS CAS MWE DQM[7:0] IOC[3:0] SDA O8 O12 O12 O12 O12 O8 I/O8 I/OD Z Z Z Z Z Z Z Z SDRAM Chip Select SDRAM Memory Address MA[14:13] are typically used for BA[1:0] SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Memory Write Enable SDRAM Data Mask Multi-purpose I/O which can be configured for many functions Serial EEPROM Data
BE[3:0]
I
AD[7:0]
I/O8
ADS
I
WNR BLAST READY
I I I/O8
ARTRY
I
AACK/DEN TT[1:0]
I/O8 I
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Pin Description
Table 3: Signal Descriptions (cont'd)
Signal SCL Type OD Ra Z Serial EEPROM Clock Clock and Reset CLK RSTIN I I Clock Input Reset Input Active low reset input used to initialize all internal functions of the chip. Power and Ground Signals VCC GND -- -- POWER leads for external connection to a 3.3 V VCC board plane. GROUND leads for external connection to a GND board plane. Description
a. R indicates state during reset.
(c) 2000 V3 Semiconductor Corp.
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Pin Description
Pinout
3.1
Pinout
Table 4 lists the pins by pin number. Figure 2: Pinout for 100-pin EIAJ PQFP (top view) shows the pinout for the 100-pin EIAJ PQFP package and Figure 3: 100-pin EIAJ PQFP mechanical details shows the mechanical dimensions of the package. Table 4: Pin Assignments
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal RSTIN A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Vcc GND A17 A18 A19 A20 A21 A22 A23 A24 A25 PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal A26 A27 A28 A29 A30 A31 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vcc GND CLK BE0 BE1 BE2 BE3 ADS WNR TT0 TT1 PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal CS0 CS2 MA14 MA13 MA12 DQM7 DQM3 Vcc GND MA11 MA10 MA9 MA8 MA7 DQM6 DQM2 GND MA6 MA5 MA4 MA3 MA2 DQM5 DQM1 Vcc PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal GND MA1 MA0 RAS CAS MWE DQM4 GND DQM0 CS1 CS3 AACK/DEN SDA SCL Vcc GND IOC0 IOC1 IOC2 IOC3 READY BLAST A2 A3 ARTRY
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Pin Description
Pinout
Figure 2: Pinout for 100-pin EIAJ PQFP (top view)
ARTRY# A3 A2 BLAST# READY# IOC3 IOC2 IOC1 IOC0 GND Vcc SCL SDA AACK#/DEN# CS3# CS1# DQM0 GND DQM4 MWE#
100 81 80
RSTIN# A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Vcc GND A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
1
V380SDC
30 31 50 51
CAS# RAS# MA0 MA1 GND Vcc DQM1 DQM5 MA2 MA3 MA4 MA5 MA6 GND DQM2 DQM6 MA7 MA8 MA9 MA10 MA11 GND Vcc DQM3 DQM7 MA12 MA13 MA14 CS2# CS0#
A31 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vcc GND CLK BE0# BE1# BE2# BE3# ADS# WNR TT0 TT1
(c) 2000 V3 Semiconductor Corp.
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DC Specifications
Pinout
Figure 3: 100-pin EIAJ PQFP mechanical details
4.0 DC Specifications
Table 5: Absolute Maximum Ratings
Symbol VCC VIN TSTG Parameter Supply voltage DC input voltage Storage temperature range Value -0.3 to +3.6 -0.3 to 6.0 -55 to +125 Units V V C
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DC Specifications
Pinout
Table 6: Guaranteed Operating Conditions
Symbol VCC Jmax Parameter Supply voltage Maximum junction temperature Value 3.0 to 3.6 125 75 24 -40 to +85 Units V C C/w C/w C
Theta Ja Thermal resistance (Package) Theta Jc Thermal resistance (Junction-Case) TA Ambient temperature range
Table 7: DC Operating Specifications (VCC = 3.3 V 0.3 V)
Symbol VIH VIL IIH IIL VOH VOL IOZL IOZH ICC (max) ICC (typ) ICC (stb) CIO Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Low level float input leakage High level float input leakage Maximum supply current Typical supply current Stand-by current Input and output capacitance VIN = VCC VIN =GND IOUT = -2, -8 mA IOUT = 2, 8 mA VOL = GND VOH = VCC LCLK = 75 MHz, VCC = 3.3 V LCLK = 33 MHz, VCC = 3.3 V VCC = 3.3 V -10 -10 -10 -10 2.4 0.4 10 10 60 25 2 10 Condition Min 2.0 0.8 10 10 Max Units V V A A V V A A mA mA mA pF
(c) 2000 V3 Semiconductor Corp.
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AC Specifications
Pinout
5.0 AC Specifications
Table 8: AC Test Conditions
Symbol VCC VIN COUT Parameter Supply voltage 3.3 volt operation Input low and high voltages Capacitive load on output and I/O pins Limits 3.0 to 3.60 0.4 and 2.0 50 Units V V pF
Table 9: Capacitive Derating for Output and I/O Pins
Output Drive Limit 8 mA 12 mA Supply voltage 3.3 volt 3.3 volt Derating +0.024 ns/pF for loads > 50pF +0.022 ns/pF for loads > 50pF
Figure 4: Clock and Synchronous Signals
TC TCH TSU TH TCL
CLOCK INPUT SETUP/HOLD OUTPUT VALID
Tczo VALID TCOV VALID
OUTPUT DRIVE
TCOZ
VALID
OUTPUT FLOAT
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AC Specifications
Pinout
Table 10: Timing Parameters for Vcc = 3.3 Volts 5%
75 MHz # 1 2 3 4a 4b 4c 4d 5 6a 6b 7 8 9 10 11 Symbol TC TCH TCL TSU TSU TSU TSU TH TCOV TCOV TCOZ TAS TAH TAH TPDQ CLK period CLK high time CLK low time Synchronous input setup (except AACK, WAIT) Asynchronous input setup (except AACK, WAIT, IOC[3:0]) Input setup for AACK Input setup for WAIT Synchronous input hold CLK to output valid delay (except IOC[3:0]) CLK to output valid delay (IOC[3:0] only) CLK to high impedance delay Address Setup to the trailing edge of ALE Address Hold from the trailing edge of ALE Address Hold from the rising edge of CLK Propogation Delay from BE to DQM 6 7 1, 8 2, 8 3 4 5 Description Notes Min 13.33 5.5 5.5 3 7 4 13 1 3 3 4 Tc ------ - 2 2 2 5 4 12 10 12 11 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1 Valid when SYNC bit in the PB_IO_CFG register is set to `1'. 2 Valid when SYNC bit in the PB_IO_CFG register is set to `0'. 3 Used by the bus watch timer to monitor unclaimed access only. 4 Input through IOC1. 5 Except when in ColdFire MCF5102 mode. 6 Only in ColdFire MCF5102 mode. 7 For BE changing with each datum in a burst write access only. 8 All IOC[3:0] input are synchronous except WAIT.
(c) 2000 V3 Semiconductor Corp.
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Getting Help from V3 Semiconductor
Serial EEPROM Port Timings
5.1
Serial EEPROM Port Timings
The clock for the serial EEPROM interface is derived by dividing the processor bus clock. The waveforms generated are shown in Figure 5. Figure 5: Serial EEPROM Waveforms and Timings
512 BUS CLOCKS
START CONDITION
STOP CONDITION
SCL
SDA
256 BUS CLOCKS
256 BUS CLOCKS
6.0 Getting Help from V3 Semiconductor
If you need assistance with a technical question, please contact us. E-mail is the quickest and most efficient way to get technical support from V3. Corporate Office 250 Consumers Road, Suite 901 Toronto, Ontario, Canada M2J 4V6 Telephone: 1-877-283-7364 (416) 497-8884 Fax: (416) 497-1160 E-mail: V3help@vcubed.com Sales Office 2348G Walsh Avenue Santa Clara, California 95051 USA Telephone: 1-800-488-8410 (408) 988-1050 Fax: (408) 988-2601
Some technical support information is also posted on the V3 Web site. This is the source of the most up-to-date documentation and is located at: http://www.vcubed.com.
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Revision History
Serial EEPROM Port Timings
7.0 Revision History
Table 11: Revision History
Revision Number 0.8 0.9 1.00 1.01 Date Comments and Changes
08/99 First pre-silicon revision of preliminary datasheet. 12/99 Second revision of preliminary datasheet. 5/00 6/00 First release. Add data to Table 7, "DC Operating Specifications (VCC = 3.3 V 0.3 V)," on page 9.
(c) 2000 V3 Semiconductor Corp.
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