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PD - 97263
IRF1324S-7PPBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
G S
VDSS RDS(on) typ. max. ID
D
24V 0.8m: 1.0m: 429A
S G S S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Single Pulse Avalanche Energy e Avalanche Current c Repetitive Avalanche Energy g
Max.
429c 303c 1640 300 2.0 20 1.6 -55 to + 175 300 10lbxin (1.1Nxm) 230 See Fig. 14, 15, 22a, 22b,
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR mJ A mJ
Thermal Resistance
Symbol
RJC RJA
Parameter
Junction-to-Case k Junction-to-Ambient (PCB Mount) , D Pak jk
2
Typ.
--- ---
Max.
0.50 40
Units
C/W
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1
10/10/06
IRF1324S-7PPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
24 --- --- 2.0 --- --- --- --- --- --- --- 0.023 --- 0.80 1.0 --- 4.0 --- 20 --- 250 --- 200 --- -200 3.0 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 160A g V VDS = VGS, ID = 250A A VDS = 24V, VGS = 0V VDS = 19V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
--- 180 47 58 122 19 240 86 93 7700 3380 1930 4780 4970 --- 252 --- --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 160A ID = 75A VDS =12V VGS = 10V g ID = 75A, VDS =0V, VGS = 10V g VDD = 16V ID = 160A RG =2.7 VGS = 10V g VGS = 0V VDS = 19V = 1.0MHz, See Fig.5 VGS = 0V, VDS = 0V to 19V i, See Fig.11 VGS = 0V, VDS = 0V to 19V h
270 --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related) --- Effective Output Capacitance (Time Related)h ---
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 429c --- 1636 A A
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 160A, VGS = 0V g VR = 20V, --- 71 107 ns TJ = 25C TJ = 125C IF = 160A --- 74 110 di/dt = 100A/s g --- 83 120 nC TJ = 25C TJ = 125C --- 92 140 --- 2.0 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 160A. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.018mH RG = 25, IAS = 160A, VGS =10V. Part not recommended for use above this value. ISD 160A, di/dt 600A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
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IRF1324S-7PPBF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
BOTTOM
100
100 4.5V
4.5V 10 0.1 1
60s PULSE WIDTH Tj = 25C
60s PULSE WIDTH Tj = 175C
10 100 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
10
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
1.8
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (A)
1.6 1.4 1.2 1.0 0.8 0.6
ID = 160A VGS = 10V
100
T J = 175C
10 T J = 25C 1 VDS = 15V 60s PULSE WIDTH 0.1 2 3 4 5 6 7 8 9
-60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 75A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance (pF)
VDS= 19V VDS= 12V
10000
Ciss Coss Crss
1000 1 10 VDS, Drain-to-Source Voltage (V) 100
0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF1324S-7PPBF
1000
10000
OPERATION IN THIS AREA LIMITED BY R DS(on)
T J = 175C 100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000 1msec 100sec
100 10msec
T J = 25C 10
10 Tc = 25C Tj = 175C Single Pulse 1 0 1 DC
VGS = 0V 1.0 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V)
10
100
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
32 Id = 5mA 31 30 29 28 27 26 25 24 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
VDS, Drain-to-Source Voltage (V)
450 400 350
ID, Drain Current (A)
Limited By Package
300 250 200 150 100 50 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
1.4 1.2 1.0
Energy (J)
Fig 10. Drain-to-Source Breakdown Voltage
1000
EAS , Single Pulse Avalanche Energy (mJ)
900 800 700 600 500 400 300 200 100 0 25 50 75 100
ID TOP 45A 80A BOTTOM 160A
0.8 0.6 0.4 0.2 0.0 -5 0 5 10 15 20 25
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRF1324S-7PPBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 2 3 4 4
Ri (C/W)
0.02070 0.08624 0.24491 0.15005
i (sec)
0.000010 0.000070 0.001406 0.009080
1
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1
0.001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100 0.05 0.10 10
0.01
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
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5
IRF1324S-7PPBF
250 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 160A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
EAR , Avalanche Energy (mJ)
200
150
100
50
0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
4.5
VGS(th) , Gate threshold Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) ID = 250A ID = 1.0mA ID = 1.0A
Fig 16. Threshold Voltage Vs. Temperature
6
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IRF1324S-7PPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
VGS
+
VDD -
90%
D.U.T VGS
Second Pulse Width < 1s Duty Factor < 0.1%
10%
VDS
td(off) tf td(on) tr
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K 20K
S
VCC
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRF1324S-7PPBF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
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IRF1324S-7PPBF
D2Pak - 7 Pin Part Marking Information
14
D2Pak - 7 Pin Tape and Reel
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/06
9

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