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CY7C128A
2K x 8 Static RAM
Features
* Automatic power-down when deselected * CMOS for optimum speed/power * High speed -- 15 ns * Low active power -- 660 mW (commercial) * Low standby power -- 110 mW (20 ns) * TTL-compatible inputs and outputs * Capable of withstanding greater than 2001V electrostatic discharge * Available in Pb-free and non Pb-free 24-pin Molded SOJ, non Pb-free 24-pin (300-Mil) Molded DIP
Functional Description
The CY7C128A is a high-performance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), and active LOW Output Enable (OE) and tri-state drivers. The CY7C128A has an automatic power-down feature, reducing the power consumption by 83% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the eight I/O pins (I/O0 through I/O7) is written into the memory location specified on the address pins (A0 through A10). Reading the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ Top View
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 24 23 2 22 3 4 21 5 20 6 19 7C128A 18 7 17 8 9 16 10 15 11 14 12 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
INPUT BUFFER
I/O0 I/O1
ROW DECODER
A10 A9 A8 A7 A6 A5 A4 CE WE OE
I/O2
SENSE AMPS 128 x 16 x 8 ARRAY
I/O3 I/O4 I/O5
C128A-2
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A3
A2
A1
A0
C128A-1
Cypress Semiconductor Corporation Document #: 38-05028 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY7C128A
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -15 15 120 40 -20 20 120 20 -35 35 120 20 -45 45 120 20
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range[2]
-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current Automatic CE Power-Down Current GND < VI < VCC GND < VI < VCC Output Disabled VCC = Max. IOUT = 0 mA Max. VCC, CE > VIH, Min. Duty Cycle = 100% Max. VCC, CE1 >VCC -0.3V, VIN > VCC-0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -10 -10 Min. 2.4 0.4 VCC 0.8 +10 +10 120 40 2.2 -0.5 -10 -10 Max. Min. 2.4 0.4 VCC 0.8 +10 +10 120 40 2.2 -0.5 -10 -10 -20 Max. -35, -45 Min. 2.4 0.4 VCC 0.8 +10 +10 120 20 Max. Unit V V V V A A mA mA
ISB2
40
20
20
mA
Notes: 1. TA is the "instant on" case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. VIL (min.) = -3.0V for pulse durations less than 30 ns.
Document #: 38-05028 Rev. *A
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CY7C128A
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 R1 481 5V OUTPUT GND 5 pF INCLUDING JIG AND SCOPE R2 255 R1 481 3.0V 10% ALL INPUT PULSES 90% 90% 10% 5 ns
C128A-5
5 ns
(a)
(b)
C128A-4
Equivalent to:
THEVENIN EQUIVALENT 167 1.73V
OUTPUT
Switching Characteristics Over the Operating Range[2, 5]
-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6] CE LOW to Low Z[7] Z[6, 7] 0 15 15 12 12 0 0 12 10 0 7 5 5 20 15 15 0 0 15 10 0 7 5 5 8 0 20 25 25 25 0 0 20 15 0 10 5 CE HIGH to High 3 8 5 8 0 20 40 30 30 0 0 20 15 0 15 5 15 10 3 8 5 15 0 25 15 15 5 20 10 3 12 5 15 20 20 5 35 15 3 15 35 35 5 45 20 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -20 Max. Min. -35 Max. Min. -45 Max. Unit
CE LOW to Power-Up CE HIGH to Power-Down
[8]
WRITE CYCLE
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[6] WE HIGH to Low Z
Notes: 4. Tested initially and after any design or process changes that may affect these parameters 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05028 Rev. *A
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CY7C128A
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C128A-6
Read Cycle No. 2[9, 11]
t RC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB
C128A-7
tHZOE tHZCE DATA VALID
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)[8]
tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATAIN VALID tHZWE DATA I/O DATA UNDEFINED
C128A-8
tAW tPWE
tHA
tHD
tLZWE HIGH IMPEDANCE
Notes: 9. WE is HIGH for read cycle. 10. Device is continuously selected. OE, CE = VIL. 11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05028 Rev. *A
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CY7C128A
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[8, 12, 13]
tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA IN VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED
C128A-9
tSCE
tHA
tHD
Notes: 12. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05028 Rev. *A
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CY7C128A
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 ICC NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC = 5.0V VIN = 5.0V ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA = 2 5C)
SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 TA = 25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
AMBIENT TEMPERATURE(C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA = 25C
VCC = 5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE(V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO 2.5 DELTA t AA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0
AMBIENT TEMPERATURE(C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.4 NORMALIZED ICC 1.3 1.2 1.1 1.0 0.9 0.8 0
OUTPUT SINK CURRENT (mA)
OUTPUT VOLTAGE(V) NORMALIZED I CC vs. CYCLE TIME
25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25C
VCC = 5.0V TA = 25C VIN = 0.5V
600
800 1000
10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05028 Rev. *A
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CY7C128A
Ordering Information
Speed (ns) 15 Ordering Code CY7C128A-15PC CY7C128A-15VC CY7C128A-15VXC CY7C128A-20VXC CY7C128A-35VC CY7C128A-45PC Package Diagram 51-85013 51-85030 51-85030 51-85030 51-85013 Package Type (300-Mil) Molded DIP Molded SOJ Molded SOJ Molded SOJ (Pb-free) Molded SOJ (300-Mil) Molded DIP Operating Range Commercial
20 35 45
24-pin 24-pin 24-pin 24-pin 24-pin 24-pin
Commercial Commercial Commercial
Please contact local sales representative regarding availability of these parts
Package Diagrams
24-pin (300-Mil) Molded DIP (51-85013)
51-85013-*B
Document #: 38-05028 Rev. *A
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CY7C128A
Package Diagrams (continued)
24-pin (300-mil) SOJ (51-85030)
PIN 1 ID
12
1
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088
0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89]
MIN. MAX.
PACKAGE WEIGHT 0.75gms PART #
13
24
V24.3 VZ24.3
STANDARD PKG. LEAD FREE PKG.
0.597[15.16] 0.613[15.57]
SEATING PLANE
0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48]
0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91]
51-85030-*B
Document #: 38-05028 Rev. *A
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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CY7C128A
Document History Page
Document Title: CY7C128A 2K x 8 Static RAM Document Number: 38-05028 REV. ** *A ECN NO. 106814 493543 Issue Date 09/10/01 See ECN Orig. of Change SZV NXR Description of Change Change from Spec number: 38-00094 to 38-05028 Removed 25 ns speed bin Removed Military Operating Range Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated ordering Information Table
Document #: 38-05028 Rev. *A
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