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SM5844AF
NIPPON PRECISION CIRCUITS LTD.
Asynchronous Sample Rate Converter
APPLICATIONS
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OVERVIEW
The SM5844AF is a digital audio signal, asynchronous sample rate converter LSI. It reads 16 or 20-bit word length input data, and writes 16, 18, or 20-bit word length output data. It also features a built-in digital deemphasis filter and digital attenuator. The SM5844AF operates from a 5 V supply, and is available in 44-pin QFPs.
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Digital audio equipment, sample rate conversion (audiovisual amplifiers, CD-R, DAT, MD and 8 mm VTRs) Commercial recording/editing equipment, sample rate conversion Input data jitter elimination
PINOUT
THRUN BCKO LRCO OCLK OCKSL SLAVE DOUT
DI
FEATURES
Functions
s s
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PACKAGE DIMENSIONS
Unit: mm 44-pin QFP
12.80 + 0.30 10.00
s
s s
12.80 + 0.30 -
MLEN/DEEM
OW18N
DMUTE
VDD
s
s
s s s s
0.17 + 0.05 -
0 to 0.20
NIPPON PRECISION CIRCUITS--1
1.75MAX
Left/right-channel processing (stereo) Input sample rate (fsi) ranges * 24 to 48 kHz (256fsi mode) * 27 to 55 kHz (384fsi mode) Output sample rate (fso) range * 20 to 100 kHz Sample rate conversion ratio (fso/fsi) * 0.5 to 2.0 times Asynchronous input and output timing (clock inputs) System clock inputs (input and output clocks independent) * 256fsi or 384fsi input system clock * 256fso or 384fso output system clock Deemphasis filter * IIR-type filter * 44.1, 48 or 32 kHz Digital attenuator * 11-bit data for 1025 levels * Smooth, incremental attenuation change * +12 dB gain shift function Direct mute function Through mode operation * Input to output direct Output data clocks (LRCO, BCKO) * External input (slave mode) * Output system clock generated internally (master mode) CMOS-level input/outputs 5 V (standard) single supply 44-pin QFP Molybdenum-gate CMOS process
VSS
SM5844AF
BCKI LRCI ICLK ICKSL IFM1 IFM2
RSTN TST2N TST1N STATE IISN OW20N
MCOM MDT/FSI1 MDT/FSI2
10.00
0.60 + 0.20 -
0.80
0.35 + 0.10 1.45
0 to 10
SM5844AF
Filter Characteristics and Converter Efficiency
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Interfaces
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20-bit internal data word length Deemphasis filter characteristics (IIR filter) * 0.03 dB gain deviation from ideal filter characteristics Converter noise levels * -110 dB internally-generated noise * -98 dB (16-bit output), -110 dB (18-bit output) and -122 dB (20-bit output) word rounding noise Anti-aliasing LPF characteristics (4 FIR filters) with automatic output/input sample rate conversion ratio selection * Up converter LPF (1.0 to 2.0 times) * Down converter LPF 1 (48.0 to 44.1 kHz or 0.92 times) * Down converter LPF 2 (44.1 to 32.0 kHz or 0.73 times) * Down converter LPF 3 (48.0 to 32.0 kHz or 0.67 times) Output S/N ratio (theoretical values)
S/N ratio Output signal word length 16 bits 18 bits 20 bits 16-bit input word length 94.8 dB 97.5 dB 97.7 dB 20-bit input word length 97 dB
Input data format * 2s-complement, L/R alternating, serial * Normal format (non IIS)
Mode 1 2 3 4 20 bits Front Rear LSB first W ord length 16 bits Rear M S B fi rst Front/rear p a cking Data sequence
s
Output data format * 2s-complement, MSB first, L/R alternating, serial * Continuous bit clock
Mode 1 2 3 4 5 6 W ord length 16 bits 18 bits 20 bits 20 bits 16 bits Front 18 bits 20 bits IIS 7 Nor mal (non IIS) Rear IIS selection Front/rear p a cking
106 dB 109 dB
NIPPON PRECISION CIRCUITS--2
SM5844AF
BLOCK DIAGRAM
IFM1 IFM2 BCKI DI
MCOM MDT/FSI1 MCK/FSI2 MLEN/DEEM Deemphasis and attenuator setup
Input data interface
Arithmetic operations ICLK ICKSL
Input-stage divider
Deemphasis operation
LRCI RSTN
Input timing controller
Attenuator
Filter characteristic select
Interpolation filter operation
TST1N TST2N Output operation timing controller Output operation
OW18N OW20N IISN Output format controller
Dither Output data interface
SLAVE
Output-stage clock select
LRCI BCKI
DI
OCLK OCKSL
Output-stage divider
Through mode switching
THRUN DMUTE Mute generator Direct mute
STATE
LRCO
BCKO
DOUT
NIPPON PRECISION CIRCUITS--3
SM5844AF
PIN DESCRIPTION
Number1 1, 2 3, 4 5 6 7 Name DI BCKI LRCI3 ICLK ICKSL I/O 2 Ip Ip Ip I Ip Data input Input bit clock Input word clock (fsi) Input system clock input Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW . Input format select 8, 9 IFM1 Ip IFM1 LOW LOW 10, 11 IFM2 Ip HIGH HIGH 12, 13 14, 15 16 VDD DMUTE MCOM - Ip Ip 5 V supply pin Direct mute pin Interface switch control pin. M D T, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM control when LOW . W h e n M C O M i s H I G H : Microcontroller interface data input (MDT) W h e n M C O M i s L OW : Deemphasis frequency set pins FSI1 LOW 18 MCK/FSI2 Ip W h e n M C O M i s H I G H : Microcontroller interface bit clock (MCK) x HIGH FSI2 HIGH LOW HIGH fsi 48.0 kHz 44.1 kHz 32.0 kHz IFM2 LOW HIGH LOW HIGH 20 bits LSB first W ord length 16 bits Rear packed M S B fi rst Front packed Rear packed Data sequence Data position Description
17
MDT/FSI1
Ip
19, 20
MLEN/DEEM
Ip
W h e n M C O M i s H I G H : Microcontroller data word latch clock (MLEN) W h e n M C O M i s L OW : Deemphasis ON/OFF control (DEEM) Output format select When IISN = HIGH (nor mal mode) OW20N OW18N LOW 20 bits LOW HIGH HIGH When IISN = LOW (IIS mode) OW20N LOW OW18N LOW 20 bits LOW HIGH HIGH HIGH LOW HIGH 18 bits 16 bits IIS mode Front packed W ord length Data position HIGH LOW HIGH 18 bits 16 bits Rear packed W ord length Data position Front packed
21, 22
OW18N
Ip
LOW
23, 24
OW20N
Ip
25, 26 27 28 29
IISN S TAT E TST1N TST2N
Ip O Ip Ip
IIS output mode select. Normal mode when HIGH, and IIS mode when LOW . Internal operation status output (for operation check) Output dither control. Dither ON when LOW , and OFF when HIGH. Test pin. Test mode when LOW . Normal operating mode when HIGH.
NIPPON PRECISION CIRCUITS--4
SM5844AF
Number1 30, 31 32, 33 34, 35 36, 37 38 39 40 41, 42 43, 44 Name RSTN VSS S L AV E THRU N OCKSL OCLK LRCO3 B C KO DOUT I/O 2 Ip - Ip Ip Ip I I/O I/O O Reset pin 0 V ground pin B C K O and LRCO mode set. Outputs (master mode) when LOW , and inputs (slave mode) when HIGH. DOUT through mode set. Normal mode when HIGH, and through mode when LOW . Output system clock (OCLK) select. 384fso when HIGH, and 256fso when LOW . Output system clock input Output word clock input/output (fso). Input/output mode set by the level on SLAVE. Output bit clock input/output. Input/output mode set by the level on SLAVE. Data output Description
1. Pins which have the same name are connected internally. Accordingly, circuit connections can be made to either pin or to both pins. 2. I = input, Ip = Input with pull-up resistor (HIGH-level pins can be left open), O = output, I/O = input/output 3. fsi is the input word clock (LRCI) frequency, and fso is the output word clock (LRCO) frequency.
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0 V
P arameter Supply voltage range Input voltage range Storage temperature range Pow er dissipation Soldering temperature Soldering time Symbol VDD V IN T stg PD T sld tsld Rating -0.3 to 7.0 -0.3 to V D D + 0.3 -40 to 125 550 255 10 Unit V V C mW C s
Recommended Operating Conditions
VSS = 0 V
P arameter Supply voltage range Operating temperature range Symbol VDD T opr Rating 4.75 to 5.5 -20 to 70 Unit V C
NIPPON PRECISION CIRCUITS--5
SM5844AF
DC Electrical Characteristics
VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = -20 to 70 C
P arameter Current consumption HIGH-level input voltage 2 ,3 voltage 2 voltage 4 L O W -level input voltage 2 ,3 A C-coupled input HIGH-level output voltage 4 L O W -level output HIGH-level input current 2 L O W -level input current 2 ,3 Input leakage current 3 Pull-up resistance 3 Symbol ID D V IH V IL V A CI VOH VOL IIH IIL IL H R IH IO H = -1.0 mA IO L = 1.0 mA V IN = V D D V IN = 0 V V IN = V D D Condition V D D = 5.0 V 1 Rating min - 0.7V D D - 0.3V D D V D D - 0.5 - - - - 250 typ - - - - - - 10 10 - 500 max 80 - 0.3V D D - - 0.4 20 20 1.0 1000 Unit mA V V V p-p V V A A A k
1. ICKSL = LOW , OCKSL = LOW , fI C L K = 13.0 MHz, f O C L K = 13.0 MHz, no output load 2. Pins ICLK and OCLK. 3. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW 1 8 N , OW20N, IISN, TST1N, T S T 2 N , R S T N , T H R U N , O C K S L a n d S L AVE. 4. P i n s D O U T, BCKO , LRCO and STATE.
AC Electrical Characteristics
VDD = 4.75 to 5.5 V, VSS = 0 V, Ta = -20 to 70 C ICLK input
P arameter L O W -level clock pulsewidth HIGH-level clock pulsewidth Clock pulse cycle Symbol Condition ICKSL LOW HIGH LOW HIGH LOW HIGH System clock 256fsi 384fsi 256fsi 384fsi 256fsi 384fsi min 30 10 30 10 80 47 Rating typ - - - - - - max - - - - 162 106 Unit
tC W L tC W H tC Y
ns
ns
ns
OCLK input
P arameter L O W -level clock pulsewidth HIGH-level clock pulsewidth Clock pulse cycle Symbol Condition OCKSL LOW HIGH LOW HIGH LOW HIGH System clock 256fso 384fso 256fso 384fso 256fso 384fso min 15 10 15 10 39 26 Rating typ - - - - - - max - - - - 200 130 Unit
tC W L tC W H tC Y
ns
ns
ns
ICLK and OCLK timing
>0.7VDD ICLK OCLK t CWH t CY t CWL 0.5VDD <0.3VDD
NIPPON PRECISION CIRCUITS--6
SM5844AF BCKI, DI, LRCI inputs
Rating P arameter B C K I L OW -level pulsewidth BCKI HIGH-level pulsewidth BCKI pulse cycle DI setup time DI hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tB C W L 1 tB C W H 1 tB C Y 1 tD S tD H tB L 1 tL B 1 50 50 100 50 50 50 50 typ - - - - - - - max - - - - - - - ns ns ns ns ns ns ns Unit
BCKI, DI, LRCI timing
t BCY1 t BCWH1 t BCWL1
BCKI
0.5VDD
t DS
t DH
DI
0.5VDD
t BL1
t LB1
LRCI
0.5VDD
BCKO, LRCO (Inputs when SLAVE = HIGH)
Rating P arameter B C K O L OW -level pulsewidth B C K O HIGH-level pulsewidth B C K O pulse cycle 1 Symbol min tB C W L 2 tB C W H 2 tB C Y 2 tB L 2 tL B 2 78 78 156 78 78 typ - - - - - max - - - - - ns ns ns ns ns Unit
Last BCKO rising edge to LRCO edge LRCO edge to first BCKO rising edge
1. B C KO clock inputs exceeding 64fso cannot be detected, and will cause incorrect operation.
NIPPON PRECISION CIRCUITS--7
SM5844AF
BCKO, LRCO timing
t BCY2 t BCWH2 t BCWL2
BCKO
0.5VDD
t BL2
t LB2
LRCO
0.5VDD
MDT, MCK, MLEN inputs
Rating P arameter M C K a n d M L E N r ise time 1 MCK and MLEN fall time 1 MDT setup time MDT hold time MLEN setup time MLEN hold time M L E N L OW -level pulsewidth MLEN HIGH-level pulsewidth Symbol min tr tf tM D S tM D H tM C S tM C H tM E W L tM E W H - - 50 50 50 50 50 50 typ - - - - - - - - max 100 100 - - - - - - ns ns ns ns ns ns ns ns Unit
1. tr and t f are the input waveform transition times measured between 0.1V D D and 0.9V D D levels.
MDT, MCK, MLEN timing
MDT
0.5VDD
t MDS
t MDH
MCK
0.5VDD
t MCS
t MCH
MLEN
0.5VDD
t MEWL
t MEWH
NIPPON PRECISION CIRCUITS--8
SM5844AF DEEM, DMUTE inputs
Rating P arameter Rise time Fall time Symbol min tr tf - - typ - - max 100 100 ns ns Unit
DOUT, BCKO, LRCO input/outputs SLAVE = LOW (outputs), CL = 15 pF
Rating P arameter LRCO pulse cycle L R C O L OW -level pulsewidth LRCO HIGH-level pulsewidth B C K O pulse cycle Symbol tL O C Y tL O C L tL O C H O C K S L = L OW tB O C Y OCKSL = HIGH O C K S L = L OW B C K O L OW -level pulsewidth tB O W L OCKSL = HIGH O C K S L = L OW B C K O HIGH-level pulsewidth tB O W H ts b H 1 tsbL1 ts b H 2 tsbL2 tb d H 1 tb d L 1 OCKSL = HIGH From OCLK fall to BCKO rise From OCLK fall to BCKO fall From OCLK fall to BCKO rise From OCLK fall to BCKO fall Fr o m B C KO fall to DOUT rise Fr o m B C KO fall to DOUT fall Condition min - - - - - - - - - 10 10 15 15 0 0 typ 1/fso 1/2fso 1/2fso 1/64fso 1/48fso 1/128fso 1/96fso 1/128fso 1/96fso - - - - - - max - - - - ns - - ns - - ns - 70 70 80 80 20 20 ns ns ns ns ns ns ns ns ns Unit
O C L K t o B C KO delay time ( O C K S L = L OW )
O C L K t o B C KO delay time (OCKSL = HIGH)
B C K O to DOUT and LRCO delay time
SLAVE = HIGH (inputs), CL = 15 pF
Rating P arameter Symbol Condition min tb d H 2 B C K O to DOUT delay time tb d L 2 Fr o m B C KO fall to DOUT fall 10 - 100 ns Fr o m B C KO fall to DOUT rise 10 typ - max 100 ns Unit
NIPPON PRECISION CIRCUITS--9
SM5844AF
DOUT, BCKO, LRCO timing
OCLK
BCKO
t sbL1, t sbL2 t BOWH t BOCY
t sbH1, t sbH2 t BOWL
BCKO
t bdH, t bdL
DOUT
t bdH
t bdL
LRCO
t LOCH t LROOY
t LOCL
NIPPON PRECISION CIRCUITS--10
SM5844AF
Filter Characteristics
Anti-aliasing filter frequency characteristic
0 48k 44.1k
20 48k 40 32k
44.1k Attenuation (dB) 60
32k
Up conversion
80
100
120
140 0.250
0.300
0.350
0.400
0.450 Frequency (fs)
0.500
0.550
0.600
0.650
Deemphasis filter frequency characteristic
0
2
-20
4 Attenuation (dB)
-40
6 48.0, 44.1 and 32 kHz 8
-60
10 Phase 12 10 20 50 100 200 500 1k Frequency (Hz) 2K 5k 10k 20k Attenuation
NIPPON PRECISION CIRCUITS--11
Phase characteristic, ()
48.0 kHz 44.1 kHz 32 kHz
0
SM5844AF
FUNCTIONAL DESCRIPTION
Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2)
Mode 1 2 3 4 IFM1 LOW LOW HIGH HIGH IFM2 LOW HIGH LOW HIGH 20 bits Front packed Rear packed LSB first W ord length 16 bits Rear packed M S B fi rst Non IIS L/R alternating Bit serial Data position Data sequence C o m m o n f eatures
Attenuator and Deemphasis Selection
The attenuator is set using the microcontroller interface. When the attenuator is used, deemphasis settings also need to be set using the microcontroller interface. The microcontroller interface comprises MDT, MCK and MLEN, and is used to receive all input serial data.
Table 1. Attenuator and deemphasis function selection
Function set method Function External pins ( M C O M = L OW ) Microcontroller interface flags (MCOM = HIGH) FDEEM
Deemphasis ON/OFF Deemphasis frequency (fsi) select Attenuator data set Test mode select
DEEM
FSI1, FSI2
FFSI1, FFSI2
N/A (no attenuation) Irreversible (test mode 1)
11 bits (a1 to a11) FTST1, FTST2
When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control flag data. When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function.
NIPPON PRECISION CIRCUITS--12
SM5844AF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock) and MLEN (latch enable clock) interface pins are used. Input data on MDT is synchronized to the MCK clock. Data is read into the input stage shift register on the rising edge of MCK. Accordingly, the input data should change on the falling edge of MCK. Input data enters an internal SIPO (serial-to-parallel converter register), and then the parallel data is latched into the mode register on the rising edge of the latch enable clock MLEN. The mode register addressed is determined by the 1st bit of the 12 data bits before MLEN goes HIGH. If this bit is LOW, then the data is read into the attenuation data register as shown in figure 1. If this bit is HIGH, then the data is read into the mode flag register as shown in figure 2. The function of each bit in the mode flag register is described in table 1.
B1 MDT LOW
B2 a0 MSB
B3 a1
B4 a2
B8 a6
B9 a7
B10 a8
B11 a9
B12 a10 LSB
MCK
MLEN MCK and MLEN can also follow the dotted lines.
Figure 1. Attenuation data format (B1 = LOW)
B1 MDT HIGH B2 ** B5 B6 FTST1 B7 FTST2 B8 FRATE B9 F12DB B10 FFSI1 B11 FFSI2 B12 FDEEM
Not used
MCK
MLEN MCK and MLEN can also follow the dotted lines.
Figure 2. Mode flag data format (B1 = HIGH)
NIPPON PRECISION CIRCUITS--13
SM5844AF
Table 2. Mode flag description
Mode function select B1 Bit B2 to B5 M o d e fl ag P arameter Not used T S T 2 N = L OW B6 FTST1 Test mode select 1 FTST2 LOW LOW B7 FTST2 Test mode select 2 HIGH HIGH FTST1 LOW HIGH LOW HIGH Mode 0 1 2 3 LOW LOW L OW/HIGH Select Reset mode
LOW B8 HIGH LOW B9 F12DB Attenuator HIGH F R AT E Input/output rate HIGH
Input/output sample rate ratio check after every output LOW Input/output sample rate ratio check for high accuracy after every 2048 outputs Nor mal operation (no shift) LOW +12 dB gain shift
B10
FFSI1
Deemphasis filter fs select 1
FFSI2 LOW LOW
FFSI1 LOW
fsi 44.1 kHz
LOW
HIGH LOW HIGH 48.0 kHz 32.0 kHz LOW
B11
FFSI2
Deemphasis filter fs select 2
HIGH HIGH LOW HIGH
B12
FDEEM
Deemphasis control ON/OFF
Deemphasis filter OFF LOW Deemphasis filter ON
Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags)
The digital deemphasis filter is an IIR filter with variable coefficients to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The filter coefficients are selected by FSI1 (or FFSI1 flag) and FSI2 (or FFSI2 flag) to correspond to the sampling frequencies fs = 44.1, 48.0 and 32.0 kHz.
Table 3. Deemphasis ON/OFF
W h e n M C O M = L OW DEEM = HIGH D E E M = L OW When MCOM = HIGH FDEEM = HIGH F D E E M = L OW Deemphasis ON OFF
Table 4. Deemphasis fs select (FSI1, FSI2 pins or FFSI1, FFSI2 flags)
M C O M = L OW ( M C O M = H I G H ) fs FSI1 (FFSI1) LOW HIGH LOW HIGH FSI2 (FFSI2) LOW 44.1 kHz LOW HIGH HIGH 48.0 kHz 32.0 kHz
NIPPON PRECISION CIRCUITS--14
SM5844AF
Attenuation (MDT, MCK, MLEN)
The digital attenuator coefficients are read in as serial data on the microcontroller interface. Data on MDT is read into the internal shift register on the rising edge of MCK, and then 12 bits are latched internally on the rising edge of MLEN. When the leading bit is 0 (B1 = LOW), the following 11 bits are read into the attenuation register and used as an unsigned integer in MSB first format. See figure 3.
B1 MDT LOW
B2 a0 MSB
B3 a1
B4 a2
B8 a6
B9 a7
B10 a8
B11 a9
B12 a10 LSB
MCK
MLEN MCK and MLEN can also follow the dotted lines.
Figure 3. Attenuation data format (microcontroller interface) Although the attenuation data comprises 11 bits, only 1025 levels are valid as given by the following. DATT = DATT Gain = 20 x log --------------- [dB] 1024 when F12DB = LOW DATT = 20 x log --------------- [dB] 256 when F12DB = HIGH After a system reset initialization, DATT is set to 400H and the F12DB flag is LOW, corresponding to 0 dB gain. (The F12DB flag is described in table 2.)
Table 5. Attenuator settings
F 1 2 D B = L OW (default) Attenuation data DAT T Gain (dB) 000H 001H 100H 3FFH 400H (to 7FFH) - -60.206 -12.041 -0.0085 0 Linear expression 0.0 1/1024 256/1024 1023/1024 1.0 Gain (dB) - -48.165 0.0 12.032 12.041 Linear expression 0.0 1/256 256/256 1023/256 4.0 F12DB = HIGH
i=0
10
ai x 2
( 10 - i )
The gain of the attenuator for values of DATT from 001H to 400H are given by the following equations. Note that when the F12DB flag is HIGH, the gain is shifted by +12.0412 dB.
NIPPON PRECISION CIRCUITS--15
SM5844AF Attenuator operation A change in the attenuation data DATT causes the gain to change smoothly from its previous value towards the new setting. The new attenuation data is stored in the attenuation data register and the current attenuation level is stored in a temporary register. Consequently, if a new attenuation level is read in before the previously set level is reached, the gain changes smoothly from the current value towards the latest setting as shown in figure 4. The attenuation counter output changes, and hence the gain changes, by 1 step every output sample. The time taken to reduce the gain from 0 dB (or 12 dB) to - dB is (1024/fso), which corresponds to approximately 23.2 ms when fso = 44.1 kHz.
Level 1 0 dB Level 3
Level 5
Gain Level 2 - t Level 4 Time
Figure 4. Attenuator operation example
NIPPON PRECISION CIRCUITS--16
SM5844AF
Direct Mute (DMUTE)
Direct mute ON/OFF
Table 6. DMUTE operation
DMUTE LOW HIGH Function Nor mal data is output from the next output word (mute OFF) 0 data is output from the next output word (mute ON)
Reset mute
Table 7. RSTN mute operation
RSTN LOW HIGH Function 0 data is output from the next output word (mute ON) Nor mal data is output from the 3073rd output word ( m ute OFF)
Internal operating status (STATE) Internally, all functions are performed using 20-bit serial data, and the conversion rate and filter type are
Table 8. Bit function
Output bit position Content (Output data cycle/input data cycle) - 9 Ex. 1st 18th 00.1111111111110111 1.0 times 01.1111111111110111 2.0 times (1/2 conversion rate ratio) 00.0111111111110111 0.5 times (2.0 conversion rate ratio) DA1 Selected filter type DA1 0 20th DA0 1 0 1 DA0 0 0 1 1 Up converter 44.1 to 48 kHz 32 to 44.1 kHz 32 to 48 kHz Filter Mode 1 2 3 4
automatically selected for output. Output data is in 20-bit front-packed format.
1st to 18th
19th
Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output.
NIPPON PRECISION CIRCUITS--17
SM5844AF
System Clock
Input system clock (ICLK, ICKSL) The input system clock can be set to run at either 256fsi or 384fsi, where fsi is the input frequency on LRCI. Note that ICLK and LRCI should be divided from a common clock source or PLL to maintain synchronism.
Table 9. ICLK system clock
ICKSL HIGH LOW ICLK system clock rate 384fsi 256fsi
Output system clock (OCLK, OCKSL) The output system clock can be set to run at either 256fso or 384fso, where fso is the input frequency on LRCO. In through mode, OCLK and OCKSL have no function and are not used. Note that in slave mode, a suitable clock must be input on OCLK. The clock on OCLK should ideally have a protection circuit to prevent incorrect operation for times when the clock on ICLK is halted.
Table 10. OCLK system clock
S L AV E LOW LOW HIGH x 256fso Not used OCKSL HIGH O C L K s y s t e m clock rate 384fso
Output data interface and output clock selection (LRCO, BCKO, DOUT, SLAVE)
Table 11. Output mode description
Function THRUN S L AV E Mode LOW HIGH HIGH Slave mode Output word clock (LRCO) and output bit clock ( B C KO) are supplied externally. Output word clock (LRCO), output bit clock ( B C KO) and output data (DOUT) are the same as LRCI, BCKI and DI, respectively. Inputs 1 Master mode Description Output word clock (LRCO) and output bit clock ( B C KO) are divided from OCLK. L R C O , B C KO state Outputs
LOW
x
Through mode
Outputs
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
System Reset (RSTN)
At power-ON, all device functions must be reset. The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation, output timing counter and internal flag register operation are synchronized on the next LRCI rising edge. Note that all flags are set to their defaults (all LOW). A power-ON reset signal can be applied from an external microcontroller. For systems where ICLK and LRCI are stable at power ON, initialization can be performed by connecting a 0.001 F capacitor between RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after LRCI and ICLK have stabilized.
Through Mode (THRUN)
Table 12. THRUN operation
THRUN Mode Description Direct connections are made: LRCI to LRCO, BCKI to BCKO , and DI to D O U T. Sample rate converter operation
LOW
Through mode
HIGH
Nor mal mode
NIPPON PRECISION CIRCUITS--18
SM5844AF
Internal Arithmetic Timing Auto-reset
The clock on LRCI should pass through 1 cycle for every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW) ICLK clock cycles to maintain correct internal arithmetic sequence. If the number of ICLK cycles is different, increases or decreases, or any jitter is present, device operation could be affected. There is a fixed-value tolerance within which the internal sequence and LRCI clock timing are not adversely affected.
Table 13. Clock tolerance
ICKSL HIGH (384fs mode) L O W (256fs mode) Allow a b le clock variation +8/-6 cycles +4/-3 cycles
Output Timing Calculation
The output timing is calculated to maintain the desired ratio between the output data cycle and the input data cycle.
Filter Characteristic Selection
Conversion rates from 0.5 to 2.0 times are supported using the following 4 filter types. The ratio between the output sample rate and input sample rate is measured automatically and the most suitable filter type for this ratio is selected automatically.
Table 15. fs ratio and filter selection
Mode 1 Filter Up converter 48.0 to 44.1 kHz 44.1 to 32.0 kHz 48.0 to 32.0 kHz fs ratio (fso/fsi) 1.0 to 2.0 0.91875 0.72562 0.66667 Selects range 0.97 0.865 to 0.97 0.711 to 0.865 0.711
Whenever the allowable tolerance is exceeded, the internal sequence is automatically reset so that the internal sequence matches the LRCI clock. When this occurs, there is a possibility that click noise will be generated.
2 3 4
Output Format Control (OW18N, OW20N, IISN)
The output is in MSB-first, 2s-complement, L/R alternating, bit serial format with a continuous bit clock.
Table 14. Output format selection
Inputs Mode 1 2 3 4 5 6 7 LOW HIGH IISN OW20N OW18N HIGH HIGH LOW LOW HIGH HIGH LOW HIGH LOW HIGH LOW HIGH LOW x W ord length 16 bits 18 bits 20 bits 20 bits 16 bits 18 bits 20 bits IIS Front Non IIS Rear Output format IIS selection Front/rear p a cking
When the selected fs conversion ratio and the actual sample rate conversion ratio do not coincide, the following phenomenon are generated.
Table 16. fs ratio mismatch
Condition Actual sample rate conversion ratio is low er than the selected filter conversion ratio Actual sample rate conversion ratio is higher than the selected filter conversion ratio Affect The audio band high-pass develops aliasing noise.
The audio band high-pass is cut off.
Note: An output noise may be generated if the fs conversion ratio changes at a rate greater than 0.057%/sec.
NIPPON PRECISION CIRCUITS--19
SM5844AF
TIMING DIAGRAMS
Input Timing Examples (DI, BCKI, LRCI)
Audio data input timing (rear-packed 16-bit word, IFM1 = LOW, IFM2 = LOW)
1/fs Left-channel data MSB DI 1 2 14 15 LSB 16 MSB 1 2 14 15 Right-channel data LSB 16
BCKI
LRCI
Audio data input timing (rear-packed 20-bit word, IFM1 = LOW, IFM2 = HIGH)
1/fs Left-channel data MSB DI 1 2 18 19 LSB 20 MSB 1 2 18 19 Right-channel data LSB 20
BCKI
LRCI
Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW)
1/fs Left-channel data MSB DI 1 2 3 19 LSB 20 MSB 1 2 3 19 Right-channel data LSB 20 1
BCKI
LRCI
All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required.
NIPPON PRECISION CIRCUITS--20
SM5844AF Audio data input timing (rear-packed 20-bit word, LSB first, IFM1 = HIGH, IFM2 = HIGH)
1/fs Left-channel data LSB DI 1 2 18 19 MSB 20 LSB 1 2 18 19 Right-channel data MSB 20
BCKI
LRCI
Output Timing Examples (DOUT, BCKO, LRCO)
Audio data output timing (rear-packed 16-bit word)
1/fso Left-channel data MSB DOUT 1 2 15 LSB 16 MSB 1 2 15 Right-channel data LSB 16
BCKO
LRCO
Audio data output timing (rear-packed 18-bit word)
1/fso Left-channel data MSB DOUT 1 2 17 LSB 18 MSB 1 2 17 Right-channel data LSB 18
BCKO
LRCO
Audio data output timing (rear-packed 20-bit word)
1/fso Left-channel data MSB DOUT 1 2 19 LSB 20 MSB 1 2 19 Right-channel data LSB 20
BCKO
LRCO
NIPPON PRECISION CIRCUITS--21
SM5844AF Audio data output timing (front-packed 20-bit word, OW18N = LOW, OW20N = LOW)
1/fso Left-channel data MSB DOUT 1 2 19 LSB 20 MSB 1 2 19 Right-channel data LSB 20
BCKO
LRCO
Audio data output timing (IIS mode, front-packed 16/18/20-bit word selected by OW18N and OW20N)
1/fso Left-channel data MSB DOUT 1 2 16 17 18 19 LSB 20 MSB 1 2 16 17 18 19 Right-channel data LSB 20
BCKO
LRCO
Data is output in 20-bit units.
State Data Output Timing
State data output timing (IISN = HIGH)
1/fso State data MSB STATE 1 2 19 LSB 20
BCKO
LRCO
State data output timing (IISN = LOW)
1/fso State data MSB STATE 1 2 19 LSB 20
BCKO
LRCO
NIPPON PRECISION CIRCUITS--22
SM5844AF
Delay Time
tINPUT is the time when the serial input data has been read in completely (on the rising edge of LRCI). tOUTPUT is the time when the serial output data has been read out completely (on the rising edge of LRCO). The delay between input and output is given by tOUTPUT - tINPUT = (49 2)/fsi.
1/fs LRCI Serial data input t input LRCO
1/fso
49 2
Serial data output t output
t INPUT
t OUTPUT - t INPUT
t OUTPUT
NIPPON PRECISION CIRCUITS--23
SM5844AF
TYPICAL APPLICATIONS
Input Interface Circuits
Digital audio interface receiver (PD0052)
VCOOUT
384fs
ICLK ICKSL
LRCK BCK
LRCI BCKI DI MCOM MLEN/DEEM MDT/FSI1 1FM1 1FM2
DIR PD0052
DATA MODE EMP
SM5844AF
32k
44.1k
48k
MCK/FSI2
Digital audio interface transceiver(YM3613)
OCKSL OCLK LRCO BCKO 384fs 16.9344 MHz oA WCI BCI DIN
SM5844AF
DOUT IISN OW18N OW20N THRUN SLAVE
DIT YM3613
SEL
NIPPON PRECISION CIRCUITS--24
SM5844AF
APPLICATION NOTE
Delay in the slave mode In the slave mode , the delay (tbdH2, tbdL2)of DUOT from BCKO is MIN= 10ns, MAX= 100ns which is ratter wide width. As specified in AC Electrical Characteristics, and BCKO is prohibited from inputting longer than 64fso. When tbdH2, tbdL2 is maximum 100ns, ideal timing may not be attained for the following devise, depending on the OCLK cycle (example 1). Please use considering the timing in the following examples in the slave mode.
(example 1) OCLK= 39ns(fs= 99.84kHz), OCKSL= L(256fs), BCKO(64fso)= 156ns, OW20N= L, OW 1 8 N = H
LRCO
BCKO (LSB) DOUT 100ns 156ns L2 100ns L1
(example 2) OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N= L, OW 1 8 N = H
LRCO
BCKO (LSB) DOUT 100ns 354ns L2 L1 100ns
NIPPON PRECISION CIRCUITS--25
SM5844AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9308DE 2000.09
NIPPON PRECISION CIRCUITS LTD.
NIPPON PRECISION CIRCUITS--26

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