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| AND8048/D SPICE Device Model NTHD5905T1 Dual P-Channel 1.8 V (G-S) MOSFET http://onsemi.com APPLICATION NOTE CHARACTERISTICS DESCRIPTION * * * * * * P-Channel Vertical DMOS Macro-Model (Sub-circuit) Level 3 MOS Applicable for both Linear and Switch Mode Applicable over a -55 to 125C Temperature Range Models Gate Charge, Transient, and Diode Reverse Recovery Characteristics The attached SPICE Model describes typical electrical characteristics of the p-channel vertical DMOS. The sub-circuit model was extracted and optimized over a 25C to 125C temperature range under pulse conditions for 0 to -5 volts gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gate-to-drain feedback capacitor network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measure electrical data and are not intended as an exact physical description of a device. D 4 M R M G CGS 1 2 3 DB S Figure 1. Model Sub-circuit This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. (c) Semiconductor Components Industries, LLC, 2001 1 April, 2001 - Rev. 0 Publication Order Number: AND8048/D AND8048/D MODEL EVALUATION P-CHANNEL DEVICE (TJ = 25C unless otherwise noted) Characteristic Static Gate Threshold Voltage On-State Drain Current (Note 1.) Drain-Source On-State Resistance (Note 1.) VGS(th) ID(on) rDS(on) VDS = VGS, ID = -250 mA VDS -5.0 V, VGS = 4.5 V VGS = -4.5 V, ID = -3.0 A VGS = -2.5 V, ID = -2.5 A VGS = -1.8 V, ID = -1.0 A VDS = 5.0 V, ID = 3.0 A IS = -0.9 A, VGS = 0.0 V 0.83 36 0.080 0.110 0.142 7.6 -0.80 V A W S V Symbol Test Conditions Typical Unit Forward Transconductance (Note 1.) Diode Forward Voltage (Note 1.) Dynamic (Note 2.) Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time 1. Pulse test: pulse width 300 ms, duty cycle 2%. 2. Guaranteed by design, not subject to production testing. gfs VSD Qg Qgs Qgd td(on) tr td(off) tf trr IF = -0.9 A, di/dt = 100 A/ms VDD = -4.0 V, RL = 4.0 W, ID ^ -1.0 A, VGEN = -4.5 V, RG = 6.0 W VDS = -4.0 V, VGS = -4.5 V, ID = -3.0 A 35 0.5 1.5 13 19 24 12 28 ns nC http://onsemi.com 2 AND8048/D 10 VGS = 2.5 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 8 VGS = 3 V VGS = 3.5 V VGS = 5 V 8 10 125C -55C 6 VGS = 2 V 6 4 4 25C 2 VGS = 1.5 V 0 0 0.5 1 1.5 2 2.5 3 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 2 0 0 0.5 1 1.5 2.0 2.5 3 VGS, GATE-TO SOURCE (V) Figure 2. Drain Current vs. Drain-to-Source Voltage Figure 3. Drain Current vs. Gate-to-Source Voltage 4.0 SQRT (IDsat) 3.2 SQRT (IDsat) (A) 1.0 RDS(on), ON-RESISTANCE () RDS(on), ON-RESISTANCE () 0.30 0.25 VGS = 1.8 V 0.20 0.15 VGS = 4.5 V 0.10 0.05 0.00 0 2 4 6 8 10 ID, DRAIN CURRENT (A) VGS = 4.5 V 0.8 2.4 0.6 1.6 0.4 0.8 RDS(on) 0.2 0.0 0 1 2 3 4 VGS, GATE-TO SOURCE VOLTAGE (V) 0.0 5 Figure 4. Sqrt vs. Gate-to-Source Voltage Figure 5. On-Resistance vs. Drain Current 1000 4.0 VGS 5 800 CAPACITANCE (pF) Ciss 600 3.2 VDS 4 2.4 VDS (V) 3 VGS (V) 400 Coss 200 Crss 0 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 1.6 2 0.8 2 0.0 0 1 2 3 Qg (nC) 4 5 6 0 Figure 6. Capacitance vs. Drain-to-Source Voltage Figure 7. VDS vs. Qg http://onsemi.com 3 AND8048/D H-SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 RTEMP 18E-3 CGS 1 2 540E-12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E-8 +RS = 45E-3 RD = 0 NSUB = 0.67E16 +KP = 4.7E-5 UO = 400 +VMAX = 0 XJ = 5E-7 KAPPA = 20E-3 +ETA = 1E-4 TPG = -1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +TLEV = 1 BEX = -1.5 TCV = 1.5E-3 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E-8 +NSUB = 16E16 NSF = 10E11 TPG = -1) ******************************************************************************************* .MODEL DBD D (CJO = 200E-12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E-8 TT = 9E-8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E-3 TC2 = 5.5E-6) ******************************************************************************************* .ENDS http://onsemi.com 4 AND8048/D P-SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 RTEMP 18E-3 CGS 1 2 540E-12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E-8 +RS = 45E-3 RD = 0 NSUB = 0.67E16 +KP = 4.7E-5 UO = 400 +VMAX = 0 XJ = 5E-7 KAPPA = 20E-3 +ETA = 1E-4 TPG = -1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E-8 +NSUB = 16E16 NSF = 10E11 TPG = -1) ******************************************************************************************* .MODEL DBD D (CJO = 200E-12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E-8 TT = 9E-8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E-3 TC2 = 5.5E-6) ******************************************************************************************* .ENDS http://onsemi.com 5 AND8048/D IS-SPICE .SUBCKT Si5905DC 4 1 2 M1 3 1 2 2 PMOS W = 183649u L = 0.50u M1 2 1 2 4 NMOS W = 183649u L = 1.05u R1 4 3 18E-3 RTEMP CGS 1 2 540E-12 DBD 2 4 DBD ******************************************************************************************* .MODEL PMOS PMOS (LEVEL = 3 TOX = 1.7E-8 +RS = 45E-3 RD = 0 NSUB = 0.67E16 +KP = 4.7E-5 UO = 400 +VMAX = 0 XJ = 5E-7 KAPPA = 20E-3 +ETA = 1E-4 TPG = -1 +IS = 0 LD = 0 CAPOP = 5 +CGSO = 0 CGDO = 0 CGBO = 0 +NFS = 0.8E12 DELTA = 0.1) ******************************************************************************************* .MODEL NMOS NMOS (LEVEL = 3 TOX = 1.7E-8 +NSUB = 16E16 NSF = 10E11 TPG = -1) ******************************************************************************************* .MODEL DBD D (CJO = 200E-12 VJ = 0.38 M = 0.31 +RS = 0.6 FC = 0.5 IS = 1E-8 TT = 9E-8 N = 1 BV = 8.5) ******************************************************************************************* .MODEL RTEMP R (TC1 = 7.5E-3 TC2 = 5.5E-6) ******************************************************************************************* .ENDS http://onsemi.com 6 AND8048/D Notes http://onsemi.com 7 AND8048/D ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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