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| Preliminary RF2469 W-CDMA AND PCS LOW NOISE AMPLIFIER/MIXER DOWNCONVERTER 8 Typical Applications * W-CDMA Handsets * PCS Handsets * General Purpose Downconverter * Commercial and Consumer Systems * Portable Battery-Powered Equipment Product Description The RF2469 is a receiver front-end designed for the receive section of W-CDMA and PCS applications. It is designed to amplify and downconvert RF signals while providing 23dB of stepped gain control range and features digital control of the LNA gain and mixer gain. A further feature of the chip is adjustable IIP3 of the LNA and mixer using an off-chip current setting resistor. Noise Figure, IP3, and other specs are designed to be compatible with W-CDMA and PCS communications. The IC is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (GaAs HBT) process and packaged in a 20-pin, leadless chip carrier with an exposed die flag. 1.00 0.90 0.60 0.24 typ 4.00 sq. 4 PLCS 0.65 0.30 3 0.20 2.10 sq. 12 MAX 0.05 Dimensions in mm. 0.75 0.50 0.50 Note orientation of package. 0.23 0.13 4 PLCS NOTES: 1 Shaded lead is Pin 1. 2 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. 8 FRONT-ENDS 3 Dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 4 Package Warpage: 0.05 mm max. 5 Die Thickness Allowable: 0.305 mm max. Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS u GND Package Style: LCC, 20-Pin, 4x4 GaAs HBT SiGe HBT LNA1 IN VCC1 VCC1 GaAs MESFET Si CMOS ENABLE Features * Complete Receiver Front-End * Stepped LNA/Mixer Gain Control * Adjustable LNA/Mixer Bias Current * 23dB Maximum Cascade Gain * 2.5dB Noise Figure at Maximum Cascade Gain 20 LNA1 OUT GND VCC1 VCC1 LNA2 IN 1 2 3 4 5 6 LNA2 OUT 19 18 17 16 15 14 LNA1 BYP LNA2 BYP GND VCC1 LO IN Logic Control 13 12 11 7 GND 8 MIX IN 9 IF+ 10 IF- Ordering Information RF2469 RF2469 PCBA W-CDMA and PCS Low Noise Amplifier/Mixer Downconverter Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Rev A5 010717 8-33 RF2469 Absolute Maximum Ratings Parameter Operating Ambient Temperature Storage Temperature Preliminary Rating -40 to +85 -40 to +150 Unit C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall RF Frequency Range LO Frequency Range IF Frequency Range Specification Min. Typ. Max. 2110 to 2170 2300 to 2360 190 Unit Condition T=25C, VCC =2.78V, RF=2140MHz, LO=2330MHz @ -10dBm MHz MHz MHz 1st LNA current setting resistor (R1) is 1.1k. 1st LNA current and IIP3 are adjustable via R1. LNA 1 Gain Noise Figure Input IP3 Input VSWR Output VSWR P1dB Current 9 +7.0 10 1.45 +10.0 <2:1 <2:1 -3 4.5 -2 2 +25.0 <2:1 <2:1 1.6 11 1.6 dB dB dBm dB mA 0 2.4 dB dB dBm See LNA P1dB Compression Point section. 8 FRONT-ENDS LNA 1 Bypass Gain Noise Figure Input IP3 Input VSWR Output VSWR Current -5 +20.0 mA Single-ended. Optimum LO Drive -10dBm to -5dBm. Local Oscillator Input Input Level LO to IF Isolation -10 +38 dBm dB Mixer/LNA2 BYP High Gain Noise Figure Input IP3 Input IP2 15 -7.0 +11.0 17 4.5 -3.0 +14.0 dB dB dBm dBm T=25C, VCC =2.78V, RF=2140MHz, LO=2330MHz@-10dBm, LNA2BYP=1, EN=1 Mixer/LNA2 BYP Low Gain Noise Figure Input IP3 Input IP2 4 +2.0 +19.0 6 10.5 +4.0 +22.0 dB dB dBm dBm LNA 2 current setting resistor (R2) is 2.4k LNA 2 current and IIP3 are adjustable via R2 T=25C, VCC =2.78V, RF=2140MHz, LNA2BYP=0, EN =1 LNA 2 current setting resistor (R2) is 2.4k LNA 2 current and IIP3 are adjustable via R2 8-34 Rev A5 010717 Preliminary Parameter Cascade - Condition 1 Gain Noise Figure Input IP3 Current Consumption* 24.5 2.55 -10.5 18.6 dB dB dBm mA RF2469 Specification Min. Typ. Max. Unit Condition LNA1 BYP high, LNA2 BYP high, ENABLE high. Assuming 2.5dB filter loss. 23 Cascade - Condition 2 Gain Noise Figure Input IP3 Current Consumption* 13.5 5.2 -3.5 17 dB dB dBm mA LNA1 BYP high, LNA2 BYP low, ENABLE high. Assuming 2.5dB filter loss. 17.5 Cascade - Condition 3 Gain Noise Figure Input IP3 Current Consumption* 12.5 9 +1.4 14 dB dB dBm mA LNA1 BYP low, LNA2 BYP high, ENABLE high. Assuming 2.5dB filter loss. 15 Cascade - Condition 4 Gain Noise Figure Input IP3 Current Consumption* 1.50 15 +8.2 12.5 dB dB dBm mA LNA1 BYP low, LNA2 BYP low, ENABLE High. Assuming 2.5dB filter loss. 13.5 8 FRONT-ENDS Power Supply Voltage 2.7 2.75 3.3 V *RF2469 is a very flexible device. Customers may choose different current consumption (see Low Current Configuration section). Rev A5 010717 8-35 RF2469 Pin 1 Function LNA1 OUT Description LNA output pin. This is an open-collector output. Externally matched to 50. Preliminary Interface Schematic LNA1 OUT 2 3 GND VCC1 This pin is connected to the ground plane. Supply voltage for LNA1. An external resistor is placed in series with this pin to adjust the current and IIP3 of LNA1. A nominal value of 1.1k sets the LNA1 current to 4.5mA with a minimum IIP3 of +7dBm. External RF bypassing is required. The trace length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground. Supply voltage for LNA2. An external resistor is placed in series with this pin to adjust the current and IIP3 of LNA2. A nominal value of 2.4k sets the LNA2 current to 1.6mA. External RF bypassing is required. The trace length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground. RF input to LNA2. This pin is internally DC-biased and, if it is connected to a device with DC present, should be DC-blocked with a capacitor suitable for the frequency of operation. 4 VCC1 5 LNA2 IN LNA2 IN 6 LNA2 OUT LNA output pin. This is an open-collector output. In normal operation, this pin is externally cascaded with pin 8 (MIX IN). LNA2 OUT 8 FRONT-ENDS 7 8 GND MIX IN 9 IF+ Ground connection. For best performance, keep traces physically short and connect directly to ground plane. Mixer RF input pin. This pin requires a DC path to ground. In normal operation, this pin is externally cascaded with pin 6 (LNA2 OUT). The external match ensures a conjugate match between pin 6 and pin 8 while providing a DC path to ground for pin 8 and a DC-block between pin 8 and pin 6. IF output pin. The output is balanced. A current combiner external network performs a differential to single-ended conversion and sets the output impedance. There must be a DC path from VCC to this pin. This is normally achieved with the current combiner network. A DC blocking cap must be present if the IF filter input has a DC path to ground. Same as pin 9, except complementary output. Mixer LO single-ended input. The pin is internally DC-blocked. External matching sets impedance. Supply voltage for LO buffer. External RF bypassing is required. The trace length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground. This pin is connected to the ground plane. Logic control for LNA2 gain. A logic high (>2.4V) places LNA2 in the high gain mode. A logic low (<0.3V) place LNA2 in the bypass mode. See pin 9. IF+ IF- 10 11 12 13 14 IFLO IN VCC1 GND LNA2 BYP LO IN 32 k LNA2 BYP 8-36 Rev A5 010717 Preliminary Pin 15 16 17 Function LNA1 BYP ENABLE VCC1 Description Logic control for LNA1 gain. A logic high (>2.4V) places LNA1 in the high gain mode. A logic low (<0.3V) place LNA1 in the bypass mode. A logic control for mixer and LO buffer. A logic high (>2.4V) turn the mixer and LO buffer on. A logic low (<0.3V) disable the mixer and LO buffer. Supply voltage for the mixer. An external resistor is place in series with this pin to adjust the mixer current. A nominal value of 1000 set the mixer current to ~10mA. External RF bypassing is required. The trace length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground. Supply voltage for IC. External RF bypassing is required. The trace length between the bypass caps and the pin should be minimized. Connect ground sides of caps directly to ground. RF input to LNA1. This pin is internally DC-biased and, if it is connected to a device with DC present, should be DC-blocked with a capacitor suitable for the frequency of operation. Ground connection. For best performance, keep traces physically short and connect directly to ground plane. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. RF2469 Interface Schematic 32 k LNA1 BYP 32 k ENABLE 18 19 VCC1 LNA1 IN LNA1 IN 20 Pkg Base GND GND 8 FRONT-ENDS Rev A5 010717 8-37 RF2469 Preliminary LNA1, LNA2 and Mixer Application Schematic (RF=2140MHz, IF=190MHz) VCC LNA1 IN VCC 10 nF 10 pF ENABLE 10 pF LNA1 OUT 27 nH 1 2 VCC 1.1 k VCC 2.4 k MIX IN 10 nF 10 pF 10 nF 10 pF 3 4 5 6 7 8 9 10 C2 3.0 pF C1 5 pF L4 VCC L3 C4 C5 LNA2 OUT and MIX IN matching network need to be determined. (L3, L4, C4, and C5) LNA2 OUT MIX IN * See output interface network of the mixer to determine L2 and C3. L1 100 nH VCC R 4.7 k C1 5pF 500 C3* IF OUT L2* IF SAW Logic Control 20 19 18 17 16 15 14 13 12 11 LNA1 BYP LNA2 BYP 0.5 pF 330 pF DNI 1000 VCC VCC 3.0 pF LO IN 10 nF 8 FRONT-ENDS 1.0 pF 10 pF 10 nF 8-38 Rev A5 010717 Preliminary RF2469 LNA1, LNA2 Cascade with Mixer Application Schematic (RF=2140MHz, IF=190MHz) VCC LNA1 IN VCC 10 nF 10 pF ENABLE 10 pF LNA1 OUT 27 nH 1 2 VCC 1.1 k VCC 2.4 k MIX IN 1.0 pF C1 5 pF 10 nH VCC 15 nH *See output interface network of the mixer to determine L2 and C3. 5 pF L1 100 nH VCC 10 nF 10 pF 10 nF 10 pF 3 4 5 6 7 8 9 10 C2 3.0 pF R 4.7 k C1 5 pF 500 C3* IF SAW IF OUT L2* Logic Control 20 19 18 17 16 15 14 13 12 11 3.0 pF 10 nF LO IN VCC LNA1 BYP LNA2 BYP 0.5 pF 330 pF 1000 VCC 8 FRONT-ENDS 10 pF 10 nF Rev A5 010717 8-39 RF2469 Output Interface Network of the Mixer Preliminary L1, C1, C2, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation: 1 f IF = ----------------------------------------------------------L1 2 ----- ( C 1 + 2C 2 + C EQ ) 2 Where CEQ is the equivalent stray capacitance and capacitance looking into pins 9 and 10. An average value to use for CEQ is 2.5pF. R can then be used to set the output impedance according to the following equation: 1 -1 1 R = ae -------------------- - ------o e 4 R OUT R Po where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C2 should first be set to 0 and C1 should be chosen as high as possible, while maintaining an RP of L1 that allows for the desired ROUT. If the self-resonant frequencies of the selected C1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including C2 capacitor with a value chosen to maintain the desired FIF frequency. L2 and C3 serve dual purposes. L2 serves as an output bias choke, and C3 serves as a series DC block. FRONT-ENDS 8 In addition, L2 and C3 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large (suggested 120nH) and C3 is chosen to be large (suggested 22nF) if a DC path to ground is present in the IF filter, or omitted if the filter is DC-blocked. 8-40 Rev A5 010717 Preliminary LNA P1dB Compression Point RF2469 For large signal input, this type of LNA will not have a fixed DC bias current. The LNA will tend to self-bias when the input signal level starts increasing above small signal conditions. This particular characteristic will move the DC bias current to a higher DC bias current. Obviously, increasing the bias current will increase the linearity of the LNA. To accurately measure the P1dB, the measurement technique must force the bias current in the LNA to be a constant, while preserving the collector output voltage of the LNA. In order to due this, a separate supply voltage must be used for the bias voltage of the LNA (pin 3) and the open collector supply (pin 1). As the input signal level is increased, the bias voltage must be dropped while monitoring the DC current in the LNA to ensure that it remains constant. Incidentally, the P1dB compression measured with this technique is consistent with the standard approximation relating P1dB to IIP3 (i.e., Input P1dB=IIP3(dBm)-10). Since the IIP3 measurements are done under small signal conditions (the input tones are low power levels), this approximation provides a good figure for P1dB under a constant DC bias condition. For the RF2469, with an IIP3 of approximately +8dBm, the Input P1dB is approximately -2dBm. However, for many applications, forcing the bias current in the LNA to be constant is not a practical solution. Leaving the LNA to self-bias will not produce any damage to the part and the P1dB performance under this condition will be: Frequency (MHz) 2140 Gain (dB) 10.5 Input P1dB 5.25 Output P1dB 14.92 LNA Current (mA) ~23 8 FRONT-ENDS Rev A5 010717 8-41 RF2469 Evaluation Board Schematic (RF=2140MHz, IF=190MHz) (Download Bill of Materials from www.rfmd.com.) VCC1 J5 LNA1 IN 50 strip VCC1 P1 P1-1 P1-2 P1-3 C25 DNI R5 1000 C24 DNI C23 DNI 1 2 3 CON3 ENABLE LNA1 BYP LNA2 BYP Preliminary C27 0.5 pF C26 330 pF VCC1 P2 P2-1 1 2 P2-3 3 CON3 VCC2 GND VCC1 C1 10 nF C2 10 pF L1 27 nH 50 strip ENABLE 20 50 strip 1 2 3 VCC1 R1 1.1 k C4 10 nF C5 10 pF 4 5 VCC1 R2 2.4 k C8 10 nF 50 strip C9 1.0 pF 50 strip R3 0 C6 10 nF C7 10 pF 6 7 8 9 10 50 strip 50 strip 50 strip C14 5 pF C15 3 pF R4 4.7 k L4 100 nH L2 15 nH VCC1 Typical Board Losses: LNA1_OUT = 0.22 dB @ 2140 MHz LNA1_IN = 0.23 dB @2140 MHz MIX_IN = 0.21 dB @ 2140 MHz IF_OUT = 0.03 dB @ 190 MHz C10 DNI C11 DNI C12 5 pF C13 DNI VCC2 L3 10 nH C16 10 nF 50 strip C18 5 pF L5 120 nH C17 10 pF Logic Control 19 18 17 16 15 14 13 12 11 C21 DNI C20 DNI C22 3.0 pF LNA1 BYP LNA2 BYP VCC1 J1 LNA1 OUT 50 strip C3 10 pF 50 strip 50 strip J4 LO IN 2469400- 8 FRONT-ENDS J2 MIX IN 500 C19 7 pF 50 strip J3 IF OUT 50 strip 50 strip 8-42 Rev A5 010717 Preliminary Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.031", Board Material FR-4, Multi-Layer Assembly Top RF2469 8 FRONT-ENDS Power Plane Back Rev A5 010717 8-43 RF2469 LNA1 (Low Gain Mode) 0.0 Gain, -30 Gain, 25 Gain, 85 -0.5 11.2 -1.0 11.4 11.6 Preliminary LNA1 (High Gain Mode) Gain (dB) Gain (dB) 11.0 -1.5 10.8 10.6 -2.0 10.4 Gain, -30 Gain, 25 Gain, 85 -2.5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 10.2 2.7 2.8 2.9 3.0 3.1 3.2 3.3 VCC (V) VCC (V) LNA1 (Low Gain Mode) 3.5 2.5 LNA1 (High Gain Mode) 3.0 8 Noise Figure (dB) 2.0 2.5 Noise Figure (dB) FRONT-ENDS 2.0 1.5 1.5 1.0 1.0 NF, -30 0.5 NF, 25 NF, 85 0.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 0.0 2.7 2.8 2.9 3.0 3.1 0.5 NF, -30 NF, 25 NF, 85 3.2 3.3 VCC (V) VCC (V) LNA1 (Low Gain Mode) 31.0 16.0 LNA1 (High Gain Mode) 29.0 14.0 27.0 12.0 25.0 IIP3 (dBm) IIP3 (dBm) 10.0 23.0 8.0 21.0 6.0 19.0 IIP3, -30 IIP3, 25 IIP3, 85 15.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 IIP3, -30 4.0 IIP3, 25 IIP3, 85 17.0 VCC (V) VCC (V) 8-44 Rev A5 010717 Preliminary Total Current (LNA1BYP=LNA2BYP=EN=0) 9.5 40.0 RF2469 Total Current (LNA1BYP=LNA2BYP=EN=1) 9.0 35.0 30.0 8.5 25.0 ICC (mA) ICC (mA) Icc, -30 8.0 20.0 7.5 15.0 7.0 10.0 Icc, -30 5.0 Icc, 25 Icc, 85 0.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.7 2.8 2.9 3.0 3.1 3.2 3.3 6.5 Icc, 25 Icc, 85 6.0 VCC (V) VCC (V) 8 FRONT-ENDS Rev A5 010717 8-45 RF2469 Mixer/LNA2, Low Gain Mode (LNA2BYP=0), LO @ -10dBm 12.0 8.0 Preliminary Mixer/LNA2, Low Gain Mode (LNA2BYP=0), LO @ -10dBm 7.0 10.0 6.0 8.0 5.0 IIP3 (dBm) Gain, -30 Gain (dB) 6.0 4.0 3.0 4.0 2.0 IIP3, -30 1.0 IIP3, 25 IIP3, 85 0.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 0.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.0 Gain, 25 Gain, 85 VCC (V) VCC (V) Mixer/LNA2, Low Gain Mode (LNA2BYP=0), LO @ -10dBm 27.0 11.5 Mixer/LNA2 IF, Low Gain Mode (LNA2BYP=0), LO @ -10dBm 25.0 11.0 8 FRONT-ENDS Noise Figure (dB) IIP2, -30 17.0 IIP2, 25 IIP2, 85 23.0 10.5 IIP2 (dBm) 10.0 21.0 9.5 19.0 9.0 NF, -30 8.5 NF, 25 NF, 85 8.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.7 2.8 2.9 3.0 3.1 3.2 3.3 15.0 VCC (V) VCC (V) Mixer/LNA2, High Gain Mode (LNA2BYP=1), LO @ -10dBm 24.0 23.0 22.0 21.0 20.0 19.0 18.0 17.0 Gain, -30 16.0 15.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 Gain, 25 Gain, 85 -9.0 2.7 -8.0 0.0 -1.0 -2.0 -3.0 Mixer/LNA2, High Gain Mode (LNA2BYP=1), LO @ -10dBm IIP3, -30 IIP3, 25 IIP3, 85 IIP3 (dBm) Gain (dB) -4.0 -5.0 -6.0 -7.0 2.8 2.9 3.0 3.1 3.2 3.3 VCC (V) VCC (V) 8-46 Rev A5 010717 Preliminary Mixer/LNA2, High Gain Mode (LNA2BYP=1), LO @ -10dBm 17.0 IIP2, -30 16.0 IIP2, 25 IIP2, 85 5.5 6.0 RF2469 Mixer/LNA2, High Gain Mode (LNA2BYP=1), LO @ -10dBm 15.0 NF, -30 Noise Figure (dB) 5.0 NF, 25 NF, 85 IIP2 (dBm) 14.0 4.5 13.0 4.0 12.0 11.0 3.5 10.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 VCC (V) VCC (V) Mixer/LNA2 LO to IF Leakage (LNA2BYP=1) -25.0 -27.0 -29.0 -31.0 -33.0 -35.0 -37.0 -39.0 -41.0 -43.0 -45.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 Isolation, -30 Isolation, 25 Isolation, 85 21.0 20.5 20.0 Mixer/LNA2, High Gain Mode (LNA2BYP=1), VCC @ 2.78V Gain, -30 LO to IF Leakage (dB) 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 -10.0 Gain, 25 Gain, 85 8 FRONT-ENDS Gain (dB) -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 VCC (V) LO (dBm) Mixer/LNA2 IF, High Gain Mode (LNA2BYP=1), 0.0 Mixer/LNA2 IF, High Gain Mode (LNA2BYP=1), 22.0 VCC=2.78V IIP3, -30 IIP3, 25 VCC=2.78V -2.0 IIP3, 85 20.0 -4.0 18.0 IIP3 (dBm) -6.0 IIP2 (dBm) 16.0 -8.0 14.0 IIP2, -30 -10.0 12.0 IIP2, 25 IIP2, 85 -12.0 -10.0 10.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 LO (dBm) LO (dBm) Rev A5 010717 8-47 RF2469 Low Current Configuration Preliminary External resistors can set different bias currents for LNA1 (pin 3), LNA2 (pin 4, also called the preamplifier of the mixer), and mixer (pin 17). Customers have the flexibility to choose the most suitable bias current, and therefore the performance, of the IC. The charts on the following page reflect different bias currents for the RF2469. The currents were calculated using the following equations. LNA1 current (R1)=Total Current (LNA1=EN=1, LNA2=0)-Total Current (EN=1, LNA1=LNA2=0)+1.6 1.6 is the bypass current of LNA1 Mixer/LNA2 current (R2)=Total Current (LNA1=0, LNA2=EN=1)-Total Current (LNA1=LNA2=0, EN=1)+1.4+10.2 1.4 is the bypass current of LNA2; 10.2 is the mixer (LO buffer included) Mixer Only current (R5)=Total Current (EN=LNA2=1, LNA1=0)-4.5 4.5 is the bypass current of the LNA1 (1.6mA)+LNA2 high mode current (2.9mA) RFMD chose a low current configuration of the RF2469, by using R1=3k, R2=3.6k, and R5=1k in the evaluation board, and the following lab results over temperature were obtained. LNA1 High Mode PIN VCC (dBm) (VDC) -30 2140 -25 2.78 +25 2140 -25 2.78 +85 2140 -25 2.78 Total Current (mA) is when LNA1BYP=LNA2BYP2=EN =1. Temp (C) Frequency (MHz) Gain (dB) +7.97 +8.81 +9.70 IIP3 (dBm) -3.78 +2.32 +7.71 Noise Figure (dB) +1.72 +1.95 +2.37 Total Current +11.33 +12.36 +16.45 8 FRONT-ENDS Mixer/LNA2 BYP High Mode Temp (C) -30 +25 +85 Frequency (MHz) 2140 2140 2140 PIN (dBm) -25 -25 -25 LO Frequency (MHz) 2330 2330 2330 PIN LO (dBm) -10 -10 -10 VCC (VDC) 2.78 2.78 2.78 Gain (dB) +18.73 +17.74 +16.67 IIP3 (dBm) -8.16 +5.13 -3.66 Noise Figure (dB) +3.98 +4.54 +5.19 8-48 Rev A5 010717 Preliminary LNA Gain, Noise Figure and IIP3 versus ICC - LNA1 Only 12.0 RF2469 Resistor (R1) versus ICC (mA) - LNA Only 4.0 (LNA High Gain) 16.0 14.0 (LNA High Gain) 10.0 12.0 Gain and Noise Figure (dB) 3.0 8.0 6.0 6.0 4.0 Gain (dB) NF (dB) IIP3 (dBm) 4.0 2.0 2.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 -2.0 10.0 Resistor R1 (k ) 8.0 10.0 IIP3 (dBm) 2.0 1.0 0.0 1.0 3.0 5.0 7.0 9.0 11.0 ICC (mA) ICC (mA) Mixer Gain, Noise Figure and IIP3 versus ICC 20.0 18.0 4.5 16.0 Resistor (R2) versus ICC - Mixer/LNA2 BYP High 0.0 5.0 Mixer/LNA2 BYP High (LO=2330MHz @ -10dBm, sweeping R2) (LO=2330MHz @ -10dBm) Gain and Noise Figure (dB) 14.0 4.0 8 FRONT-ENDS 11.5 12.0 12.5 13.0 13.5 IIP3 (dBm) 12.0 10.0 8.0 6.0 4.0 Gain (dB) NF (dB) IIP3 (dBm) -4.0 Resistor R2 (k ) -2.0 3.5 3.0 2.5 2.0 2.0 0.0 11.0 -6.0 13.5 1.5 11.0 11.5 12.0 12.5 13.0 ICC (mA) ICC (mA) Mixer Gain, Noise Figure and IIP3 versus ICC 25.0 Resistor (R5) versus ICC - Mixer/LNA2 BYP High 0.0 -1.0 1.4 1.6 Mixer/LNA2 BYP High (LO=2330MHZ @ 019dBm, sweeping R5) (LO=2330MHz @ -10dBm) 20.0 -2.0 -3.0 Gain and Noise Figure (dB) IIP3 (dBm) -5.0 10.0 -6.0 -7.0 5.0 -8.0 IIP3 (dBm) 15.0 NF (dB) -4.0 Resistor R5 (k ) Gain (dB) 1.2 1.0 0.8 0.6 -9.0 0.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 -10.0 14.0 0.4 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 ICC (mA) ICC (mA) Rev A5 010717 8-49 RF2469 Preliminary 8 FRONT-ENDS 8-50 Rev A5 010717 |
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