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White Electronic Designs
2Mx16x 4 Banks Synchronous DRAM
FEATURES
Single 3.3V power supply Fully Synchronous to positive Clock Edge SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz) Burst Operation * Sequential or Interleave * Burst length = programmable 1,2,4,8 or full page * Burst Read and Write * Multiple Burst Read and Single Write DATA Mask Control per byte Auto Refresh (CBR) and Self Refresh * 4096 refresh cycles across 64ms Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode
WED416S8030A-SI
DESCRIPTION
The WED416S8030AxxSI is 134,217,728 bits of synchronous high data rate DRAM organized as 4 x 2,097, 152 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Available in a 54 pin TSOP type II package the WED416S4030AxxSI is tested over the industrial temp range (-40C to +85C) providing a solution for rugged main memory applications.
PIN CONFIGURATIONS
PIN DESCRIPTION
CLK CKE RAS# CAS# WE# CE# A0-A11 BA0, BA1 DQ0-DQ15 L(U)DQM VCC VCCQ VSS VSSQ NC Clock Input Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Select Address Inputs Bank Select Address Data Input/Output Data Input/Output Mask Power (+3.3V 10%) Data Output Power Ground Data Output Ground No Connection
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE# CAS# RAS# CE# BA0 BA1 A10/AP A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC/RFU UDQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
TERMINAL CONNECTIONS
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
(TOP VEIW)
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WED416S8030A-SI
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK CKE CE# RAS#, CAS#, WE# BA0, BA1 A0-11, A10/AP Type Input Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Level Polarity Positive Edge Active High Active Low Active Low Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be WE executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
DQ0-15 L(U)DQM
Input/Output Input
Level Pulse
Mask Active High
VCC, VSS VCCQ, VSSQ
Supply Supply
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Disspation Short Circuit Output Current Symbol VCC VIN VOUT TOPR TSTG PD IOS Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 1.0 50 Unit V V V C C W mA
WED416S8030A-SI
Recommended Operating Conditions
Voltage Referenced to: VSS = 0V, -40C TA +85C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Voltage Output Leakage Voltage Symbol Min Typ Max Unit Notes 3.0 3.3 3.6 V VCC VIH 2.0 3.0 VCC+0.3 V -0.3 -- +0.8 V VIL VOH 2.4 --- -- V (IOH=-2mA) VOL ---- 0.4 V (IOL=2mA) IIL -5 -- 5 A IOL -5 -- 5 A
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
TA = 25C, f = 1MHz, VCC = 3.0V to 3.6V Parameter Input Capacitance (A0-11, BA0-1) Input Capacitance (CK, CKE, RAS#, CAS# WE#, CE#, L(U)DQM) Input/Output Capacitance (DQ0-15) Symbol CI1 CI2 COUT Max 4 4 5 Unit pF pF pF
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, = -40C TA +85C Parameter Operating Current (One Bank Active) Operating Current (Burst Mode) Precharge Standby Current in Power Down Mode Precharge Standby Current in NonPower Down Mode Active Standby Current in Non-Power Down Mode Active Standby Current in Power Down Mode Refresh Current Self Refresh Current
NOTE: 1. Measured with outputs open. 2. Refresh period is 64ms.
Symbol ICC1 ICC4 ICC2P ICC2PS ICC1N ICC1NS ICC3P ICC3PS ICC2N ICC2NS ICC5 ICC6
Test Conditions Burst Length = 1, tRC tRC =min Page Burst, 2 banks active, tCCD = 2 clocks CKE VIL (MAX), tCC = 15ns CKE, CK VIL (MAX), tCC =, Input Stable CKE = VIH, tCC = 15ns. Input Change every 30ns CKE VIH (MIN), tCC = , No Input Change CKE VIL (MAX), tCC = 15ns CKE VIL (MAX), tCC = CKE = VIH, tCC = 15ns, Input Change every 30ns CKE VIH (MIN), tCC = , No Input Change tRC tRC (Min) CKE 0.2V
-10 140 200 2 2 50 35 12 12 30 20 210 3
-12 125 165 2 2 50 35 12 12 30 20 210 3
Units mA mA mA mA mA mA mA mA mA mA mA mA
Notes 1 1
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC CHARACTERISTICS
OPERATING AC PARAMETERS
VCC = 3.3V, = -40C TA +85C Parameter Clock Cycle Time CAS latency = 3 CAS latency = 2 Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD Min 10 13 3 3.5 3.5 2.5 1 1 7 20 24 24 50 80 80 1 1 1 1 2 1 24 26 26 60 90 90 1 1 1 1 2 1 -10 Max 1000 1000 7 Min 12 15 3 4.0 4.0 3 1 1
WED416S8030A-SI
-12 Max 1000 1000 8
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK ea
Notes 1 1, 2 2 3 3 3 3 2 4 4 4 4 4 4, 8 5 5 5 6 7
Clock to Valid Output Delay Output Dta Hold Time Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time Clock to Output in Low-Z Clock to Output in High-Z Row Active to Row Active Delay RAS# to CAS# Delay Row Precharge Time Row Active Time Row Cycle Time-Operation Row Cycle Time-Auto Refresh Last Data In to New Column Address Delay Last Data In to Row Precharge Last Data In to Burst Stop Colunm Address to Column Address Delay Number of Valid Output Data CAS latency = 3 CAS latency = 2
8
100,000
100,000
NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns, (tRISE/2 - 0.5ns) should be added to the parameter. 3. Assumed input RISE and fall time = 1ns. If tRISE & tFALL are longer than 1ns, [(tRISE + tFALL)/2-1ns] should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit.
REFRESH CYCLE PARAMETERS
Parameter Refresh Period Self Refresh Exit Time Symbol tREF tSREX Min tRFC -10 Max 64 Min tRFC -12 Max 64 Units ms ns Notes 1, 2 3
NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation.
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(UNITS = NUMBER OF CLOCKS) Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (12.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 tRC 80ns 8 7 6 6 tRAS 50ns 5 5 4 4 tRP 24ns 3 2 2 2 tRRD 20ns 2 2 2 2 tRCD 24ns 3 2 2 2
WED416S8030A-SI
CLOCK FREQUENCY AND LATENCY PARAMETERS = 100MHz
tCCD 10ns 1 1 1 1 tCDL 10ns 1 1 1 1 tRDL 10ns 1 1 1 1
CLOCK FREQUENCY AND LATENCY PARAMETERS = 83MHz
(UNITS = NUMBER OF CLOCKS) Frequency 83MHz (12ns) 75MHz (12ns) 66MHz (15ns) CAS Latency 3 3 2 tRC 90ns 8 7 6 tRAS 60ns 5 5 4 tRP 26ns 3 2 2 tRRD 24ns 2 2 2 tRCD 26ns 3 2 2 tCCD 12ns 1 1 1 tCDL 12ns 1 1 1 tRDL 12ns 1 1 1
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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COMMAND TRUTH TABLE
CKE Command Register Refresh Precharge Bank Activate Write Read Mode Register Set Auto(CBR) Refresh Entry Self Refresh Single Bank All Banks Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Previous Cycle H H H H H H H H H H L H X Current Cycle X H L X X X X X X X X X L H CE# L L L L L L L L H X X H RAS# L L L L H H H H X X X X CAS# L L H H L L H H X X X X WE# L H L H L H L H X X X X
WED416S8030A-SI
DQM X X X X X X X X X X L H X
BA
A10/AP
A11, A9-0
Notes
X BA X BA BA BA X X X X X X
OP CODE X
X 2 2 2 2 2 2 3
L X H X Row Address L Column Address H L H X X X X X X Column Address X X X X X X
Burst Stop No Operation Device Deselect Clock Suspend/Standby Mode Data Write/Output Enable Mask/Output Disable Power Down Entry Mode Exit
4 5 5 6 6
(X = Don't Care, H = Logic High, L = Logic Low) NOTES: 1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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CLOCK ENABLE (CKE0) TRUTH TABLE
Current State Self Refresh CKE Previous H L L L L L L H L L L H H H H H H H H H H L H H L L Current X H H H H H L X H H L H H H H H L L L L L X H L H L CE# X H L L L L X X H L X H L L L L H L L L L X X X X X RAS# X X H H H L X X X X X X H L L L X H L L L X X X X X Command CAS# X X H H L X X X X X X X X H L L X X H L L X X X X X WE# X X H L X X X X X X X X X X H L X X X H L X X X X X BA X X X X X X X X X X X A0-12 X X X X X X X X X X X
WED416S8030A-SI
Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode Exit, all bank idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Notes 1 2 2 2 2 2 1 2 2 3
Power Down
All Banks Idle
X
X OP Code
4 3
Any State other than listed above
X OP Code X X X X X X X X X X
X
4 4
5
NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. 5. Must be a legal command as defined in the Current State Truth Table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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CURRENT STATE TRUTH TABLE
Current State Idle Command CE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
8
WED416S8030A-SI
Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Prechage ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
Notes 2 2,3
4 4
5
Row Active
6 4 7,8 7,8
Read
4 8,9 8,9
Write
4 8,9 8,9
Read with Auto Precharge
4 4
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CURRENT STATE TRUTH TABLE (cont'd)
Current State Write with Auto Precharge Command CE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED416S8030A-SI
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Write; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL
Notes
4 4
Precharging
4 4 4
Row Activating
4 4,10 4 4
Write Recovering
4 4 9 9
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CURRENT STATE TRUTH TABLE (cont'd)
Current State Write Recovering with Auto Precharge Command CE# L L L L L L L L H L L L L L L L L H L L L L L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
WED416S8030A-SI
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; idle after tRC No Operation; idle after tRC No Operation; idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles
Notes
4 4 4,9 4,9
Refreshing
Mode Register Accessing
NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ORDERING INFORMATION
Part Number WED416S8030A10SI WED416S8030A12SI Organization 2Mx16bitsx4banks 2Mx16bitsx4banks Operating Frequency 100MHz 83MHz
WED416S8030A-SI
Height* 11.76 (0.463") 11.76 (0.463")
NOTE: This product does not include the prefix "WED" for part marking due to package size constraints.
PACKAGE OUTLINE, JEDEC MS-024-FA, ISSUE C
22.62 (0.89) MAX
Note 1 VIEW A
10.16 (0.40) Note 2
11.76 0.20 (0.463 0.008) 0.05 (0.002) 0.35 0.10 (0.01 0.004)
1.20 (0.047) MAX
0.75 (0.030) 0.45 (0.018)
0.80 (0.03) TYP
SEE VIEW A 0-8 0.125 0.035 (0.005 0.001)
NOTES: 1. Dimension does not include 0.24mm (0.006) inch flash each side. 2. Dimension does not include 0.50mm (0.016) inch flash each side.
*ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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Document Title
2Mx16x 4 Banks Synchronous DRAM
WED416S8030A-SI
Revision History Rev #
Rev 1 Rev 2
History
Created 2.1 Changed from EDI to WED 2.2 Changed from Advanced to Preliminary
Release Date
5-21-1999 5-15-2000
Status
Advanced Advanced Preliminary
Rev 3 Rev 4
3.1 Changed from Preliminary to Final 4.1 Changed to WEDC format 4.2 Added Document Title Page
9-2000 10-2004
Final Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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