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T6K41
Preliminary
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6K41
Column and Row Driver LSI for a Dot Matrix Graphic LCD
The T6K41 is a driver for a small-to-medium-sized dot matrix graphic LCD, especially for four-gray-scale monochromatic STN Unit: mm LCDs. This driver can be interfaced to the MPU via an 8-bit Lead Pitch (80/68-series) or a serial interface, and is operated T6K41 asynchronously with the MPU. IN OUT Since the T6K41 contains a CR oscillator, it can generate the timing signals required for the LCD. The T6K41 has 128 outputs for the LCD drive (segment) Please contact your nearest TOSHIBA dealer for individual package dimensions. signals that constitute the display data, 128 outputs for the LCD drive (common) signals that constitute the scanning signals and No idea 16 bits of static-LCD drive (icon) signals. Furthermore, the T6K41 has 128 x 128 x 2 bits display RAM and 16-bit register. TCP (Tape Carrier Package) Thus, this single device allows you to drive an LCD panel comprised of up to 128 x 128 + 16 dots with a minimize of power requirement. It also incorporates a gray-scale function. The display RAM of the T6K41 is a two-port RAM so that the MPU access it without any wait time. To minimize power consumption, the T6K41 has a display change mode (power save mode) in which only a 16-dot icon can be displayed. Furthermore, it has various built-in analog circuits such as a voltage regulator, voltage divider resistors, power supply op-amp, DC-DC converters (x2 to x6) and a contrast control (electronic volume) circuit. All these circuits enable the LCD panel to be driven with a single power supply.
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T6K41
Features
* * * * * * LCD drive outputs Display RAM Gray scales Word length Display duty cycle Display modes : 128 rows (common) x 128 columns (segment) + 16 icons : 128 x 128 x 2 = 32,768 bits, 2-port RAM : 4 gray-scale levels (palette function) : 8-bit/word : 1/72, 1/80, 1/100 or 1/128 duty during Normal Mode. (Duty cycles in Normal Mode are set in software by the MPU.) : Normal Mode: Full display Power Save Mode: Icon display Partial Display Mode: Partial display Standby Mode: Clock stopped (all internal circuits turned off) * * * * * MPU Oscillator Power supply circuits Operating voltage LCD drive voltage : 8-bit (68/80 Series) parallel or serial interface : Built-in CR oscillator with external resistors : Resistors to divide bias voltage, op-amp for LCD drive power supply, DC-DC converters (x2 to x6), contrast control circuit. : VDD = 2.4 V to 3.3 V, VIN = 2.7 V to 3.3 V : VCC = 16.5 V (max) VOUT = 15.4 V (typ.) or VOUT = 13.0 V (typ.) (for internal voltage regulator) These voltages can be selected in software. * * CMOS process Low power consumption : ISS = 300 A (typ.) Conditions: VDD = VIN = 3.0 V, when DC-DC converter is used (x6 Mode), LCD non-loaded, Ta = 25C, 1/128 duty, 1/12 bias, fosc = 82 kHz (when internal oscillator is used), voltage regulator ON, op-amp ON, display data = ALL 4-gray-scale checker pattern, no data access from MPU. * * Temperature coefficient of voltage regulator: -0.05%/C Package :
Product T6K41 (xxx, xxx) JBT6K41-AS Package TCP (Tape carrier package) Gold bump chip
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T6K41
Block Diagram
COM128 LCD driver circuit(128) FRC circuit Latch circuit 128 2 3 Decoder Multiplexer 6 Input/Output gate circuit Y-address counter/decoder X-address counter Display RAM128 128 2 = 32,768 bits FRC SEG1 SEG128
COM1
COM64 COM65
LCD driver circuit (64)
LCD driver circuit (64)
32 bit shift register
32 bit shift register
3
VCC
Timing signals generating circuit
M/S BLNK SYNC CK CL PM FR STB
Op-amp Z-address counter FRS control register
VLC1 VLC2 VLC3 VLC4 8 Duty cycle control register Display control register
Contrast control register
Z- address register
VLC5
VOUT
DC-DC converter
VREF
CnA
X/Y counter select register
X/Y counter up/down register
Bias control circuit
CnB n = 1 to 5 Analog control register 4
VIN
Contrast control circuit
Grayscale control register
Static icon control register
Oscillator control register
Register select circuit
S1 to S16
COMS
Static icon driver circuit
Output register 8
Input register 8 Interface control circuit Input/Output buffer
Oscillator OSC3 VDD VSS 68/80 RST D/I
OSC1
OSC2
P/S
CS1
CS2
WR
RD
RS SCK
SI
SO
DB0 to DB7
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T6K41
Pin Assignment
S1 S2 S3
S14 S15 S16 COMS COM64 COM63 COM62 COM61
COM4 COM3 COM2 COM1 SEG1 SEG2 SEG3 SEG4
T6K41
(top view)
SEG125 SEG126 SEG127 SEG128 COM65 COM66 COM67 COM68
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CS1 CS2 RS RD WR D/I RST P/S 68/80 SO SI SCK M/S BLNK SYNC CK CL PM FR STB VDD OSC3 OSC2 OSC1 VSS VREF VIN C1A C1B C2A C2B C3A C3B C4A C4B C5A C5B VOUT VCC VLC0 VLC1 VLC2 VLC3 VLC4 VLC5 (HVSS)
COM125 COM126 COM127 COM128 COMS
Note 1: The above diagram shows the pin configuration of the LSI chip, not that of the tape carrier package.
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T6K41
Pad Specification
Note 2: Please refer to the T6K41 technical datasheet for pad specification.
Item Chip Size (1) (2) Chip Tip Coordinates (3) (4) Bump Pitch Bump Height
Size 12300 2610 -6150, -1305 -6150, -1305 6150, 1305 6150, -1305 52 144
Unit
mm
mm
mm mm
Item Input pin Output pin TEST Pin FUSE Pin
Number of Pins 105 Pins (including Dummy pins) 283 Pins (including Dummy pins) 2 Pins 17 Pins (Note 3) (Note 3)
Note 3: TEST and FUSE pins are LSI test pins, leave these pins open.
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T6K41
Pad Layout
Chip size: 12.3 2.61 mm
No. 407
(0, 0)
No. 1
Note 4: Please refer to the T6K41 technical datasheet for pad layout and coordinates values.
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T6K41
Pad Coordinates (1)
[Unit: mm]
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 NAME VCL5 VLC5 VLC5 VLC5 VLC4 VLC4 VLC3 VLC3 VLC2 VLC2 VLC1 VLC1 VLC0 VLC0 VLC0 VLC0 VCC1 VCC1 VCC1 VCC1 TEST2 VOUT VOUT C5B C5A C4B C4A C3B C3A C2B C2A C1B C1A DMYVSS VIN VIN DMYVSS VREG TDUMMY1 TDUMMY2 TDUMMY3 TDUMMY4 TDUMMY5 TDUMMY6 TDUMMY7 X-Point -5871 -5769 -5667 -5565 -5463 -5361 -5259 -5157 -5055 -4953 -4851 -4749 -4647 -4545 -4443 -4341 -4239 -4137 -4035 -3933 -3831 -3729 -3627 -3525 -3423 -3321 -3219 -3117 -3015 -2913 -2811 -2709 -2607 -2514 -2421 -2319 -2231 -2142 -2056 -1955 -1833 -1732 -1652 -1551 -1429 Y-Point -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 No. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 NAME TDUMMY8 DMYVSS VSS VSS VSS VSS VSS TEST3 OSC1 DMYVSS OSC2 DMYVSS OSC3 FUSE31 FUSE32 FUSE3G FUSE33 FUSE34 FUSE21 FUSE22 FUSE23 FUSE2G FUSE24 FUSE25 FUSE11 FUSE12 FUSE13 FUSE1G FUSE14 FUSE15 VDD VDD VDD VDD VDD TDUMMY9 TDUMMY10 TDUMMY11 TDUMMY12 TDUMMY13 TDUMMY14 TDUMMY15 TDUMMY16 TDUMMY17 TDUMMY18 X-Point -1328 -1249 -1170 -1084 -998 -912 -826 -740 -654 -568 -482 -396 -310 -210 -111 -12 87 186 285 384 483 582 681 780 879 978 1077 1176 1275 1374 1486 1587 1688 1789 1890 1976 2077 2199 2279 2380 2502 2582 2662 2805 2885 Y-Point -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 NAME TDUMMY19 /STB FR PM CL CK SYNC BLNK M/S SCK SI SO DMYVDD 68/80 DMYVSS P/S DMYVDD /RST D/I /WR /RD RS CS2 /CS1 DMYVSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DMYVDD DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 S1 S2 S3 S4 S5 X-Point 2986 3072 3161 3252 3343 3434 3525 3616 3705 3791 3877 3963 4049 4135 4221 4307 4393 4479 4565 4651 4737 4823 4909 4995 5081 5167 5253 5339 5425 5511 5597 5683 5769 5871 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 Y-Point -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -1124 -803 -721 -669 -617 -565 -513 -461 -409 -357 -305 -253
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T6K41
Pad Coordinates (2)
[Unit: mm]
No. 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NAME S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 COMS2 DUMMY7 DUMMY8 COM64 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 X-Point 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5934 5801 5719 5667 5615 5563 5511 5459 5407 5355 5303 5251 5199 5147 5095 5043 4991 4939 4887 4835 4783 4731 4679 4627 4575 4523 4471 Y-Point -201 -149 -97 -45 8 60 112 164 216 268 320 372 425 477 529 581 633 685 767 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 NAME COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 X-Point 4419 4367 4315 4263 4211 4159 4107 4055 4003 3951 3899 3847 3795 3743 3691 3639 3587 3535 3483 3431 3379 3327 3275 3223 3171 3119 3067 3015 2963 2911 2859 2807 2755 2703 2651 2599 2547 2495 2443 2391 2339 2287 2235 2183 2131 Y-Point 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 No. 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 NAME SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 X-Point 2079 2027 1975 1923 1871 1819 1767 1715 1663 1611 1559 1507 1455 1403 1351 1299 1247 1195 1143 1091 1039 987 935 883 831 779 727 675 623 571 519 467 415 363 311 259 207 155 103 51 -1 -53 -105 -157 -209 Y-Point 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087
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T6K41
Pad Coordinates (3)
[Unit: mm]
No. 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 NAME SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 X-Point -261 -313 -365 -417 -469 -521 -573 -625 -677 -729 -781 -833 -885 -937 -989 -1041 -1093 -1145 -1197 -1249 -1301 -1353 -1405 -1457 -1509 -1561 -1613 -1665 -1717 -1769 -1821 -1873 -1925 -1977 -2029 -2081 -2133 -2185 -2237 -2289 -2341 -2393 -2445 -2497 -2549 -2601 Y-Point 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 No. 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 NAME SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 X-Point -2653 -2705 -2757 -2809 -2861 -2913 -2965 -3017 -3069 -3121 -3173 -3225 -3277 -3329 -3381 -3433 -3485 -3537 -3589 -3641 -3693 -3745 -3797 -3849 -3901 -3953 -4005 -4057 -4109 -4161 -4213 -4265 -4317 -4369 -4421 -4473 -4525 -4577 -4629 -4681 -4733 -4785 -4837 -4889 -4941 -4993 Y-Point 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 No. 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 NAME COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 DUMMY9 COMS1 X-Point -5045 -5097 -5149 -5201 -5253 -5305 -5357 -5409 -5461 -5513 -5565 -5617 -5669 -5721 -5803 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 -5934 Y-Point 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 1087 767 685 633 581 529 477 425 373 321 269 217 165 113 61 9 -43 -95 -147 -199 -251 -303 -355 -407 -459 -511 -563 -615 -667 -719 -801
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T6K41
Pin Functions
Pin Name SEG1 to SEG128 COM1 to COM128 S1 to S16 COMS DB0 to DB7 I/O Output Output Output Output I/O LCD drive segment signals LCD drive common signals LCD driver segment signals for static icons LCD driver common signals for static icons Data bus Functions
Chip Select Signal 1 CS1 Input Write data: Data on DB0 to DB7 is latched on the rising edge of CS1 . Read data: Data appears on DB0 to DB7 while CS1 is Low. Chip Select Signal 2 CS2 Input Write data: Data on DB0 to DB7 is latched on the falling edge of CS2. Read data: Data appears on DB0 to DB7 while CS1 is High. Input for data/instruction select signal D/I Input
* D/I = High (R) Indicates that the data on DB0 to DB7 or SI is display data. * D/I = Low (R) Indicates that the data on DB0 to DB7 or SI is an instruction.
Input or Write Select signal (Input for Read/Write Select signal) WR (R/W) Input
* If 80 Series MPU is selected, data on DB0 to DB7 is latched on the rising edge of WR * If 68 Series MPU is selected, data read is selected if R/W = High and data write is selected if R/W = Low.
Input for Read Select signal (Input for Enable signal)
RD (E)
Input
* If 80 Series MPU is selected, data appears on DB0 to DB7 while RD = Low. * If 68 Series MPU is selected, this pin is used for the Input Enable signal.
Input for Register Mode Select signal RS Input
* If RS = Low, this input is recognized as a register number. * If RS = High, this input is recognized as the data to be written to the register.
Input for parallel/serial interface select signal P/S Input
* P/S = High (R) Parallel interface is selected. SI and SCK must be connected to VDD or VSS. * P/S = Low (R) Serial interface is selected. DB0 to DB7 must be open. WR and RD must be connected to VSS.
Input for 68/80 Series Parallel MPU Select signal 68/80 Input
* 68/80 = High (R) 68 Series parallel MPU is selected. * 68/80 = Low (R) 80 Series parallel MPU is selected.
SO SI SCK RST
Output Input Input Input
Output for serial data Input for serial data Input for serial clock Input for Reset signal
* RST = Low (R) Reset state
Input for Standby signal Usually connected to VDD.
STB
Input
* STB = Low (R) T6K41 is in Standby state. Column drive signals and row drive signals are at the VSS level and the on-chip oscillator is stopped. * In standby state T6K41 can be accessed by the MPU.
OSC1
Input
Input for CR oscillator When using an external clock, input the clock to OSC1 and leave OSC2 and OSC3 open.
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T6K41
Pin Name I/O Output for CR oscillator OSC2, OSC3 Output When using the internal clock oscillator, connect a resistor between OSC1 and OSC2 or between OSC1 and OSC3. OSC1 and OSC2: Oscillator for Normal Display Mode OSC1 and OSC3: Oscillator for Partial Display Mode Power supply for DC-DC converter VIN
3/4
Functions
Usually connected to VDD The condition VDD < VIN must always be met. = External capacitor-connecting pin for 2 DC-DC converter External capacitor-connecting pin for 3 DC-DC converter External capacitor-connecting pin for 4 DC-DC converter External capacitor-connecting pin for 5 DC-DC converter External capacitor-connecting pin for 6 DC-DC converter DC-DC converter output pin LV regulator output pin LCD driver power supply pin LCD drive power supply pin Logic circuit power supply pin Input for Master/Save Select signal
* M/S = High (R) T6K41 is a master chip. * M/S = Low (R) T6K41 is a slave chip.
C1A, C1B C2A, C2B C3A, C3B C4A, C4B C5A, C5B VOUT VREF VCC VLC0 to VLC5 VDD, VSS M/S
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Input
CL
I/O
Input/Output for Shift Clock pulse
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
PM
I/O
Input/Output for Frame signal
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
FR
I/O
Input/Output for display alternating signal
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
CK
I/O
Input/Output for system clock signal
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
SYNC
I/O
Input/Output for gray-scale data synchronous signal
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
BLNK
I/O
Input/Output for static icons blinking synchronous signal
* Master Mode (M/S = High) (R) Output * Slave Mode (M/S = Low) (R) Input
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T6K41
Function Each Block
MPU interface unit
The T6K41 can be operated with an 80-Series MPU, 68-Series MPU or a serial interface. Figure 1 shows an example of interface.
RESET
D0 to 7 RD 80-Series WR MPU An An + 1 An + 2
RST DB0 to 7 RD T6K41 WR D/I RS CS1
RESET
D0 to7 RD 68-Series WR MPU An An + 1 An + 2
RST DB0 to 7 RD T6K41 WR D/I RS CS1
(CS2 = VDD)
(CS2 = VDD/CS1 = VSS)
Case of 80-Series MPU (Using CS1 signal)
Case of 68-Series MPU
RESET
RST
MPU
SO SCK SI
SI SCK SO
T6K41
(CS2 = VDD/CS1 = VSS)
Case of serial interface
Figure 1
The T6K41 selects an 8-bit parallel or serial interface, allowing for data to transferred from the MPU.
P/S
68/80
Interface Type 80-Series MPU ( CS1 ) 80-Series MPU (CS2)
CS1
CS2 H An + 2 H H
D/I An An An L/H
RS An + 1 An + 1 An + 1 L/H
WR WR WR
RD RD RD
SO Open Open Open SO
SI L/H L/H L/H SI
SCK L/H L/H L/H SCK
DB0 to 7 DB0 to 7 DB0 to 7 DB0 to 7 Open
An + 2 L L L
L H H L L
68-Series MPU Serial
R/W L/H
E L/H
Note 5: H denotes the VDD level; L denotes the VSS level.
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T6K41

SCK SI
0
0
R/W RS
D/I DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

SCK SI
0
0
R/W RS
D/I
SO
*
0
0
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
*: Dummy Data
Figure 2
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T6K41
Register select circuit
This circuit transfers a register chosen by command to the data. T6K41 has R0 to R31 registers. The R23 to R31 registers are provided for test. Do not choose these registers.
Input register
This register stores 8-bit data from the MPU. The D/I signal discriminate between command data and display data.
X-address counter
The X-address counter is a 128-Up/Down counter. It holds the row address of the display RAM. When this counter is selected by a command, it is automatically incremented or decremented each time data is read or written to the display RAM.
Y (page) -address counter
The Y (page) -address counter is a 32-Up/Down counter. It holds the column address of the display RAM. When this counter is selected by a command, it is automatically incremented or decremented each time data is read or written to the display RAM.
Z-address counter
The Z-address counter is a 128-Up counter used to supply the display data stored in the display RAM to the LCD drive circuit. This counter is incremented by CL signal. The data held in the Z-address register is loaded into this counter as Z-address. For instance, when Z start address is 16, the counter increment like this: 16, 17, ,18..., 127, 128, 1, 2..., 14,15,16. Therefore, the display start line is 16-line of the display RAM.
X/Y counter up/down register
This register holds the data that selects the up-count or down-count mode for the X and Y counters.
X/Y counter select register
The register holds the data that selects the X or Y counter to be used.
Display ON/OFF register
This register holds the data that determines whether the display be turned ON or OFF. When turned OFF, the output data turns to default level. When turned ON, the display data appears according to the display RAM data. The display ON or OFF state does not affect the data of display RAM.
Duty cycle control register
This register holds the data that sets one of the four duty cycles that can be used.
FRS control register
This register holds FRS control data.
Contrast control register
This register holds contrast control data.
Oscillator control register
This register holds the data that controls oscillator.
Static icon control register
This register holds the data that controls static icons. The static icons are usually independent of the LCD drive circuit for a normal display, and holds contrast control data, display ON/OFF data, and blink control data.
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T6K41
Analog circuit ON/OFF register
This register holds the data that determines whether the internal analog circuit be turned ON or OFF.
Z-address register
This register holds the data that determines the display start line. By setting Z-address in this register successively, it is possible to scroll the display up or down.
Shift register
T6K41 has two 64-bit shift registers necessary to shift the turn-on data required for the LCD drive common signals.
Latch circuit
The circuit latches the data from the display RAM.
LCD drive circuit (segment)
The segment driver circuit consists of 128 driver circuits. One of the four LCD driving level is selected by the combination of M (internal signal) and the display data transferred from the latch circuit. Details of segment driver circuit are shown in Figure 3.
VLC5 Vcon VLC0 Display data VLC3 Vcoff VLC2 SEG1 to SEG128
M
Figure 3
LCD driver circuit (common)
The common driver circuit consists of 128 driver circuits. One of the four LCD driving level is selected by the combination of M (internal signal) and the data from the shift register. Details of common driver circuit are shown in Figure 4.
VLC0 Vcon VLC5 Display data VLC4 Vcoff VLC1 SEG1 to SEG128
M
Figure 4 15 2002-01-08
T6K41
FRC (Frame Rate Control) circuit
The circuit controls ON/OFF of PWM data in each frame for generating the gray scale level. PWM (Pulse Width Modulation) is performed by gray scale data (the 2-bit display RAM data correspond to gray scale data). The gray scale data also determines whether PWM data is assigned to which frame.
Timing generation circuit
The circuit divides the signals from the oscillator and generates display timing signals and operating clock.
Op-Amp, Bias control circuit and Voltage divider resistors
The T6K41 has five op-amp for supplying LCD driving levels. To maintain good LCD contrast, connect a capacitor between the op-amp output and VSS. The value of the capacitor should normally be 0.1 mF. One of four biases can be selected by a bias control command.
VCC Output circuit RS Rb DB0 to 7 Decoder Rb Bias control register VLC2 VLC1 VLC0
8Rb
7Rb
6Rb
5Rb VLC3 Rb VLC4 Rb VLC5
Rb = 1400kW
Figure 5
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2002-01-08
T6K41
Oscillator
The T6K41 has two oscillators for normal display mode and partial display mode. When using internal oscillators, connect an external resistor for normal display mode between OCS1 and OSC2 and connect an external resistor for partial display mode between OSC1 and OSC3. When using external clock, input the clock to OSC1 after setting up Oscillation control resister data, as shown in Figure 7.
STB
C OSC1
Rf1
Internal Circuit
OSC2 PD Rf1: External resistor for normal display mode Rf2: External resistor for partial display mode
Rf2
OSC3 PD
Figure 6

STB
OSC1 External clock
Internal Circuit
Figure 7
Static icon driver circuit
T6K41 has 16 static icons. Since this circuit is driven on logic system voltage (VDD), the terminal of S1 to S16 and COMS outputs the LCD drive waveform of the level between VDD to VSS. The static icon is driven by 1/2duty and contrast adjustment is performed by changing the phase of an output waveform, as shown in Figure 8. The ON period ratio of the drive voltage for the static icon is adjusted by changing the phase of the waveform between the COMS pin and S1 to S16 pins.
ON Term (Width after contrast adjustment) COMS VDD VSS S1 to S16 VDD VSS
Figure 8
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2002-01-08
T6K41
DC-DC converter
T6K41 contains a 4/5/6 DC-DC converter. This circuit boosts by an external capacitor (charge pump system). By supping voltage to VIN, this circuit can generate the boosted voltage selected by the command, and outputs the voltage from VOUT. The boosted voltage is fed back to DC-DC converter circuit and the voltage adjusted by contrast control circuit is again outputted from VOUT. When using a DC-DC converter, short VOUT and VCC. As for the output voltage of VOUT, 15.4 V or 13.0 V is the maximum value after a contrast control setup. Since more than 15.4 V or more than 13.0 V is not outputted, please be careful. In partial display mode, the DC-DC converter automatically changes to 2 or 3 mode. The output voltage of VOUT is VIN level in a standby state (/STB = "L") or a reset state (/RST = "L"). Refer to Figure 9 for the capacitor connection.
VDD VIN VCC VOUT
C2
C1A
C1
C1B C2A
C1
VDD VIN VCC VOUT
C1A
C1
C1B C2A
C1
VDD VIN VCC VOUT
C1A C1B C2A C2B C3A C3B C4A
C1 C1 C1
C2B C3A
C1 C2
C2B C3A
C1
C3B C4A
C1
C3B C4A
C1
C4B C5A VSS
C1
C2
C4B C5A VSS C5B VSS
C4B C5A C5B C1: 0.1 mF C2: 2.2 mF
C5B
When using 6 moder
When using 5 Booster
When using 4 Booster
Note 6: Please set the capacitor value of C1 and C2 as the following ratio to suit the circuit characteristic. C1:C2 = 1:More than 20
Figure 9
Contrast control circuit
The contrast control circuit feeds back the voltage outputted from VOUT through built-in variable resistance, and outputs again contrast adjustment voltage to VOUT. Therefore, the output voltage of VOUT is the maximum of LCD drive voltage adjusted by contrast control circuit.
VLC0 Contrast control VCC VOUT DC-DC converter
Figure 10
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2002-01-08
T6K41
Command Definition
Command Set register Status read Counter mode Display mode Set power control Set duty/bias Oscillator control Set X/Y-address Set Z-address Set normal display contrast Set static icon contrast Set static icon register (1) Set static icon register (2) Set static icon register (3) Set static icon register (4) Set partial display mode Set alternating period Reg. No.
3/4 3/4
D/I 0 0 0 0 0 0 0 0 0
RS 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
WR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RD
DB7 0
*
DB6 0
*
DB5 0 PD 0 SDR
3/2
DB4
DB3
DB2
DB1
DB0
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Register (0 to 31) N/F 0 0 0 SI 0 PD 0 0 0 0 DP 0 SI Hi/Lo 0 0 Y/X Y/X N/F OP U/D U/D DP DC
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
0 0
0 CDR
6/5/4
0 0 1 0 0
0 0 0
BIAS
DUTY EXT OSC
X-address (0 to 127) 0 0 Y-address (0 to 31) Z-address (0 to 127) Contrast control for normal display (0 to 255)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0
0
Contrast control for static icon display (0 to 63) S3 state S7 state S11 state S15 state Partial area size S2 state S6 state S10 state S14 state S1 state S5 state S9 state S13 state
S4 state S8 state S12 state S16 state BIAS 0 0
Partial start area (0 to 15) 0 FRS Control (0 to 7)
0
0
Gray scale data for normal display (1) GS data to RAM data "00" Gray scale data for normal display (2) GS data to RAM data "01" Gray scale data for normal display (3) GS data to RAM data "10" Gray scale data for normal display (4) GS data to RAM data "11" Test mode (Do not access these registers.) Write data Read data
Gray scale pallet for normal display
R18 R19 R20 R21 R22
Test mode Data write Data read
R23 to R31
3/4 3/4
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2002-01-08
T6K41
* Set register T6K41 has registers for command (R0 to R31). But, R23 to R31 registers are provided for LSI test. Do not access these registers. If you access these registers inadvertently, you must be execute a re-setup of a register after executing reset function of T6K41. R0: Counter mode
D/I Code 0 RS 1 WR 0
RD
*
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 Y/X
DB0 U/D
1
Y/X:
U/D:
Selects Y-Counter or X-Counter. Y/X = 1: Y-Counter is selected. Y/X = 0: X-Counter is selected. Selects Up mode or Down mode. U/D = 1: Up mode is selected. U/D = 0: Down mode is selected.
*
R1: Display mode
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6 CDR
DB5 SDR
DB4 0
DB3 PD
DB2 SI
DB1 N/F
DB0 DP
1
CDR: Sets the common data scanning direction. CDR = 1: Data is scanned in the direction COM1 (R) COM128. CDR = 0: Data is scanned in the direction COM128 (R) COM1. SDR: Sets the segment data direction. SDR = 1: SEG1 (R) SEG4 with respect to the data direction DB7 (R) DB0. SDR = 0: SEG1 (R) SEG4 with respect to the data direction DB0 (R) DB7. Note 7: For details, see Figure 11 on Function Description. PD: Turns partial display ON or OFF. DP = 1: Partial display is turned ON DP = 0: Partial display is turned OFF. (Normal display) Turns static icons ON or OFF. SI = 1: Static icons are turned ON. SI = 0: Static icons are turned OFF. Selects between normal display and icon display modes. N/F = 1: Normal display mode is selected. N/F = 0: Icon display mode is selected.
SI:
N/F:
Display mode
Display Mode Normal display mode Power save mode Normal Display valid invalid Static Icons valid valid
Note 8: When power save mode (icon display mode) is selected, only static icon can be displayed. DP: Turns display ON or OFF. DP = 1: Display is turned ON. DP = 0: Display is turned OFF.
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2002-01-08
T6K41
* R2: Set power control
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
3/2
DB4 0
DB3 0
DB2 Hi/Lo
DB1 OP
DB0 DC
1
6/5/4
6/5/4: Selects booster level in Normal Display mode
DB7 1 0 0 DB6 0 1 0 Booster
6 5 4
3/2: Selects booster level in Partial Display mode. 3/2 = 1: 3 booster 3/2 = 0: doubler Hi/Lo: Selects LCD drive voltage (VOUT). Hi/Lo = 1: VOUT = 15.4 V (typ.) Hi/Lo = 0: VOUT = 13.0 V (typ.) OP: Controls op-amp for driving LCD. OP = 1: Op-amp for driving LCD ON OP = 0: Op-amp for driving LCD OFF (Externally supply VCC and VLC1 to VLC4 via op-amp.) DC: Controls booster (DC-DC converter). DC = 1: Booster ON DC = 0: Booster OFF
*
R3: Set Duty/Bias Sets duty/bias in Normal Display mode.
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6 0
DB5
DB4
DB3 0
DB2 0
DB1
DB0
1
BIAS (0 to 3)
DUTY (0 to 3)
BIAS: Sets a power supply bias for LCD drive.
DB5 1 1 0 0 DB4 1 0 1 0 Set to 1/12 bias. Set to 1/11 bias. Set to 1/10 bias. Set to 1/9 bias.
DUTY : Sets a display duty cycle.
DB1 1 1 0 0 DB0 1 0 1 0 Set to 1/128 duty Set to 1/100 duty Set to 1/80 duty Set to 1/72 duty
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2002-01-08
T6K41
* R4: Oscillation control
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 EXT
DB0 OSC
1
EXT: Switches input. EXT = 1: Inputs external clock. EXT = 0: Uses internal oscillator. OSC: Controls internal oscillator. OSC = 1: Internal oscillator ON OSC = 0: Internal oscillator OFF Switching between Normal Display and Partial Display modes switches oscillator resistor when an internal oscillator is used (EXT = 0). Normal Display mode: resistor between OSC1 and OSC2 Partial Display mode: resistor between OSC1 and OSC3 Divides the frequency from the selected oscillator to obtain the static icon clock. To switch between Normal Display and Partial Display modes using external clock input, the clock frequency must be changed according to the display mode.

OSC3
OSC2
OSC1
OSC3
OSC2
OSC1
In Partial Display mode
In Non-Partial Display mode

External clock
Recommended frequency
(VDD = 3.0 V, FR = 70 Hz, Ta = 25C)
Display Mode Duty 1/128 Normal display 1/100 1/80 1/72 1/32 1/24 Partial display mode 1/16 1/8 Frequency (typ.) Fosc2 = 80.64 kHz Fosc2 = 63.0 kHz Fosc2 = 50.4 kHz Fosc2 = 45.36 kHz Fosc3 = 20.16 kHz Fosc3 = 15.12 kHz Fosc3 = 10.08 kHz Fosc3 = 5.04 kHz
OSC3
OSC2
OSC1
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2002-01-08
T6K41
* R5: Set X/Y-address
D/I Code 0 RS 1 WR 0
RD
DB7 1 0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
X-address (0 to 127) 0 0 Y-address (0 to 31)
(1)
(2)
Set X-address Setting DB7 to 1 acknowledges an X-address. The address is controlled as a vertical address of the screen image. Using the X-up/down counter automatically enables write and read. The X-up/down counter counts addresses on the specified horizontal line only. Set Y-address Setting DB7 to 0 acknowledges a Y-address. The address is controlled as a horizontal address of the screen image. Using the Y-up/down counter automatically enables write and read. The Y-up/down counter counts addresses on the specified vertical line only.
*
R6: Set Z-address
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Z-address (0 to 127)
Sets the start line of display RAM. Setting this address enables vertical scrolling. For the scroll function, see the detailed description.
*
R7: Set normal display contrast
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Contrast control (0 to 255)
Sets contrast control of the Normal Display area. When set to 0, contrast is the minimum. When set to 255, contrast is the maximum. Note 9: that if a doubler is selected in Partial Display mode, set DB7 = 1 and set a step from 1 to 128.
*
R8: Set static icon contrast
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6 0
DB5
DB4
DB3
DB2
DB1
DB0
1
Contrast control (0 to 63)
Sets contrast control of the static icon area. When set to 0, contrast is the minimum. When set to 63, contrast is the maximum. The ON period ratio of the drive voltage for the static icon area is adjusted by changing the phase of the waveform between the COMS pin and pins S1 to S16.
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2002-01-08
T6K41
* R9: Set static icon register (1)
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
S4 state
S3 state
S2 state
S1 state
Sets ON/OFF of static icons S1 to S4. When a static icon is ON (R1: SI = 1), S1 to S4 are turned on according to the setting of this register. When a static icon is OFF (R1: SI = 0), the display is off regardless of the setting of this register. Static icon states vary as shown below according to the 2-bit data.
S1 to S16 state
0 0 1 1 0 1 0 1 OFF ON (Blinks at intervals of about 1 second) ON (Blinks at intervals of about 0.5 seconds) ON
Turned off
Approx. 1 s
Turned off
Turned on
Turned on
Turned off
Turned on
*
R10: Set static icon register (2)
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
S8 state
S7 state
S6 state
S5 state
Sets ON/OFF of the static icons S5 to S8. When a static icon is ON (R1: SI = 1), S5 to S8 are turned on according to the setting of this register. When a static icon is OFF (R1: SI = 0), the display is off regardless of the setting of this register.
*
R11: Set static icon register (3)
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
S12 state
S11 state
S10 state
S9 state
Sets ON/OFF of the static icon S9 to S12. When a static icon is ON (R1: SI = 1), S9 to S12 are turned on according to the setting of this register. When a static icon is OFF (R1: SI = 0), the display is off regardless of the setting of this register.
*
R12: Set static icon register (4)
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
S16 state
S15 state
S14 state
S13 state
Sets ON/OFF of the static icon S13 to S16. When a static icon is ON (R1: SI = 1), S13 to S16 are turned on according to the setting of this register. When a static icon is OFF (R1: SI = 0), the display is off regardless of the setting of this register.
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2002-01-08
T6K41
* R13: Set partial display mode
D/I Code 0 RS 1 WR 0
RD
DB7 Bias
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Partial area size
Partial start area
Set partial start area
DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Start Area 0 1 2 3 4
COM1 SEG1 SEG128
5 6 7 8 9 10 1 12 13 14
COM121 COM128 COM9 COM17
Area 0 Area 1 Area 2
Area 15
Sets the partial display start area. The partial display start area can be specified in units of 8 lines (8 COMs).
Set partial area size
DB5 0 0 1 1 DB4 0 1 0 1 Partial Area Size 8 lines mode 16 lines mode 24 lines mode 32 lines mode
Sets the partial display area size. A partial display area of the set size is displayed from the partial display start area.
Set bias
DB7 0 0 1 1 DB6 0 1 0 1 BIAS 1/4 bias 1/5 bias 1/6 bias 1/7 bias
Sets bias in Partial Display mode.
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2002-01-08
T6K41
* R14: Set alternating period
D/I Code 0 RS 1 WR 0
RD
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2
DB1
DB0
1
FRS Control (0 to 7)
This command sets the number of lines at which intervals the polarity of the frame signal (alternating signal) is switched over.
DB2 1 1 1 1 0 0 0 0 DB1 1 1 0 0 1 1 0 0 DB0 1 0 1 0 1 0 1 0 FR signal inverts on every 19 lines. FR signal inverts on every 17 lines. FR signal inverts on every 13 lines. FR signal inverts on every 11 lines. FR signal inverts on every 7 lines. FR signal inverts on every 5 lines. FR signal inverts on every 3 lines. In case 1/n duty is selected by R3, FR signal inverts on every n lines.
*
R15 to R22: Gray scale pallet for normal display
D/I RS WR
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R15/16: Gray scale data for normal display (1) Code 0 1 0 1 R17/18: Gray scale data for normal display (2) R19/20: Gray scale data for normal display (3) R21/22: Gray scale data for normal display (4)
This register stores the data for generating the gray scale level. The gray scale is created by pulse width modulation (PWM) and frame rate control (FRC). Use two registers for each gray scale level. Set the PWM data for the first to fourth frames in these registers. Four bits of PWM data are eliminated from a frame. Four frames are used to display one gray scale level. Frames (1) to (4) above correspond to display data 00, 01, 10 and 11, respectively. Any gray scale level is assigned to the display data values (00, 01, 10 and 11).
Frame Rate control (FRC) setting
The T6K41 determines the gray scale level by specifying the PWM to be performed in the four frames. The correspondence between frame control order and the registers is shown in the table below.
Register R15/R17/R19/R21 R16/R18/R20/R22 DB7 DB6 DB5 Data Bus DB4 DB3 DB2 DB1 DB0
Data eliminated from second frame Data eliminated from fourth frame
Data eliminated from first frame Data eliminated from third frame
Note 10: Eliminated data are PWM data.
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2002-01-08
T6K41
PWM (pulse width modulation) setting
The T6K41 determines the gray scale level by dividing the segment data ON waveform by nine. The data to be written to the register are selected from the gray scale levels listed below.
BIN 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 1111 HEX 00 01 02 03 04 05 06 07 08 09 0A to 0F PWM (on width) 0 (0/9) 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1 (9/9) 0 (0/9) These data select off level (0 level). Note
Note 11: Optimization by combination of PWM and FRC data depends on the characteristics of the LCD.
*
R23 to R31: Test mode
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Test mode
This command selects a test mode, so do not use it. If you've used this test command inadvertently, deassert it by pulling the RST input low
*
Data Write
D/I Code 0 RS 1 WR 0
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
Write data
Writes 8-bit data to display RAM. Using the X/Y counter automatically counts up/down addresses after specifying the start address so that data can be written.
*
Data Read
D/I Code 1 RS 1 WR 1
RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
Read data
Reads 8-bit data from display RAM. Using the X/Y counter automatically counts up/down addresses after specifying the start address so that data can be read.
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2002-01-08
T6K41
* Status read
D/I Code 0 RS 0 WR 1
RD
DB7
*
DB6
*
DB5
*
DB4 N/F
DB3 SI
DB2 DP
DB1 Y/X
DB0 U/D
0
N/F (DB4): Identifies Normal Display mode or Power Save mode. N/F = 1: Indicates Normal Display mode. N/F = 0: Indicates Power Save mode. SI (DB3): Identifies static icon ON/OFF. SI = 1: Static icon ON SI = 0: Static icon OFF DP (DB2): Identifies display ON/OFF. DP = 1: Display ON DP = 0: Display OFF Y/X (DB1): Identifies Y or X counter. Y/X = 1: Y counter is selected. Y/X = 0: X counter is selected. U/D (DB0): Identifies Counter Up or Down mode. U/D = 1: Counter Up mode U/D = 0: Counter Down mode
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2002-01-08
T6K41
Reset Function
The T6K41 has a RST pin. When input to this pin is pulled low, the T6K41 is reset, with its internal circuits (register contents) initialized as shown below.
Command Counter mode Reg. No. R0 D7 0
*
D6 0
*
D5 0
*
D4 0
*
D3 0
*
D2 0
*
D1 1 Y/X 1 N/F 0 OP 1 DUTY 1 EXT 0
D0 1 U/D 0 DP 0 DC 1
Display mode
R1
0
*
1 CDR 0
1 SDR 0
3/2
0
*
0 PD 0
*
0 SI 1 Hi/Lo 0
*
Power control
R2
1
6/5/4
0
*
Set Duty/Bias
R3
0
*
0
*
1 BIAS 0
*
1
0
*
Oscillator setting
R4
0
*
0
*
0
*
0
*
0
*
1 OSC 0
Set X/Y-address
R5
0
*
0
0
0
0
0
X-address/Y-address 0 0 0 0 Z-address 0 0 0 0 0 0 0 0 0 0
Set Z-address Contrast setting in Normal Display mode Contrast setting for static icon
R6
0
*
R7
0
Contrast control data for normal display R8 0
*
0
*
0
0
0
0
0
0
Contrast control for static icon 0 0 0 0 0 0
Static icon setting
R9 to R12
0
0
S1 to S16 states (specify in two bits) 0 Partial display setting R13 BIAS Alternating current signal setting R14 0
*
0
0 Area size
0
0
0 Display start area
0
0
0
*
0
*
0
*
0
*
0
0
0
Alternating current signal 0 0 0
Setting of gray scale pallet for normal R15 to R22 display
0
0
0
0
0
Gray scale data for normal display
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2002-01-08
T6K41
Function Description
* Display data bit (1) When SDR = 1
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8
LCD display
GS3
GS2
GS1
GS0
GS3
GS2
GS1
GS0
LCD control
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
Display RAM bit
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 page
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 page
(2) When SDR = 0
SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121
LCD display
GS3
GS2
GS1
GS0
GS3
GS2
GS1
GS0
LCD control
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
Display RAM bit
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 page
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 page
Figure 11
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2002-01-08
T6K41
* The relationship between the Duty and the LCD drive common signal output
T6K41 can change Duty by command setup. When CDR = 1, assignment of LCD drive common signal output (COM) pins are as shown below.
Number of using pins 128 100 80 72
Duty 1/128 duty 1/100 duty 1/80 duty 1/72 duty
Assignment of COM pins COM1***COM128 COM1 *** COM50, COM65 *** COM114 COM1 *** COM40, COM65 *** COM104 COM1 *** COM36, COM65 *** COM100
*
Partial Display function The T6K41 has the partial display function for displaying arbitrary area by command setup. The partial display area size can be selected from 8 lines, 16 lines, 24 lines, or 32 lines. The partial start area (start line) can be selected from the following table.
Partial Start Area No 0 1 2 3 4 5 6 7 Display Start Line COM1 COM9 COM17 COM25 COM33 COM41 COM49 COM57 Partial Start Area 8 9 10 11 12 13 14 15 Display Start Line COM65 COM73 COM81 COM89 COM97 COM105 COM113 COM121
R13 x0H x1H x2H x3H x4H x5H x6H x7H
R13 x8H x9H xAH xBH xCH xDH xEH xFH
Note 12: x: Invalid
Z address determines the effective display RAM area. For instance, when the partial display area size is set to 16 lines and the partial start area no. is set to 0, the data of effective display RAM area shown below by Z-address setup is displayed on 16 lines from COM1. When Z-address (ZAD) is set to 0, the range of XAD = 0 to XAD = 15 are effective When Z-address (ZAD) is set to 30, the range of XAD = 30 to XAD = 46 are effective.
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2002-01-08
T6K41
* Expansion function The T6K41's expansion function, allows two, T6K41s to drive an LCD panel of up to 256 by 128 dots. The table below shows the timing signals state by using M/S pin.
Timing signal output/input for Expansion CL H L Output Input PM Output Input FR Output Input CK Output Input SYNC Output Input BLNK Output Input
M/S
The table below shows the selectable function by using M/S pin.
M/S H
Single-chip mode Disable expansion mode Two-chip mode (Master chip) Timing signals and power voltage supply to Slave chip.
L
Two-chip mode (Slave chip) Timing signals and power voltage are supplied from Master chip.
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2002-01-08
T6K41
LCD Drive Waveform (Normal Display mode)
V0 V1 V4 COM1 V5 V1 V4 COM2 V0 V1 V4 COM12 V5 V5 V0 V1 V4 V4 V0 V4 V5 V1
V0 V2 V3 SEG1 V0 V2 V3 SEG128 V5 V3 V5 V3
V0
V0
ON
OFF
ON
OFF
LCD Drive Timing Chart (1/128 duty)
Maximum Ratings
Characteristics Power supply voltage (1) Symbol VDD, VIN (Note 13) VLC0, 1, 2, 3, 4, 5, VCC, VOUT Vinp (Note 13, 14) Topr Tstg Rating
-0.3 to 6.0
Unit V
Power supply voltage (2)
VSS + 18.0 to VSS - 0.3
-0.3 to VDD + 0.3 -30 to 85 -55 to 125
V
Input voltage Operating temperature Storage temperature
V C C
Note 13: Value based on VSS = 0 V Note 14: Applies to input and data bus excluding VCC, VOUT, VLC0, VLC1, VLC2, VLC3, VLC4 and VLC5.
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T6K41
Electrical Characteristics (1)
(Test Conditions: Unless Otherwise Noted, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics Operating voltage (1) Operating voltage (2) Normal Operating voltage display (3) Partial display High level Input voltage Low level VIL
3/4 3/4
Symbol VDD VIN VCC VCC VIH
Test Test Condition Circuit
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Min 2.4 2.7 6.0 VSS 4.0 VSS 0.8 VDD 0 VDD 0.2 0
3/4 3/4 3/4
Typ.
3/4 3/4 3/4 3/4 3/4
Max 3.3 3.3 16.5 VSS 16.5 VSS VDD 0.2 VDD VDD 0.2 7.5 1.5 7.5
Unit V V V V V VDD VIN
Applicable
VCC, VOUT VCC, VOUT DB0 to DB7, D/I, WR , RD , CS1 , CS2, RS, P/S, 68/80, SI, SCK, RST , STB , CL, PM, FR, SYNC, CK, BLNK DB0 to DB7, SO, CL, PM, FR, SYNC, CK
3/4
V
High level Output voltage Low level Segment driver on-resistance Common driver on-resistance Static icon on-resistance Normal Display mode Normal Display mode Low Power Consumption mode
VOH VOL Rcol Rrow Ricon
3/4 3/4 3/4 3/4 3/4
IOH = -400 mA IOL = 400 mA (Note 15) (Note 15) (Note 16)
3/4 3/4 3/4 3/4 3/4
V V kW kW kW
SEG1 to SEG128 COM1 to COM128 COMS, S1 to S16 DB0 to DB7, D/I, WR , RD , CS1 , CS2, RS, P/S, 68/80, SI, SCK, RST , STB , CL, PM, FR, SYNC, CK, BLNK OSC1 OSC1 OSC1 OSC1 VSS VSS VSS VSS VSS
Input leakage current
IIL
3/4
Vinp = VDD to GND
-1
3/4
1
mA
Operating frequency External clock input frequency External clock duty External clock rise/fall time Current consumption (1) Current consumption (2) Current consumption (3) Current consumption (4) Current consumption (5)
fosc fex fduty tr/tf ISS1 ISS2 ISS3 ISS4 ISSSTB
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
(Note 22) (Note 22)
3/4 3/4
3/4 3/4
80.64 80.64 50
3/4
3/4 3/4
kHz kHz % ns
mA mA mA mA mA
45
3/4 3/4 3/4 3/4 3/4 -1
55 50 450 90 6 700 1
(Note 17) (Note 18) (Note 19) (Note 20) (Note 21)
300 60 4 500
3/4
Note 15: VCC = 10.3 V, Load current 100 mA, 1/9 bias Note 16: VDD = 3.0 V, Load current 100 mA, 1/4 bias Note 17: VDD = 3.0 V, VOUT = 15.4 V (6 booster), no data access, internal clock (OSC = 80.64 kHz), no load, 1/12 bias, 1/128 duty, op-amp on, regulator on, Normal Display mode (Gray Scale), display pattern: check Note 18: VDD = 3.0 V, VOUT = 5.2 V (doubler), no data access, internal clock (OSC = 5 kHz), no load, 1/4 bias, 1/8 duty, op-amp on, regulator on, Partial Display mode, display pattern: check Note 19: VDD = 3.0 V, no data access, internal clock (OSC = 5.04 kHz), no load, op-amp off, regulator off, Low Power Consumption mode Note 20: VDD = 3.0 V, VOUT = 6 booster, data access cycle (f/CE = 1 MHz), internal clock (OSC = 82 kHz), no load, 1/12 bias, 1/128 duty, op-amp on, regulator on Note 21: VDD = 3.3 V, VCC - VSS = 16.0 V, STB = "L" Note 22: 1/128 duty, fFR = 70 Hz
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T6K41
Electrical Characteristics (2)
(Test Conditions: Unless Otherwise Noted, VSS = 0 V, VDD = VIN = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics Regulator reference high voltage (1) (Hi/Lo = 1) Regulator reference high voltage (2) (Hi/Lo = 0) Regulator reference high voltage (3) (Partial display mode) Regulator reference high voltage temperature gradient Symbol VHR1 VHR2 VHR3 Test Test Condition Circuit
3/4 3/4 3/4 3/4
Min 15.3 12.9 7.9
Typ. 15.4 13.0 8.0
-0.05
Max 15.5 13.1 8.1
Unit V V V VOUT VOUT VOUT
Applicable
Ta = 25C (Note 23) Ta = 25C (Note 24) Ta = 25C (Note 24) Ta = -20 to 60C (Note 23)
VHRINC
TBD
TBD
%/C
VOUT
Note 23: VDD = VIN = 3.0 V, contrast = max, no display load, Normal Display mode Note 24: VDD = VIN = 3.0 V, contrast = max, no display load, Partial Display mode
Electrical Characteristics (3)
(Test conditions: unless otherwise specified, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics Op-amp output voltage offset (1) Op-amp output voltage offset (2) Op-amp output voltage offset (3) Symbol Vopoff Vopoffs1 Vopoffs2 Test Test Condition Circuit
3/4 3/4 3/4
Min
-100 -100 -130
Typ.
3/4 3/4 3/4
Max 100 100 130
Unit mV mV mV
Applicable VLC0, VLC1, VLC2, VLC3, VLC4 VLC0, VLC1, VLC2, VLC3, VLC4 VLC0, VLC1, VLC2, VLC3, VLC4
(Note 25) (Note 26) Iload = 100 mA
Note 25: VDD = 2.7 to 3.3 V, VSS = 0 V, 1/12 bias, 1/128 duty, VCC = 15.4 V, op-amp on, no load VLC0: VLC0 = Vopoff VLC1: (VLC0 11/12) - VLC1 = Vopoff VLC2: (VLC0 10/12) - VLC2 = Vopoff VLC3: (VLC0 2/12) - VLC3 = Vopoff VLC4: (VLC0 1/12) - VLC4 = Vopoff Note 26: VDD = 2.7 to 3.3 V, VSS = 0 V, 1/12 bias, 1/128 duty, VCC = 16.0 V, op-amp on, no load Vopoff1 = ((VLC1 - VLC2) - (VLC0 - VLC1)) + ((VLC3 - VLC4) - (VLC4 - VLC5)) Vopoff2 = ((VLC1 - VLC2) - (VLC0 - VLC1)) + ((VLC3 - VLC4) - (VLC4 - VLC5))
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T6K41
Test Circuit
(1) With doubler
VDD OSC1 R2 OSC3
VIN C1A C1 C1B
OSC = 5.04 kHz C1 = C2 = 1.0 mF Iload = 100 mA
VOUT VSS VCC
Iload C2
A External power supplied
(2) With 3 booster
VDD OSC1 R2 OSC3
VIN C1A C1 C1B C2A C1 C2B OSC = 20.16 kHz C1 = C2 = 1.0 mF Iload = 100 mA
VOUT VSS VCC
Iload C2
A External power supplied
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T6K41
(3) With 4 booster
VDD OSC1 R1 OSC2
VIN C1A C1 C1B C2A C1 C2B C3A C1 C3B OSC = 40.32 kHz C1 = C2 = 1.0 mF Iload = 200 mA
VOUT VSS VCC
Iload C2
A External power supplied
(4) With 5 booster
VDD OSC1 R1 OSC2
VIN C1A C1 C1B C2A C1 C2B C3A C1 C3B C4A C1 C4B VOUT Iload C2 A External power supplied OSC = 63 kHz C1 = C2 = 1.0 mF Iload = 200 mA
VSS
VCC
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T6K41
(5) With 6 booster
VDD OSC1 R1 OSC2
VIN C1A C1 C1B C2A C1 C2B C3A C1 C3B C4A C1 C4B C5A C1 C5B VOUT Iload C2 A External power supplied OSC = 80.64 kHz C1 = C2 = 1.0 mF Iload = 200 mA
VSS
VCC
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T6K41
Switching Characteristics (1) (8-bit 80 series MPU interface)
D/I
VIH VIL
VIH VIL tAH
CS1 (CS2 = H)
VIL tAS tEf PWEL tEr VIL tDS VIH
VIL
WR
VIH
VIL
VIH
tDHW Valid data VIH VIL
Data Write
VIH VIL tEf
tEr VIL tDD VIH VIH
RD
VIH
VIL
tDHR VOH VOL Valid data tcycE VOH VOL
Data Read
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Load Circuit Characteristics Enable cycle time Enable pulse width Enable rise/fall time Address setup time Address hold time Data setup time Write data hold time Data delay time Read data hold time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note 27) tDHR (Note 27) Min 500 410
3/4
Max
3/4 3/4
Unit DB0 to 7 CL
25
3/4 3/4 3/4 3/4
20 0 100 20
3/4
CL = 100 pF (including wiring capacitance) ns
300
3/4
20
Note 27: When the load circuit shown is added
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T6K41
Switching Characteristics (2) (8-bit 68 series MPU interface)
D/I
VIH VIL
VIH VIL tAH
R/W ( WR )
VIL tAS tEr PWEH tEf VIL VIH
VIL
E ( RD )
VIH
VIL
VIH tDHW
tDS Data Write tDD Data Read VOH VOL VIH VIL
Valid data tDHR Valid data tcycE
VIH VIL
VOH VOL
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics Enable cycle time Enable pulse width Enable rise/fall time Address setup time Address hold time Data setup time Write data hold time Data delay time Read data hold time Symbol tcycE PWEH tEr, tEf tAS tAH tDS tDHW tDD (Note 28) tDHR (Note 28) Min 500 410
3/4
Max
3/4 3/4
Unit
Load Circuit
DB0 to 7 CL
25
3/4 3/4 3/4 3/4
20 0 100 20
3/4
ns
CL = 100 pF (including wiring capacitance)
300
3/4
20
Note 28: When the load circuit shown is added
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T6K41
Switching Characteristics (3) (serial interface)
tcycC PWCL PWCH
SCK
VIL
VIL tDS
VIH tCr tDH VIH VIL
VIH
VIL tCf
SI tDD SO
VIH VIL
VOH VOL
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics Enable cycle time Enable pulse width Enable rise/fall time Data setup time Data hold time Data delay time Symbol tcycC PWCL, PWCH tCr, tCf tDS tDH tDD Min 2000 900
3/4
Max
3/4 3/4
Unit
25
3/4 3/4
ns
250 100
3/4
200
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T6K41
Switching Characteristics (4)
VDST VDD VIH VRST RSTW RST VIL VIH
VIL
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = 15.5 V, Ta = 25C)
Characteristics VDD rise time Reset hold Reset pulse width Symbol VDST VRST RSTW Min
3/4
Max 1
3/4 3/4
Unit ms
ms ms
1 1
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T6K41
Application Circuit
T6K41 one chip (Master) mode
16 dot static icons
16 1
64
128 128 dot LCD
64
128
COM65 to COM128
IORQ
SEG1 to SEG128
COM1 to COM64 S1 to S16, COMS
Ax Ay Am MPU An WR RD DB0 to DB7 RESET
Decoder CS1 RS DI WR RD DB0 to DB7 RST 0.1 mF VLC0 VLC1 VLC2 VLC3 VLC4 VLC5 VREF Reset circuit VIN SCK CS2 68/80 P/S SI STB VSS VDD M/S VCC V OSC1 OSC2 OSC3 CnA CnB OUT 0.1 mF 2.2 mF
T6K41
8
0.1 mF
VSS
VDD
* * * * *
VDD = 3.0 V Using DC-DC converter (6) Using internal CR oscillator Using Op-amp 80-series parallel interface
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T6K41
RESTRICTIONS ON PRODUCT USE
000707EBE
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2002-01-08

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