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SPT7920
12-BIT, 10 MSPS, TTL, A/D CONVERTER
FEATURES
* * * * * * * * Monolithic 12-Bit 10 MSPS Converter 66 dB SNR @ 1 MHz Input On-Chip Track/Hold Bipolar 2.0 V Analog Input Low Power (1.1 W Typical) 5 pF Input Capacitance TTL Outputs
APPLICATIONS
* * * * * * * * Radar Receivers Professional Video Instrumentation Medical Imaging Electronic Warfare Digital Communications Digital Spectrum Analyzers Electro-Optics
GENERAL DESCRIPTION
The SPT7920 A/D converter is the industry's first 12-bit monolithic analog-to-digital converter capable of sample rates greater than 10 MSPS. On board input buffer and track/hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Logic inputs and outputs are TTL. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.1 watts with power supply voltages of +5.0 and -5.2 volts. The SPT7920 also provides a wide input voltage range of 2.0 volts. The SPT7920 is available in 32-lead ceramic sidebrazed DIP and 44-lead cerquad packages over the commercial temperature range. Consult the factory for availability of die, military temperature and /883 versions.
BLOCK DIAGRAM
VIN
Input Buffer
4-Bit Flash Converter 4 Error Correction, Decoding and Output TTL Drivers
Digital Output 12
Analog Gain Compression Processor
Track-and-Hold Amplifiers
Asynchronous SAR
8
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VCC ...........................................................................+6 V VEE ........................................................................... -6 V Input Voltages Analog Input ............................................... VFBVINVFT VFT, VFB. ................................................... +3.0 V, -3.0 V Reference Ladder Current ..................................... 12 mA CLK IN ...................................................................... VCC Note: Output Digital Outputs .............................................. 0 to -30 mA Temperature Operating Temperature ................................. 0 to +70 C Junction Temperature ......................................... +175 C Lead Temperature, (soldering 10 seconds) ........ +300 C Storage Temperature ................................ -65 to +150 C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error Reference Input Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Signal-to-Noise Ratio (without Harmonics) fIN=500 kHz fIN=1 MHz fIN=3.58 MHz TEST CONDITIONS TA=+25 C Full Scale 100 kHz Sample Rate TEST LEVEL MIN 12 SPT7920 TYP MAX UNITS Bits LSB LSB
V V VI VI I I V V V V VI V VI V IV V V V
2.0 0.8 Guaranteed 2.0 30 300 5 120 5.0 5.0 800 0.8
fCLK=1 MHz TA=+25 C VIN=0 V, TA=+25 C 3 dB Small Signal
60
100
V A k pF MHz LSB LSB /C MHz ns
fCLK=1 MHz 500
10 20 14 1 5 1 18
Clock Cycle
TA=+25 C TA=+25 C TA=+25 C
ns ns ps-RMS
10.2 10.0 9.5
Bits Bits Bits
TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX
I IV I IV I IV
64 58 64 58 62 58
67 61 66 60 64 60
dB dB dB dB dB dB
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle, unless otherwise specified. TEST CONDITIONS TEST LEVEL SPT7920 TYP
PARAMETERS Dynamic Performance Harmonic Distortion fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Signal-to-Noise and Distortion fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Spurious Free Dynamic Range1 Differential Phase2 Differential Gain2 Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) Digital Outputs Logic 1 Voltage Logic 0 Voltage Power Supply Requirements Voltages VCC DVCC -VEE Currents ICC DICC -IEE Power Dissipation Power Supply Rejection
MIN
MAX
UNITS
TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=TMIN to TMAX TA=+25 C TA=+25 C TA=+25 C fCLK=1 MHz TA=+25 C TA=+25 C TA=+25 C TA=+25 C
I IV I IV I IV I IV I IV I IV V V V I I I I IV IV I I IV IV IV I I I VI V
63 59 63 59 59 57 60 55 60 55 57 54
66 62 65 61 61 59 63 58 62 57 59 56 74 0.2 0.7 4.5 0.8 +20 +20 300
dB dB dB dB dB dB dB dB dB dB dB dB dB Degree % V V A A ns ns V V V V V mA mA mA W LSB
2.4 0 0 30 30 2.4 +5 +5
fCLK=1 MHz TA=+25 C TA=+25 C
0.6 4.75 4.75 -4.95 5.0 5.0 -5.2 135 40 45 1.1 1.0 5.25 5.25 -5.45 150 55 70 1.3
TA=+25 C TA=+25 C
+5 V 0.25 V, -5.2 0.25 V
Typical thermal impedances (unsoldered, in free air): 32L sidebrazed DIP: ja = +50 C/W 44L cerquad: ja = +78 C/W ja at 1 M/s airflow = +58 C/W jc = +3.3 C/W 1fIN = 1 MHz. 2fIN = 3.58 and 4.35 MHz.
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TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
Figure 1A: Timing Diagram
N N+1 N+2
t pwH
CLK
t pwL
td
OUTPUT DATA N-2 N-1 DATA VALID N DATA VALID N+1
Figure 1B: Single Event Clock
CLK
td
OUTPUT DATA
DATA VALID
Table I - Timing Parameters
PARAMETERS td tpwH tpwL DESCRIPTION CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width MIN 30 30 TYP 14 MAX 18 300 UNITS ns ns ns
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SPECIFICATION DEFINITIONS
APERTURE DELAY Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels that is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. DIFFERENTIAL NONLINEARITY (DNL) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) INTEGRAL NONLINEARITY (INL) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal.
N=
SINAD - 1.76 6.02
+/- FULL-SCALE ERROR (GAIN ERROR) Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage.
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PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
80 80
THD vs Input Frequency
70
70
fs = 10 MSPS
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
60
60
50
fs = 10 MSPS
50
40
40
30
30
20 10 -1 100 101
20 10-1 100 101
Input Frequency (MHz)
Input Frequency (MHz)
SNR, THD, SINAD vs Sample Rate
80
SINAD vs Input Frequency
80
60
Signal-to-Noise and Distortion (dB)
70
SNR, THD
fs =10 MSPS
70
SNR, THD, SINAD (dB)
60
SINAD
50
50
fIN = 1 MHz
40
40
30
30
20 10 0
20
Sample Rate (MSPS)
10 1
10 2
10 -1
100
101
Input Frequency (MHz)
SPT7920 Spectral Response
0
SNR, THD, SINAD vs Temperature
75
fS = 10 MSPS fIN = 1 MHz
SNR, THD, SINAD (dB)
-30
70
SNR
Amplitude (dB)
65
-60
THD
60
SINAD
-90
fS = 10 MSPS fIN = 1 MHz
55
-120 0 1 2 3 4 5
50
Frequency (MHz)
-25
0
+25
+50
+75
Temperature (C)
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TYPICAL INTERFACE CIRCUIT The SPT7920 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7920 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7920 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog VCC. These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7920 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 F for VEE and VCC, and 0.01 F for DV CC (chip caps are preferred). AGND and DGND are the two grounds available on the SPT7920. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead.
A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7920. VOLTAGE REFERENCE The SPT7920 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. The +2.5 V voltage source for reference VFT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are five reference ladder taps (VST, VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRT2 is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). VRT1 and VRT3 are quarter point ladder taps (+1.0 and -1.0 V typical, respectively). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). VST and VSB should be used to monitor the actual full scale input voltage of the device. VRT1, VRT2 and VRT3 should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 F connected to AGND from each tap is recommended to minimize high frequency noise injection.
Figure 2 - Typical Interface Circuit
R1 CLK
(TTL)
17 CLK 100
D12 VIN
14 (OVERRANGE) 13 12 11 10 9 8 7 6 5 4 3 2 (LSB)
D I G IT A L O UT P UT S
VIN
(2 V)
2.5 V Max
24
COARSE A/D
4
D11 D10 D9
(MSB)
D E C O D I N G N ETW O R K
+ 5V
C19 1 F
2
+
VIN
IC1
6
VOUT
+2.5 V
21
VFT
D8 D7 D6 D5 D4 D3 D2 D1
(REF-03) 4
GND Trim
5
10 k
+
1 F 30 k
C1 .01 F
C2 .01 F C3 .01 F C4 .01 F
22 VST 23 VRT3 25 VRT2
R
ANALOG PRESCALER
2R 2R 2R SUCCESSIVE INTERPOLATION STAGE # 1
3 1 10 k
2 4
+IC2
OP-07 8 7
- 5.2 V
C5 .01 F C17 .01 F 30 k C6 .01 F
26 VRT1 2R 27 VSB R SUCCESSIVE INTERPOLATION STAGE # N
+5 V
C18 .01 F
D0
6 -2.5 V C16 1 F C7 .01 F
28
VFB
DGND
AGND
DVCC
+ 18
31
19
C8 .1 F C9 .1 F
30
20
C10 C11
29
16
32
DVCC
1
15
C12 .01 F C13 .01 F
FB
Notes to prevent latch-up due to power sequencing: 1) D1 = Schottky or hot carrier diode, P/N IN5817. 2) FB = Ferrite bead, Fair Rite P/N 2743001111 to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C13 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for V CC and DVCC is not recommended. 5) R1 provides current limiting to 45 mA. 6) C8, C9, C10 and C11 should be ten times larger than C12 and C13. 7) C10 = C11 = 0.1 F cap in parallel with a 4.7 F cap.
DGND
AGND
VCC
VEE
VEE
VCC
FB
D1
C15 10 F
C14 10 F
+
+
FB
-5.2 V (Analog)
AGND
+5 V (Analog)
DGND
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Figure 3 - Analog Equivalent Input Circuit
VCC
VIN
ANALOG PRESCALER
VFT
The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due to the SPT7920's extremely low input capacitance of only 5 pF and very high input impedance of 300 k. For example, for an input signal of 2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 A. CLOCK INPUT The SPT7920 is driven from a single-ended TTL input (CLK). For optimal noise performance, the clock input slew rate should be a minimum of 6 ns. Because of this, the use of fast logic is recommended. The clock input duty cycle should be 50% where possible, but performance will not be degraded if kept within the range of 40-60%. However, in any case the clock pulse width (tpwH) must be kept at 300 ns maximum to ensure proper operation of the internal track and hold amplifier (see timing diagram). The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH 4.5 V, TRISE <6 ns). In the event the clock is driven from a high current source, use a 100 resistor in series to current limit to approximately 45 mA. DIGITAL OUTPUTS The format of the output data (D0-D11) is straight binary. (See table II.) The outputs are latched on the rising edge of CLK with a propagation delay of 14 ns (typ). There is a one clock cycle latency between CLK and the valid output data. (See timing diagram.) Table II - Output Data Information
ANALOG INPUT >+2.0 V + 1/2 LSB +2.0 V -1 LSB 0.0 V -2.0 V +1 LSB <-2.0 V OVERRANGE D12 1 O O O O OUTPUT CODE D11-DO 1111 1111 1111 1111 1111 111O
VEE
The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is 20% of the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with 2.5 V references, the accuracy of the device will degrade if operated beyond a 2% range. An example of a recommended reference driver circuit is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is 10 k and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. R1 and R4 should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. The following errors are defined: +FS error = top of ladder offset voltage = (+FS -VST) -FS error = bottom of ladder offset voltage = (-FS -VSB) Where the +FS (full scale) input voltage is defined as the output 1 LSB above the transition of 1--10 and 1--11 and the -FS input voltage is defined as the output 1 LSB below the transition of 0--00 and 0--01. ANALOG INPUT VIN is the analog input. The full scale input range will be 80% of the reference voltage or 2 volts with VFB=-2.5 V and VFT=+2.5 V.
OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO
(O indicates the flickering bit between logic 0 and 1). The rise times and fall times of the digital outputs are not symmetrical. The propagation delay of the rise time is typically 14 ns and the fall time is typically 6 ns. (See figure 4.) The nonsymmetrical rise and fall times create approximately 8 ns of invalid data.
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Figure 4 - Digital Output Characteristics
N N+1
CLK IN
2.4 V
Rise Time 6 ns 6 ns typ.
3.5 V
DATA OUT (Actual)
2.4 V
(N-2)
0.8 V 0.5 V
Invalid Data
(N-1)
Invalid Data
(N)
tpd1
(14 ns typ.)
DATA OUT (Equivalent)
(N-2)
Invalid Data
(N-1)
Invalid Data
(N-1)
OVERRANGE OUTPUT The OVERRANGE OUTPUT (D12) is an indication that the analog input signal has exceeded the full scale input voltage by 1 LSB. When this condition occurs, the outputs will switch to logic 1s. All other data outputs are unaffected by this operation. This feature makes it possible to include the SPT7920 into higher resolution systems.
EVALUATION BOARD The EB7920 evaluation board is available to aid designers in demonstrating the full performance of the SPT7920. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7920) describing the operation of this board as well as information on the testing of the SPT7920 is also available. Contact the factory for price and availability.
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PACKAGE OUTLINES
32-Lead Sidebrazed
32
H
I 1 G A E F C B D
SYMBOL A B C D E F G H I J INCHES MIN 0.081 0.016 0.095 0.040 0.175 1.580 0.585 0.009 0.600 0.225 1.620 0.605 0.012 0.620 MAX 0.099 0.020 0.105 .050 typ MILLIMETERS MIN 2.06 0.41 2.41 1.02 4.45 40.13 14.86 0.23 15.24 5.72 41.15 15.37 0.30 15.75 MAX 2.51 0.51 2.67 1.27
J
44-Lead Cerquad
INCHES SYMBOL A B C MIN 0.550 typ 0.685 0.037 0.016 typ 0.008 typ 0.027 0.006 typ 0.080 0.150 0.051 0.709 0.041 MAX MILLIMETERS MIN 13.97 typ 17.40 0.94 0.41 typ 0.20 typ 0.69 0.15 typ 2.03 3.81 1.30 18.00 1.04 MAX
C
D E F G H
D
A
B
0 - 5
H E F G
A B
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PIN ASSIGNMENTS
DGND D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26
PIN FUNCTIONS
DV CC V
EE
Name DGND AGND D0-D11 D12 CLK VEE VCC VRT1-VRT3 VIN DVCC VFT VST
Function Digital Ground Analog Ground TTL Outputs (D0=LSB) TTL Output Overrange Clock Input -5.2 V Supply +5.0 V Supply Voltage Reference Taps Analog Input Digital +5.0 V Supply (TTL Outputs) Force for Top of Reference Ladder Sense for Top of Reference Ladder Force for Bottom of Reference Ladder Sense for Bottom of Reference Ladder
AGND V V V
CC FB SB
VRT1 VRT2 V V
IN RT3
32L Sidebrazed
25 24 23 22 21 20 19 18 17
D8 10 D9 11 D10 12 D11 13 D12 14 DGND 15 DVCC 16
VST VFT V
CC
AGND VEE CLK
AGND
DVCC DGND
VFB VSB
33 32 31 30 29
VCC
VEE
N/C
N/C
N/C
42
N/C
DO
43
D1
44
36
39
35
38
41
34
37
40
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 N/C
1 2 3 4 5 6 7 8 9 10 11
N/C VFB VSB VRT1 VRT2 VIN VRT3 VST VFT N/C VCC
44L Cerquad
28 27 26 25 24 23
20
17
14
21
18
15
ORDERING INFORMATION
PART NUMBER SPT7920SCJ SPT7920SCQ TEMPERATURE RANGE 0 to +70 C 0 to +70 C PACKAGE 32L Sidebrazed Dip 44L Cerquad
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
12
22
19
16
13
CLK
DVCC DGND
N/C VEE
AGND
D12 N/C
N/C
N/C
N/C
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