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UNISONIC TECHNOLOGIES CO., LTD 4066
QUAD BILATERAL SWITCH
DESCRIPTION
The UTC 4066 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
SOP-14
CMOS IC
FEATURES
* Wide supply voltage range: 3V ~ 15V. * High noise immunity : 0.45VDD (typ.) * Wide range of digital and 7.5VPEAK analog switching * "ON" resistance for 15V operation : 80 * Matched "ON" resistance : RON=5 (typ.) over 15V signal input * "ON" resistance flat over peak-to-peak signal range * High "ON" / "OFF" : 65 dB (typ.) output voltage ratio @ fIS=10kHz, RL=10k * High degree linearity: 0.1% distortion (typ.). @ fIS=1kHz, VIS=5Vp-p. * VDD-VSS=10V, RL=10k * Extremely low "OFF" : 0.1nA (typ.) * switch leakage @VDD-VSS=10V, Ta=25 * Extremely high control input impedance : 1012 (typ.) * Low crosstalk : -50dB (typ.) * between switches @ fIS=0.9MHz, RL=1k * Frequency response, switch "ON" : 40MHz (typ.)
DIP-14
TSSOP-14
*Pb-free plating product number: 4066L
ORDERING INFORMATION
Ordering Number Normal Lead Free Plating 4066-D14-T 4066L-D14-T 4066-S14-R 4066L-S14-R 4066-S14-T 4066L-S14-T 4066-P14-R 4066L-P14-R 4066-P14-T 4066L-P14-T Package DIP-14 SOP-14 SOP-14 TSSOP-14 TSSOP-14 Packing Tube Tape Reel Tube Tape Reel Tube
4066L-D14-T (1)Packing Type (2)Package Type (3)Lead Plating (1) R: Tape Reel, T: Tube (2) D14: DIP-14, S14: SOP-14, P14: TSSOP-14 (3) L: Lead Free Plating Blank: Pb/Sn ,
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PIN CONFIGURATION
1 2 3 SW D 14 VDD 13 CONTROL A 12 CONTROL D 11 IN/ OUT 10 OUT/ IN 9 SW C 8 OUT / IN IN / OUT
CMOS IC
IN / OUT OUT/ IN OUT/ IN
SW A
IN / OUT 4 CONTROL B 5 CONTROL C 6 Vss 7 SW B
SCHEMATIC DIAGRAM
IN/ OUT
OUT/ IN CONTROL Vss
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ABSOLUTE MAXIMUM RATINGS (VSS=0V, unless otherwise specified)
PARAMETER Supply Voltage Input Voltage SYMBOL VDD VIN
CMOS IC
RATINGS UNIT -0.5 ~ +18 V -0.5 ~ Vcc+0.5 V 700 DIP-14 mW Power Dissipation PD SOP-14 500 mW TSSOP-14 500 mW Junction Temperature TJ +125 C Storage Temperature TSTG -40 ~ +150 C Note Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS (VSS=0V, unless otherwise specified)
PARAMETER Supply Voltage Input Voltage Operating Temperature Range SYMBOL VDD VIN TOPR RATINGS 3 ~ 15 0 ~ VDD -40 ~ +85 UNIT V V C
DC ELECTRICAL CHARACTERISTICS (VSS=0V, unless otherwise specified)
PARAMETER Quiescent Current Device SYMBOL IDD CONDITIONS -40C MIN MAX 1.0 2.0 4.0 MIN +25C TYP 0.01 0.01 0.01 MAX 1.0 2.0 4.0 +85C UNITS MIN MAX A 7.5 A 15 A 30
VDD=5V VDD=10V VDD=15V SIGNAL INPUTS AND OUTPUTS Input or Output Leakage IIS Vc=0 Switch "OFF" RL=10k ~ (VDD-VSS/2) Vc=VDD, VSS ~ VDD VDD=5V "ON" Resistance RON VDD=10V VDD=15V RL=10k ~ (VDD-VSS/2) "ON" Resistance Vc=VDD, VIS=VSS ~VDD Between Any 2 of 4 RON VDD=10V Switches VDD=15V CONTROL INPUTS VIS= VSS and VDD Vos=VDD and VSS IIS= 10A Low Level Input VILC Voltage VDD=5V VDD=10V VDD=15V VDD=5V HIGH Level Input VIHC VDD=10V (Note 4) Voltage VDD=15V VDD-VSS=15V VDD VIS VSS Input Current IIN VDD Vc VSS
50
0.1
50
200
nA
850 330 210
270 120 80
1050 400 240
1200 520 300

10 5

1.5 3.0 4.0 3.5 7.0 11.0 0.3 3.5 7.0 11.0
2.25 4.5 6.75 2.75 5.5 8.25 10-5
1.5 3.0 4.0 3.5 7.0 11.0 0.3
1.5 3.0 4.0
V V V V V V A
1.0
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(Ta=25 , tr=tf=20 ns and Vss=0V unless otherwise) PARAMETER SYMBOL Propagation Delay Time Signal Input to Signal Output Propagation Delay Time Control Input to Signal Output High Impedance to Logical Level Propagation Delay Time Control Input to Signal Output Logical Level to High Impedance Sine Wave Distortion Frequency Response -Switch "ON" (Frequency at-3dB) TPHL, TPLH CONDITIONS VDD=5V MIN TYP 25 15 10
CMOS IC
AC ELECTRICAL CHARACTERISTICS (AC Parameters are guaranteed by DC correlated testing)
MAX UNITS 55 ns 35 25 125 60 50 125 60 50 0.1 40 ns ns ns ns ns ns ns ns % MHz
tPZH, tPLZ
Vc=VDD, CL=50pF, (Figure1) VDD=10V RL=200k VDD=15V RL=1.0k, CL=50pF VDD=5V (Figure 2, Figure3) VDD=10V VDD=15V RL=1.0k, CL=50pF, (Figure 2, Figure3) VDD=5V VDD=10V VDD=15V Vc=VDD=5V, Vss= -5V RL=10k, VIS=5VP-P, f=1kHz, (Figure 4) Vc=VDD=5V, Vss= -5V RL=1k, VIS=5Vp-p 20 Log10 VOS/VOS (1kHz)-dB (Figure 4) VDD=5.0V, Vcc=Vss= -5.0V, RL=1k, VIS=5.0VP-P, 20Log10, VOS/VIS= -50dB, (Figure 4) VDD=VC(A)=5.0V; Vss=Vc (B)=5.0V, RL=1k, VIS(A)=5.0VP-P, 20Log10, VOS(B)/VIS (A)= -50dB (Figure 5) VDD=10V, RL=10k, RIN=1.0k Vcc=10V Square Wave, CL=50pF (Figure 6) RL=1.0k, CL=50pF, (Figure 7) Vos (f) =1/2Vos (1.0kHz) VDD=5.0V VDD=10V VDD=15V VDD=10V VC=0V
tPHZ, tPLZ
Feedthrough - Switch "OFF" (Frequency at -50 dB) Crosstalk Between Any Two Switches(Frequency at-50dB) Crosstalk; Control Input to Signal Output Maximum Control Input
1.25
0.9
MHz
150
mVp-p
Signal Input Capacitance Signal Output Capacitance Feedthrough Capacitance Control lnput Capacitance
CIS COS CIOS CIN
6.0 8.0 8.5 8.0 8.0 0.5 5.0 7.5
MHz MHz MHz pF pF pF pF
Note 1: These devices should not be connected to circuits with the power "ON" Note 2: In all cases, these is approximately 5pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is specified. Note 3: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. Vc is the voltage at the control input. Note 4: Conditions for VIHC: (a) VIS=VDD, Ios=standard B series IOH. (b) VIS=0V, IOL=standard B series IOL
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SPECIAL CONSIDERATIONS
CMOS IC
In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability should exceed VDD/RL (RL=effective external load of the UTC 4066 bilateral switches).This provision avoids any permanent current flow or clamp action of the VDD supply when power is applied or removed from UTC 4066. In certain applications, the external load-resistor current may include both VDD and Signal-line components. To avoid drawing VDD current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the bidirectional swith must not exceed 0.6V at Ta 25 , or 0.4V at Ta >25 (calculated from RON values shown). NO VDD current will flow through RL if the switch current flows into terminals2, 3, 9 or 10.
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
VC=VDD VDD CONTROL VDD 1 OF 4 OU OUT/IN /IN IN/OUT T SWITCHES Vss VDD VIS CL 50 pF VOS RL 200 K 0V VDD VOS 0V 50% tf 90% 50% 10% tf
VIS
t PLN
t PNL
FIGURE 1. t PHL, t PLH Propagation Delay Time Signal Input to Signal Output
VC
VDD VDD CONTROL 1 OF 4 IN/OUT OUT/IN SWITCHES Vss CL 50pF RL 1K VDD
t PZH VDD 50% VOS 0V VOH 0V tPZH 10% 0V VOH 0V
t PHZ 50% tPHZ 90% VDD
VIS =VDD
FIGURE 2. t PZH, t PHZ Propagation Delay Time Control to Signal Output
VC
VDD VDD CONTROL 1OF 4 OUT/IN IN/OUT SWITCHES Vss
VDD RL 1K VOS CL 50pF
t PZL VDD 50% 0V VDD VOL tPZL 90% 0V VDD VOL 10% VDD
t PLZ 50% t PLZ
VIS=0V
FIGURE 3 . t PZL, t PLZ Propagation Delay Time Control to Signal Output
VC
5V CONTROL VDD 1OF 4 IN/OUT OUT/IN SWITCHES Vss 2.5V VOS RL VIS = 0V -2.5V 1 /f
VIS
-5V Vc=VDD for distortion and frequency response tests Vc= Vss for feedthrough test FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
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AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS(Cont.)
VC(1 DD )=V 5V VDD CONTROL 1 OF 4 IN/OUT OUT/IN SWITCHES Vss -5V V (2)=Vss C VIS (2)=0V 5V CONTROL VDD 1 OF 4 IN/OUT OUT/IN SWITCHES Vss -5V FIGURE 5. Crosstalk Between Any Two Switches
CMOS IC
VIS (1)
VOS (1) RL 1k 2.5V VIS 0V -2.5V 1 /f
VOS (2) RL 1k
Vc
10V VDD CONTROL VDD 1OF 4 IN/OUT OUT/IN SWITCHES Vss VC RL 10k VOS CL 50pF 0V
tf=20ns 90% 10%
tf=20ns
VIS R IN 1k
VOS
CROSSTALK
FIGURE 6. Crosstalk : Control Input to Signal Output
Vc
VDD CONTROL VDD 1OF 4 OUT/IN IN/OUT SWITCHES Vss VDD VC VOS CL 50pF RL 1k VOS 0V 10%
tf 50% 90% 50%
tf
VIS =VDD
10% 1/f VOS 1kHz
FIGURE 7 . Maximum Control Input Frequency
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TYPICAL PERFORMANCE CHARACTERISTICS
ON
Resistance (RON) ( )
CMOS IC
Resistance vs Signal Voltage for Ta =25
Resistance(RON) ( ) ON
400 350 300 250 200 150 VDD -VSS=10V 100 50 0 -8 -6 -4 -2 0 VDD- VSS=15V 2 4 6 8 Signal Voltage (VIS ) (V) VDD-VSS =5V
ON Resistance as a Function of emperature for VDD-VSS=15V 400 350 300 250 200 150 100 50 0 Ta =-20 -8 -6 -4 -2 0 2 4 6 8 Signal Voltage (VIS) (V) Ta=+125 Ta=+25
ON
Channel
Resistance (RON) ( )
350 300 250 200 150 100 50 0 -8 Ta =+125 Ta =+25
Resistance (RON) ( )
"ON" Resistance as a Function of Temperaturefor VDD-VSS=10V 400
Channel
"ON" Resistance as a Function of Temperature for VDD-VSS =15V 400 350 300 250 200 150 100 50 0 -8 -6 -4 -2 2 4 6 0 Signal Voltage (VIS) (V) 8 Ta =-20 Ta =+25 Ta=+125
ON
Channel
Ta=-20 -6 -4 -2 2 4 6 0 Signal Voltage (VIS) (V) 8
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
UNISONIC TECHNOLOGIES CO., LTD
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Channel
ON
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