View 7429_1135031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA7429L
3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROL
s s s
3 STEREO INPUTS AUXILIARY MONO INPUT INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE MIDDLE AND BASS CONTROL FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION SUBWOOFER OUTPUT (L+R) CONTROLLED IN 1dB STEP INPUTS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
an additional subwoofer control. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
SDIP42 ORDERING NUMBER: TDA7429L
s s
s
s
DESCRIPTION The TDA7429L is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems, providing also
Figure 1. Test Circuit
2.2F 2.2F 0.47F BASSO_R L+R OUTPUT N.C. N.C. N.C. N.C. N.C. LP 100nF 9 1 2 3 4 7 5 34 33 42 35 14 VAR_R 13 BASSO_L 12 VAR_L 11 MONO INPUT 10 0.47F R_IN3 40 0.47F R_IN2 39 38 36 R_IN1 0.47F
MONITOR_L L_IN1 0.47F
L_IN2 L_IN3 VS 10F
0.47F
0.47F
LP1
6
100nF 5.6nF
100nF
TREBLE_R TREBLE_L
23 24 41 8 37 15 19 20 16 HP2 BASS_LO CREF
22F 220nF 100nF
100nF MONITOR_R 22nF 18nF MIDDLE_LI 22nF MIDDLE_RO MIDDLE_RI 21 22 32 31 30 29 R_OUT 28 27 26 SDA 25 AGND MIDDLE_LO
100nF BASS_LI 100nF
2.7K
5.6K
17
BASS_RO
18nF 2.7K
100nF 18 BASS_RI 5.6K
AUXOUT_L AUXOUT_R L_OUT
DIG_GND SCL
D99AU1029
March 2000
1/16
TDA7429L
Figure 2. Pin Connection
N.C. N.C. N.C. N.C. LP LP1 N.C. HP2 L+R OUTPUT MONO INPUT VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D99AU1028
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI
Table 1. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2db step) Middle Control (2db step) Bass Control (2dB step) Balance Control 1dB step (LCH, RCH) Mute Attenuation -14 -14 -14 -79 100 Parameter Min. 7 2 0.01 106 90 +14 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB
2/16
5.6nF 100nF
MIDDLE_LI MIDDLE_LO
2.7K 18nF 100nF 2.2F
5.6K 22nF 100nF
Figure 3. Block Diagram.
MONITOR_L BASS_LI BASSO_L 12 30K 11 VAR_L 16 15 RB FIX 6 RM 24 20 19
LP1 TREBLE_L BASS_LO
0.47F
36
35
31.5dB control
L_IN1
50K OFF SURR + LPF 1 REAR MUTE FIX TREBLE BASS OFF MIDDLE 3BAND MUTE VAR + REC ATT 79dB CONTROL 79dB CONTROL SPKR ATT
0.47F
32
AUXOUT_L
34
L_IN2
50K
0.47F
33
30
L_IN3
L_OUT
50K
27 26 I 2C BUS DECODER + LATCHES 28 SCL SDA DIG GND
0.47F TREBLE FIX MIDDLE BASS LPF 2 L+R CONTROL
38
R_IN1
FIX VAR + 3BAND MUTE REC ATT 79dB CONTROL SPKR ATT 29 R_OUT
50K OFF
0.47F
39
R_IN2 REAR SURR SUPPLY 50K RM 23 TREBLE_R 22 21 18 8 9 L+R OUTPUT REARIN MIDDLE_RI 10 HP2 22F 100nF 0.47F 5.6nF LP 5 Vref RB 17
50K
0.47F
40
R_IN3
31 30K MUTE 79dB CONTROL BASSO_R 14 13 VAR_R
AUXOUT_R
50K
31.5dB control 25 41
37
42
MONITOR_R AGND CREF
VS
D99AU1030
BASS_RI
MIDDLE_RO
18nF 2.7K
22nF
100nF 5.6K
100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS_RO
2.2F
TDA7429L
3/16
TDA7429L
Table 2. Thermal Data
Symbol R th j-pins Thermal Resistance Junction-pins Description Max. Value 85 Unit C/W
Table 3. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 -10 to 85 -55 to +150 Unit V C C
Table 4. Electrical Characteristics (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K,Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
Symbol SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 10 60 9 18 80 10.2 26 V mA dB Parameter Test Conditio n Min. Typ. Max. Unit
INPUT STAGE RIN VCL CRANGE AVMIN AVMAX A STEP Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution -1 31 THD = 0.3% 35 2 50 2.5 31.5 0 31.5 0.5 1 32 1 65 K Vrms dB dB dB dB
BASS CONTROL Gb B STEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut 11.5 1 32 14.0 2 44 16.0 3 56 dB dB K
MIDDLE CONTROL Gm M STEP RM Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut 11.5 1 17.5 14.0 2 25 16.0 3 32.5 dB dB K
TREBLE CONTROL Gt TSTEP Control Range Step Resolution Max. Boost/cut 13.0 1 14.0 2 15.0 3 dB dB
4/16
TDA7429L
Table 4. Electrical Characteristics (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K,Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
Symbol CONTROL L+R CRANGE S STEP Control Range Step Resolution - 11 0.5 1 +4 1.5 dB dB Parameter Test Conditio n Min. Typ. Max. Unit
SPEAKER & AUX ATTENUATORS CRANGE S STEP EA Control Range Step Resolution Attenuation set error Av = 0 to -20dB Av = -20 to -79dB VDC AMUTE RVEA DC Steps Output Mute Condition Input Impedance adjacent att. steps -0.5 -1.5 -3 -3 +70 21 79 1 0 0 0 100 30 39 1.5 1.5 2 3 dB dB dB dB mV dB K
AUDIO OUTPUTS NO(OFF) d SC VOCL ROUT VOUT Output Noise (OFF) Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Output Mute, Flat BW = 20Hz to 20KHz Av = 0 ; Vin = 1Vrms 70 2 20 4 5 0.01 90 2.5 40 3.8 70 0.1 Vrms Vrms % dB Vrms V
MONITOR OUTPUTS d SC VOCL ROUT VOUT Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Av = 0 ; Vin = 1Vrms 70 2 20 0.01 90 2.5 50 4.5 70 0.1 % dB Vrms V
BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V mA V
5/16
TDA7429L
1.0 I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
1.1 Data Validity
As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
1.2 Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
1.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
1.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
1.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
Figure 4. Data validity on the 2C bus I
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
2 Figure 5. Timing Diagram of I C bus
SCL I2 CBUS SDA
D99AU1032
START
STOP
6/16
TDA7429L
2 Figure 6. Acknowledge on the I C bus
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
2.0 SOFTWARE SPECIFICATION 2.1 Interface Protocol
The interface protocol comprises:
s s s s s
A start condition (S) A chip address byte, containing the TDA7429L address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU226A
ACK = Acknowledge 3.0 EXAMPLES
S = Start
P = Stop
A = Address
B = Auto Increment
3.1 No Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D95AU306
3.2 Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU307
7/16
TDA7429L
Table 5. Function Selection
The first byte (subaddress)
MSB D7 B1 B B B B B B B B
<1> <2>
LSB SUBADDRESS D6 X2 X X X X X X X X D5 X X X X X X X X X D4 X X X X X X X X X D3 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 0 0 D1 0 0 1 1 0 0 1 0 0 D0 0 1 0 1 0 1 1 0 1 INPUT ATTENUATION CONTROL OUT L+R & SUBWOOFER NOT USED BASS & NATURAL BASE MIDDLE & TREBLE SPEAKER ATTENUATION "L" AUX ATTENUATION "L" AUX ATTENUATION"R" INPUT MULTIPLEXER, & AUX OUT
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1
Table 6. Input Attenuation Selection
MSB D7 X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -4 -8 -12 -16 -20 -24 -28
INPUT ATTENUATION = 0 ~ -31.5dB D7 X D6 0 D5 D4 D3 D2 D1 D0 L+R OUTPUT SWITCH (L+R) OUTPUT PIN ACTIVE
8/16
TDA7429L
Table 7. Out & (L+R) & Subwoofer Selection
MSB D7 X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SUBWOOFER CONTROL SUBWOOFER ON NOT ALLOWED SUBWOOFER OFF NOT ALLOWED OUT VAR FIX L+R CONTROL +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 --9 -10 -11
Table 8. Bass Selection
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
9/16
TDA7429L
Table 9. Speaker/Aux Att. R & L Selection
MSB D7 X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER/AUX ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE X X 1 1 0 1 1 X X X
Notes: 1. X = INDIFFERENT 0.1 2. SPAEAKER/AU X ATTENUATI ON = 0dB to 79dB
10/16
TDA7429L
Table 10. Middle & Treble Selection
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 MIDDLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 TREBLE 2 dB STEPS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
11/16
TDA7429L
Table 11. Input/recout L & R Selection
MSB D7 X X X D6 D5 D4 D3 D2 1 0 0 D1 1 0 1 LSB D0 0 0 0 INPUT MULTIPLEXER IN1 IN2 IN3 AUX OUT "L" X X X X 0 0 1 1 0 1 0 1 0 0 0 0 VAR 1 (3BAND) NOT ALLOWED VAR 3 (REAR) FIX AUX OUT "R" X X X X 0 0 1 1 0 1 0 1 0 0 0 0 VAR 1 (3BAND) NOT ALLOWED VAR 3 (REAR) FIX
Table 12. Power on reset
BASS & MIDDLE TREBLE SURROUND & OUT CONTROL + (L+R) CONTROL SPEAKER/AUX ATTENUATION L & R INPUT ATTENUATION + (L+R) SWITCH NATURAL BASE INPUT 2dB 0dB OFF + FIX + MAX. ATTENUATION MUTE MAX. ATTENUATION + ON OFF IN1
12/16
TDA7429L
Figure 7. Pin: TREBLE-L, TREBLE-R
VS 20A
Figure 10. Pin: CREF
VS 20K 42K 20A
25K
20K
GND
D95AU336
GND
D95AU309
Figure 8. Pin: VOUT REF
VS
Figure 11. Pin: VAR-L, VAR-R
VS
20A
20A
SW
GND
30K
D95AU233A
10K GND
GND Vref
D95AU227
Figure 9. Pin: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4
Figure 12. Pin: LP1, LP
VS 20A
VS 20A
50K GND
GND
10K
D94AU200
VREF
HP1
D94AU211
13/16
TDA7429L
Figure 13. Pin: SCL, SDA Figure 16. Pin: BASS-LI, BASS-RI, MIDDLE-LI, MIDDLE-R
VS
20A
20A
GND
GND
D94AU205
BASS-LO
45K : Bass or 25K : MIDDLE
D95AU231A
BASS-RO,MIDDLE-LO,MIDDLE-RO
Figure 14. Pin: MONO INPUT
Figure 17. Pin: BASS-LO, BASS-RO, MIDDLELO,MIDDLE-RO
VS
VS
20A
20A
SW
(*) GND
50K GND Vref
D95AU229
BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI (*) 45K : Bass 25K : MIDDLE
D95AU232
Figure 15. Pin: L-OUT, R-OUT, MONITOR-L,
MONITOR-R, LTR OUTPUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R
VS 20A
GND
D95AU230
14/16
TDA7429L
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70
mm TYP. MAX. 5.08 0.020 3.81 0.46 1.02 0.25 36.83 4.57 0.56 1.14 0.38 37.08 16.00 13.72 1.778 15.24 18.54 1.52 3.30 3.56 0.10 14.48 0.120 MIN.
inch TYP. MAX. 0.20
OUTLINE AND MECHANICAL DATA
0.150
0.180
0.0149 0.0181 0.0220 0.035 0.040 0.045
0.0090 0.0098 0.0150 1.440 0.60 0.50 0.540 0.070 0.60 0.730 0.060 0.130 0.140 1.450 1.460 0.629 0.570
SDIP42 (0.600")
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
15/16
TDA7429L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com
16/16

▲Up To Search▲

Price & Availability of 7429

	To Download 7429 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .