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CS8183 Dual Micropower 200 mA Low Dropout Tracking Regulator/Line Driver
The CS8183 is a dual low dropout tracking regulator designed to provide adjustable buffered output voltages that closely track (10 mV) the reference inputs. The outputs deliver up to 200 mA while being able to be configured higher, lower or equal to the reference voltages. The outputs have been designed to operate over a wide range (2.8 V to 45 V) while still maintaining excellent DC characteristics. The CS8183 is protected from reverse battery, short circuit and thermal runaway conditions. The device also can withstand 45 V load dump transients and -50 V reverse polarity input voltage transients. This makes it suitable for use in automotive environments. The VREF/ENABLE leads serve two purposes. They are used to provide the input voltage as a reference for the output and they also can be pulled low to place the device in sleep mode where it nominally draws less than 30 A from the supply. The two trackers can be combined in parallel doubling the capability to 400 mA for a single application. Features Two Regulated Outputs 200 mA, 10 mV Track Worst Case Low Dropout (0.35 V typ. @ 200 mA) Low Quiescent Current Independent Thermal Shutdown Short Circuit Protection Wide Operating Range Internally Fused Leads in the SO-20L Package
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20 1 SO-20L DWF SUFFIX CASE 751D
PIN CONNECTIONS AND MARKING DIAGRAM
1 VIN1 VOUT1 NC NC GND GND NC NC VADJ1 VREF/ENABLE1 A WL, L YY, Y WW, W CS8183 AWLYYWW 20 VOUT2 VIN2 NC NC GND GND NC NC VREF/ENABLE2 VADJ2
* * * * * * *
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS8183YDWF20 CS8183YDWFR20 Package SO-20L SO-20L Shipping 37 Units/Rail 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2004
1
March, 2004 - Rev. 15
Publication Order Number: CS8183/D
CS8183
VIN1
VOUT1
Current Limit & VSAT Sense Adj1
-
ENABLE
+
VREF/ENABLE1
+ Independent Thermal Shutdown GND - 2.0 V VOUT2
VIN2
Current Limit & VSAT Sense Adj2
-
ENABLE
+
VREF/ENABLE2
+ Independent Thermal Shutdown - 2.0 V
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Package Lead Number SO-20L 1 2 3, 4, 7, 8, 13, 14, 17, 18 5, 6, 15, 16 9 10 11 12 19 20 Lead Symbol VIN1 VOUT1 NC GND VADJ1 VREF/ENABLE1 VADJ2 VREF/ENABLE2 VIN2 VOUT2 Input voltage for VOUT1. Regulated output voltage 1. No connection. Ground (4 leads fused) Adjust lead for VOUT1. Reference voltage and ENABLE input for VOUT1. Adjust lead for VOUT2. Reference voltage and ENABLE input for VOUT2. Input voltage for VOUT2. Regulated output voltage 2. Function
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CS8183
MAXIMUM RATINGS*
Rating Storage Temperature Supply Voltage Range (continuous) Supply Voltage Range (normal, continuous) Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V) Voltage Range (Adj, VREF/ENABLE, VOUT) Maximum Junction Temperature Package Thermal Resistance: Junction-to-Case, RJC Junction-to-Ambient, RJA ESD Capability (Human Body Model) (Machine Model) Lead Temperature Soldering: 1. 60 second maximum above 183C. 2. -5C/+0C allowable conditions. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value -65 to 150 15 to 45 3.4 to 45 45 -10 to 45 150 18 73 2.0 200 240 peak (Note 2) Unit C V V V V C C/W C/W kV V C
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; -40C TJ +125C; COUT 10 F; 0.1 < COUT - ESR < 1.0 @ 10 kHz; unless otherwise stated.)
Parameter Regular Output 1, 2 VREF - VOUT VOUT Tracking Error Dropout Voltage (VIN - VOUT) Line Regulation Load Regulation Adj Lead Current Current Limit Quiescent Current (IIN - IOUT) 4.5 V VIN 26 V, 100 A IOUT 200 mA, Note 3 IOUT = 100 A IOUT = 200 mA 4.5 V VIN 26 V, Note 3 100 A IOUT 200 mA, Note 3 Loop in Regulation VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 3 VIN = 12 V, IOUT = 200 mA VIN = 12 V, IOUT = 100 A VIN = 12 V, VREF/ENABLE = 0 V VOUT = 5.0 V, VIN = 0 V f = 120 Hz, IOUT = 200 mA, 4.5 V VIN 26 V - -10 - - - - - 225 - - - - 60 150 - 100 350 - - 0.2 - 15 75 30 0.2 - 180 10 150 600 10 10 1.0 700 25 150 55 1.5 - 210 mV mV mV mV mV A mA mA A A mA dB C Test Conditions Min Typ Max Unit
Reverse Current Ripple Rejection Thermal Shutdown VREF/ENABLE 1, 2 Enable Voltage Input Bias Current 3. VOUT connected to Adj lead.
- VREF/ENABLE 1, 2 > 2.0 V
0.80 -
2.00 0.2
2.75 1.0
V A
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CS8183
TYPICAL CHARACTERISTICS
18 QUIESCENT CURRENT (mA) 16 14 12 10 8 6 4 2 0 0 20 40 60 80 100 120 140 160 180 200 OUTPUT CURRENT (mA)
Figure 2. Quiescent Current vs. Output Current
1 QUIESCENT CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 I (Vout) = 1 mA 10 15 20 25 30 35 40 45 VIN, INPUT VOLTAGE (V) I (Vout) = 20 mA QUIESCENT CURRENT (A)
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 VIN, INPUT VOLTAGE (V) Vref / ENABLE = 0 V
Figure 3. Quiescent Current vs. Input Voltage (Operating Mode)
Figure 4. Quiescent Current vs. Input Voltage (Sleep Mode)
20 18 CURRENT INTO Vout (mA) 16 14 12 10 8 6 4 2 0 0 5 Vin = 0 V 10 15 20 25 FORCED Vout VOLTAGE (V) Vin = 6 V* Vref = 5 V** CURRENT INTO Vout (mA) * Graph is duplicate for Vin > 1.6V. **Dip (@5V) shifts with Vref voltage.
140 120 100 80 60 40 20 0 0 5 10 15 20 25 30 35 40 FORCED Vout VOLTAGE (V) Vin = 6 V* Vref = 5 V** Vin = 0 V * Graph is duplicate for Vin > 1.6V. **Dip (@5V) shifts with Vref voltage.
Figure 5. Vout Reverse Current
Figure 6. Vout Reverse Current
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CS8183
CIRCUIT DESCRIPTION
ENABLE Function
By pulling the VREF/ENABLE 1, 2 lead below 2.0 V typically, (see Figure 10 or Figure 11), the IC is disabled and enters a sleep state where the device draws less than 30 A from supply. When the VREF/ENABLE lead is greater than 2.75 V, VOUT tracks the VREF/ENABLE lead normally.
Output Voltage
The outputs are capable of supplying 200 mA to the load while configured as a similiar (Figure 7), lower (Figure 9), or higher (Figure 8) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the VREF lead as the non-inverting. The device can also be configured as a high-side driver as displayed in Figure 12.
Figures 7 through 12 only display one channel of the device for simplicity. The configurations shown apply for both channels.
VOUT, 200 mA Loads VOUT C2** GND 10 mF GND Adj VOUT, 200 mA Loads VOUT C2** GND 10 mF RF GND Adj RA
VIN CS8183 GND GND C3*** 10 nF C1* 1.0 mF
B+
VIN CS8183 GND GND C3*** 10 nF C1* 1.0 mF
B+
VREF/ ENABLE
5.0 V
VREF/ ENABLE
VREF
VOUT + VREF
R VOUT + VREF(1 ) E) RA
Figure 7. Tracking Regulator at the Same Voltage
VOUT, 200 mA Loads VOUT C2** GND 10 mF GND Adj
Figure 8. Tracking Regulator at Higher Voltages
VOUT, 200 mA
VIN CS8183 GND GND R1 C3*** 10 nF C1* 1.0 mF
B+
VOUT GND GND CS8183
VIN GND GND R C3*** 10 nF C1* 1.0 mF
B+
C2** 10 mF
VREF/ ENABLE
VREF R2 from MCU
Adj
VREF/ ENABLE
VREF
VOUT + VREF( R2 ) R1 ) R2
Figure 9. Tracking Regulator at Lower Voltages
VIN 100 nF 5.0 V To Load 10 mF (e.g. sensor) VOUT GND GND Adj CS8183 VIN GND GND I/O C3*** 10 nF C1* 1.0 mF mC VREF (5.0 V)
Figure 10. Tracking Regulator with ENABLE Circuit
6.0 V-40 V
NCV8501
200 mA
VOUT CS8183 GND GND Adj
VIN GND GND C3*** 10 nF
B+
VREF/ ENABLE
MCU
VREF/ ENABLE
VOUT + B ) * VSAT
Figure 11. Alternative ENABLE Circuit
* C1 is required if the regulator is far from the power source filter. ** C2 is required for stability. *** C3 is recommended for EMC susceptibility
Figure 12. High-Side Driver
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CS8183
VOUT 400 mA C2 20 F
400 mA Output Capability
B+ C1 2.0 F VOUT2 VIN2 NC NC GND GND NC NC VREF/ ENABLE2 VREF/ VADJ2 ENABLE1 VIN1 VOUT1 NC NC GND GND NC NC VADJ1
Normally regulator outputs cannot be combined to increase capability. This can cause damage to an IC because of mismatches in the output drivers. The tight tolerances in tracking of the CS8183 allow their outputs to be combined for increased performance. Figure 13 shows the circuit connections needed to perform this function.
VREF
Figure 13. 400 mA Loading
APPLICATION NOTES
Switched Application
The CS8183 has been designed for use in systems where the reference voltage on the VREF/ENABLE pin is continuously on. Typically, the current into the VREF/ENABLE pin will be less than 1.0 A when the voltage on the VIN pin (usually the ignition line) has been switched out (VIN can be at high impedance or at ground.) Reference Figure 14.
Ignition Switch VOUT CS8183 C2 10 F GND GND Adj VIN GND GND < 1.0 A C1 1.0 F VBAT
VOUT
Worst-case is determined at the minimum ambient temperature and maximum load expected. The output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. The capacitors must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to -40C, a capacitor rated at that temperature must be used. More information on capacitor selection for SMART REGULATOR(R)s is available in the SMART REGULATOR application note, "Compensation for Linear Regulators."
Calculating Power Dissipation in a Dual Output Linear Regulator
VREF/ ENABLE
VREF 5.0 V
The maximum power dissipation for a dual output regulator (Figure 15) is:
PD(max) + {VIN(max) * VOUT1(min)} IOUT1(max) ) {VIN(max) * VOUT2(min)}IOUT2(max2) ) VIN(max)IQ (1)
Figure 14. External Capacitors
Output capacitors for the CS8183 are required for stability. Without them, the regulator outputs will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability.
where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2,
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CS8183
IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated:
RQJA + 150C * TA PD
(2)
Heatsinks
A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA:
RQJA + RQJC ) RQCS ) RQSA
(3)
The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required.
IIN VIN
where: RJC = the junction-to-case thermal resistance, RCS = the case-to-heatsink thermal resistance, and RSA = the heatsink-to-ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
SMART REGULATOR
IOUT VOUT
Control Features
IQ
Figure 15. Dual Output Regulator with Key Performance Parameters Labeled
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CS8183
PACKAGE DIMENSIONS
SO-20L DWF SUFFIX CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CS8183/D

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