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74AC299 * 74ACT299 8-Input Universal Shift/Storage Register
July 1988 Revised March 2005
74AC299 * 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
General Description
The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
Features
s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes: shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s ACT299 has TTL-compatible inputs
Ordering Code:
Order Number 74AC299SC 74AC299SCX_NL (Note 1) 74AC299SJ 74AC299MTC 74AC299PC 74ACT299SC 74ACT299MTC 74ACT299PC Package Number M20B M20B M20D MTC20 N20A M20B MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0-I/O7 Q0, Q7 Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset 3-STATE Output Enable Inputs Parallel Data Inputs or 3-STATE Parallel Outputs Serial Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009893
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74AC299 * 74ACT299
Logic Symbols
Truth Table
Inputs MR S1 L H H H H X H L H L S0 X H H L L CP Response

X X
Asynchronous Reset; Q0-Q7 Parallel Load; I/On o Qn
LOW
Shift Right; DS0 o Q0, Q0 o Q1, etc. Shift Left, DS7 o Q7, Q7 o Q6, etc. Hold
IEEE/IEC
H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
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74AC299 * 74ACT299
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC299 * 74ACT299
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) (Unless Otherwise Specified) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.0V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO
20 mA 20 mA VO DC Output Voltage (VO) 0.5V to VCC 0.5V r 50 mA DC Output Source or Sink Current (IO)
DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) (PDIP) 140qC
0.5V VCC 0.5V
40qC to 85qC
r 50 mA 65qC to 150qC
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 5.5 4.0 5.5 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 25qC TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1
V
IOH IOH IOH
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND 1.65V Max 3.85V Min VCC or GND
V
IOUT VIN
0.44 0.44 0.44 V
IOH IOH IOH VI
r 0.1
r 1.0
86
PA
mA mA
VOLD VOHD VIN
75
40.0
PA
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74AC299 * 74ACT299
DC Electrical Characteristics for AC
Symbol IOZT Parameter Maximum I/O Leakage Current VCC (V) 5.5 TA Typ
(Continued)
25qC TA
40qC to 85qC r 3.0
Units
Conditions VI (OE) VI VO VIL, VIH
Guaranteed Limits
r 0.3
PA
VCC, GND VCC, GND
Note 3: All outputs loaded; threshold on input associated with output under test. Note 4: Maximum test duration 20 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level VCC (V) 4.5 5.5 3.0 4.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC IOZT Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 0.0001 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 25qC TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V IOUT VIN
50 PA
VIL or VIH
V
IOH IOH
24 mA 24 mA (Note 6)
50 PA VIL or VIH
V
IOUT VIN
V
IOL 24 mA IOL 24 mA (Note 6) VI VI VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC or GND VIL, VIH VCC, GND VCC, GND
r 0.1
r 1.0
1.5 75
PA
mA mA mA
VOLD VOHD VIN VI VO VI (OE)
75
40.0
PA PA
r0.3
r3.0
Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
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74AC299 * 74ACT299
AC Electrical Characteristics for AC
VCC Symbol fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Input Frequency Propagation Delay CP to Q0 or Q7 (Shift Left or Right) Propagation Delay CP to Q0 or Q7 (Shift Left or Right) Propagation Delay CP to I/On Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time OE to I/On Output Enable Time OE to I/On Output Disable Time OE to I/On Output Disable Time OE to I/On
Note 8: Voltage Range 3.3 is 3.3V r 0.3V. Voltage Range 5.0 is 5.0V r 0.5V.
TA CL Min 90 130 8.5 5.5 8.5 5.5 9.0 6.0 10.0 6.5 9.0 5.5 9.0 5.5 7.0 4.5 7.0 5.0 6.5 3.5 5.5 3.5
25qC
50 pF Typ 124 173 14.0 9.5 14.5 10.0 14.5 10.0 16.0 11.0 15.5 10.5 15.0 10.0 12.0 8.5 12.5 8.0 13.0 9.5 11.5 8.0 20.5 14.0 21.5 14.5 20.5 14.5 23.0 16.0 22.5 15.5 21.5 15.0 18.0 12.5 18.0 12.5 18.5 14.0 17.0 12.5 Max
TA
40qC to 85qC
CL 50 pF Max MHz 22.0 15.0 23.0 16.0 22.5 16.0 24.5 17.5 25.0 17.0 24.0 16.5 19.5 13.5 20.5 14.0 19.5 15.0 19.0 13.5 ns ns ns ns ns ns ns ns ns ns Units
(V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Min 80 105 7.0 4.5 7.0 5.0 7.5 5.0 8.5 6.0 7.5 5.0 7.5 5.0 6.0 4.0 6.0 4.0 5.5 3.0 4.5 2.0
AC Operating Requirements for AC
VCC Symbol tS tH tS tH tS tH tW Parameter Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On to CP Hold Time, HIGH or LOW I/On to CP Setup Time, HIGH or LOW DS0 or DS7 to CP Hold Time, HIGH or LOW DS0 or DS7 to CP CP Pulse Width, LOW (V) (Note 9) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 tW tREC MR Pulse Width, LOW Recovery Time MR to CP
Note 9: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 3.0 2.0
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 8.0 5.0 0.5 1.0 5.5 3.5 0 1.0 6.5 4.0 0 1.0 4.5 3.5 4.5 3.5 1.5 1.5 8.5 5.5 0.5 1.0 6.0 4.0 0 1.0 7.0 4.5 0.5 1.0 5.0 3.5 5.0 3.5 1.5 1.5 ns ns ns ns ns ns ns
3.0 1.5
2.0 1.0
2.0 1.0
2.5 1.5
2.0 1.0
3.5 2.0 4.0 2.0 0 0.5
3.3 5.0 3.3 5.0
ns ns
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74AC299 * 74ACT299
AC Electrical Characteristics for ACT
VCC Symbol fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Input Frequency Propagation Delay CP to Q0 or Q7 (Shift Left or Right) Propagation Delay CP to Q0 or Q7 (Shift Left or Right) Propagation Delay CP to I/On Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time OE to I/On Output Enable Time OE to I/On Output Disable Time OE to I/On Output Disable Time OE to I/On
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 120 4.0 4.0 4.5 5.0 4.0 4.0 2.5 2.0 2.0 2.5
25qC
50 pF Typ 170 8.5 9.0 8.5 9.5 14.0 13.0 8.0 8.0 8.5 8.0 12.5 13.5 12.5 15.0 15.0 14.5 12.0 12.0 12.5 11.5 Max
TA
40qC to 85qC
CL 50 pF Max MHz 14.0 15.0 13.5 16.5 18.0 17.5 13.0 13.5 13.5 12.5 ns ns ns ns ns ns ns ns ns ns Units
(V) (Note 10) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
Min 110 3.0 3.5 4.5 4.5 4.0 3.5 1.5 1.5 2.0 2.0
AC Operating Requirements for ACT
VCC Symbol Parameter (V) (Note 11) tS tH tS tH tS tH tW Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On to CP Hold Time, HIGH or LOW I/On to CP Setup Time, HIGH or LOW DS0 or DS7 to CP Hold Time, HIGH or LOW DS0 or DS7 to CP CP Pulse Width HIGH or LOW tW tREC MR Pulse Width, LOW Recovery Time, MR to CP 5.0 5.0 2.0 0 3.5 1.5 3.5 1.5 ns ns 5.0 2.0 4.0 4.5 ns 5.0 5.0 1.5 4.5 1.0 5.0 1.0 ns ns 5.0 5.0 1.5 4.0 1.0 4.5 1.0 ns ns 5.0 5.0 Typ 2.0 5.0 1.0 TA CL
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 5.5 1.0 ns ns
2.0
1.0
1.0
Note 11: Voltage Range 5.0 is 5.0V r 0.5V.
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 170 Units pF pF VCC VCC 5.0V 5.5V Conditions
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74AC299 * 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC299 * 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74AC299 * 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74AC299 * 74ACT299 8-Input Universal Shift/Storage Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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