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MCS7840
USB-2.0 to Four Serial Ports
Features * USB-2.0 Device Controller * On-Chip USB-2.0 PHY * On-Chip Voltage Regulators * Four 16c450/16c550 compatible UARTs * Supports SIR IrDA Mode on any/all ports * Supports RS-232, RS-485 and RS-422 Serial Ports * 5, 6, 7 & 8-bit Serial Data support * Hardware and Software Flow Control * Serial Port speeds from 50 bps to 6 Mbps * Custom BAUD Rates supported through external clock and/or by programming the internal PLL * On-Chip 512-Byte FIFOs for upstream and downstream data transfers for each Serial Port * Supports Remote Wakeup and Power Management features * Serial Port Transceiver Shut-Down support * Two-Wire I2C Interface for EEPROM * EEPROM read/write through USB * iSerial feature support with EEPROM * One Bi-directional multi-function GPIO * On-Chip buffers for Serial Port signals to operate without external Transceivers over short cable lengths * Bus-Powered Device Applications * Serial Attached Devices * Modems, Serial Mouse, Generic Serial Devices * Serial-Port Server * Data Acquisition System * POS Terminal & Industrial PC Application Note * AN-7840 Evaluation Board * MCS7840-EVB Package * 64-pin LQFP Package Driver Support * Windows (98SE / ME / 2000 / XP / 2003 Server) * Linux Kernel 2.6.5 and above * MAC 10.2 & above * Windows CE5.0 * Windows Vista
Utility Support * Windows based EEPROM Tool * Mass Production Utility
General Description The MCS7840 is a USB-2.0 to Quad-Serial Port device. It has been developed to connect a wide range of standard serial devices to a USB host. The MCS7840 has a USB Device Controller connected to four (4) individual UARTs. Support for the following serial communication programs is included: HyperTerminal, PComm, Windows direct connection, Windows dial-up connection through modem, Networking over IrDA and Windows direct connection over IrDA, Minicom.
Ordering Information Commercial Grade (0 C to +70 C) MCS7840CV 64-LQFP RoHS
MosChip Semiconductor 3335 Kifer Rd, Santa Clara, CA 95051 Tel (408) 737-7141 Fax (408) 737-7708
MCS7840
USB-2.0 to Four Serial Ports
Block Diagram
SCL
SDA
I C EEPROM Controller
2
Interrupt-In Block
Wake-Up Block
Serial Port x4
DTR RTS TXD
Tx Buffer DP DM XTAL OUT USB-2.0 PHY USB-2.0 Device Controller Bulk In FIFOs RXD Bridge Rx Buffer DCD CTS Bulk Out FIFOs RI DSR
XTAL IN
VSPEC_CMD_ Processor
Clock Recovery
Resets
BAUD Clock Generator x4
Ext_Clock
PLL
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Pin-Out Diagram
50 EXT_CLOCK
62 DCD_3_N
54 DCD_2_N
61 DSR_3_N
53 DSR_2_N
57 DTR_3_N
63 CTS_3_N
55 CTS_2_N
58 RTS_3_N
60 RI_3_N
52 RI_2_N
59 RXD_3
56 TXD_3
49 GNDK
51 Vcc3IO
64 VccK
GNDK USB_XSCI USB_XSCO VccA GNDA USB_RREF USB_DM USB_DP VccA
1 2 3 4 5 6 7 8 9
48 RXD_2 47 RTS_2_N 46 DTR_2_N 45 TXD_2 44 EE_SDA 43 EE_SCL 42 RESET
MCS7840CV
41 GPIO 40 VCC3IO 39 VccK 38 GND18A_PLL 37 Vcc18A_PLL 36 REG02_V18 35 GND5A 34 VCC5A 33 REG06_VCC33
GNDA 10 VccK 11 TEST_MODE 12 TXD_4 13 DTR_4_N 14 RTS_4_N 15 RXD_4 16
RI_4_N 17 DSR_4_N 18 DCD_4_N 19 CTS_4_N 20 TXD_1 21 DTR_1_N 22 RTS_1_N 23 RXD_1 24 RI_1_N 25 VccK 26 GNDK 27 Vcc3IO 28 DSR_1_N 29 DCD_1_N 30 CTS_1_N 31 SHTD_1_N 32
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Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 Name GNDK USB_XSCI USB_XSCO VccA GNDA USB_RREF USB_DM USB_DP VccA GNDA VccK Type Power Input Output Power Power Input I/O I/O Power Power Power Core Ground Crystal Oscillator Input Crystal Oscillator Output Power Pin (A3V3) Analog Ground External Reference Resistor (12.1 K, 1%) Connect resistor to Analog GND. USB D- Signal USB D+ Signal Power Pin (A3V3) Analog Ground Power Pin (1.8V) Test Mode Pin, (active high). Default = Low (0) When TEST_MODE = 1, PLL, Core, and SCAN/BIST/ Memory BIST testing can be performed. Set TEST_MODE = 0 for normal operation. Serial Port 4 Transmit Data out to transceiver or IrDA data out to IR LED Serial Port 4 Data Terminal Ready (in serial protocol), active low. Serial Port 4 Request To Send (in serial protocol), active low. Serial Port 4 Serial Receive Data in from transceiver or IrDA data in from IrDA detector. Serial Port 4 Ring Indicator, active low Serial Port 4 Data Set Ready (in serial protocol), active low Serial Port 4 Data Carrier Detect (in serial protocol), active low Serial Port 4 Clear To Send (in serial protocol), active low Serial Port 1 Transmit Data out to transceiver, or IrDA data out to IR LED Serial Port 1 Data Terminal Ready (in serial protocol), active low. Functional Description
12
TEST_MODE
Input
13 14 15 16 17 18 19 20 21 22
TXD_4 DTR_4_N RTS_4_N RXD_4 RI_4_N DSR_4_N DCD_4_N CTS_4_N TXD_1 DTR_1_N
Output Output Output Input Input Input Input Input Output Output
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Pin 23 24 25 26 27 28 29 30 31 Name RTS_1_N RXD_1 RI_1_N VccK GNDK Vcc3IO DSR_1_N DCD_1_N CTS_1_N Type Output Input Input Power Power Power Input Input Input Functional Description Serial Port 1 Request To Send (in serial protocol), active low. Serial Port 1 Serial Receive Data in from transceiver, or IrDA data in from IrDA detector. Serial Port 1 Ring Indicator, active low. Power Pin (1.8V) Core Ground Power Pin (D3V3) Serial Port 1 Data Set Ready (in serial protocol), active low Serial Port 1 Data Carrier Detect (in serial protocol), active low Serial Port 1 Clear To Send (in serial protocol), active low Shut Down External Serial Transceiver during normal operation, active low by default, can be configured active high by using DCR setting. Power Pin (3.3V OUTPUT) Power Pin (5V INPUT) Ground Pin for 5V Input Power Pin (1.8V OUTPUT) PLL Power (1.8V) PLL Ground Power Pin (1.8V) Power pin D3V3. GPIO_MODE - Bidirectional GPIO bit. The direction (Input or Output) is controlled by the DCR for Serial Port #1. Power-On Reset signal (active high). 2-Wire EEPROM Clock. Default = High (1) 2-Wire EEPROM Data in/out. Default = High (1) Serial Port 2 Transmit Data out to transceiver, or IrDA data out to IR LED Serial Port 2 Data Terminal Ready (in serial protocol), active low.
32 33 34 35 36 37 38 39 40 41
SHTD_1_N REG06_VCC33 Vcc5A GND5A REG02_V18 Vcc18A_PLL GND18A_PLL VccK VCC3IO GPIO
Output Power Power Power Power Power Power Power Power I/O
42 43 44 45 46
RESET EE_SCL EE_SDA TXD_2 DTR_2_N
I I/O I/O Output Output
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Pin 47 48 49 Name RTS_2_N RXD_2 GNDK Type Output Input Power Functional Description Serial Port 2 Request To Send (in serial protocol), active low. Serial Port 2 Serial Receive Data in from transceiver or IrDA data in from IrDA detector. Core Ground. Input Clock from external world. In normal operation mode, clock can be supplied to serial ports and used for custom BAUD Rate of user's choice. In test mode, clock will be the test clock input from external world. Power Pin (D3V3). Serial Port 2 Ring Indicator, active low. Serial Port 2 Data Set Ready (in serial protocol), active low. Serial Port 2 Data Carrier Detect (in serial protocol), active low. Serial Port 2 Clear To Send (in serial protocol), active low. Serial Port 3 Transmit Data out to transceiver, or IrDA data out to IR LED. Serial Port 3 Data Terminal Ready (in serial protocol), active low. Serial Port 3 Request To Send (in serial protocol), active low. Serial Port 3 Serial Receive Data in from transceiver, or IrDA data in from IrDA detector. Serial Port 3 Ring Indicator, active low. Serial Port 3 Data Set Ready (in serial protocol), active low. Serial Port 3 Data Carrier Detect (in serial protocol), active low. Serial Port 3 Clear To Send (in serial protocol), active low. Power Pin (1.8V)
50
EXT_CLOCK
Input
51 52 53 54 55 56 57 58 59 60 61 62 63 64
Vcc3IO RI_2_N DSR_2_N DCD_2_N CTS_2_N TXD_3 DTR_3_N RTS_3_N RXD_3 RI_3_N DSR_3_N DCD_3_N CTS_3_N VccK
Power Input Input Input Input Output Output Output Input Input Input Input Input Power
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Functional Block Descriptions Internal Regulators
An internal DC-DC Regulator is provided to convert 5V to 1.8V for Core Logic. An additional regulator is provided to convert the 5V input to 3.3V for I/O functions. These regulators eliminate the need for external voltage sources.
Interrupt-In Block
The Interrupt-In controller block gives the status of the serial port interrupt registers to the USB-2.0 Device Controller. The USB host controller periodically polls the interrupt endpoint and reads the status of the interrupts.
Wakeup Block USB-2.0 PHY
This is the physical layer of the USB interface. The USB-2.0 PHY communicates with the USB-2.0 Device Controller logic through a UTMI interface to send/receive data on the USB bus. The Wakeup block is used for remote wakeup control. The USB host can suspend operation of the device. The remote wakeup block checks for activity on the serial port pins, and if information is available, it issues a remote wakeup request to the USB-2.0 Device Controller. The Device Controller in turn requests a remote wakeup by the external host. The host issues the "Resume Signaling" command to the device, which then resumes normal operation.
USB-2.0 Device Controller
The USB-2.0 Device Controller interfaces to the internal bridge and communicates with the serial ports through the bridge logic. The device controller logic is connected to a physical layer USB-2.0 PHY which provides the USB bus interface for the chip. The device controller responds to standard as well as vendor specific requests from USB-2.0 and USB-1.1 Hosts.
I2C EEPROM Controller
The I2C EEPROM Controller interfaces to an external EEPROM and retrieves information necessary for serial port settings, Product-IDs, Vendor-IDs and other control information. The EEPROM controller logic communicates with the USB-2.0 Device Controller block which uses the information from the external EEPROM.
Bridge
The bridge logic controls traffic between the USB-2.0 Device Controller and the Serial Port Controllers. The bridge logic has synchronous RAM memories with pingpong FIFO control logic to buffer data in either direction (Bulk-In and Bulk-Out) and send it to the other side without loss. Control logic prevents overflow or underflow conditions in the memory.
Clock Generation and Resets
The Clock Generation logic is used to generate the clocks for the various BAUD rates supported by the device. The Resets block has logic for synchronous de-assertion and asynchronous assertion of Resets in the respective clock domains to various blocks.
UART / Serial Port Controllers
The Serial Port Controllers are linked to the bridge and send/receive data from the bridge interface. Each serial port controller has register logic controlling BAUD rates (50 bps - 6 Mbps), stop-bits, and parity bit settings. Each serial port has synchronous RAM memories acting as transmit and receive FIFOs to buffer outgoing and incoming data. This block has registers for interrupts, line status, and line control features which can be accessed by software. The Serial Port Controllers can interface to external RS-232 / RS-422 / RS-485 transceivers.
BAUD Clock Generators
The BAUD Clock Generator block generates clocks for each of the Serial Port Controllers depending on the BAUD settings from the host. A source clock is generated from the Clock Recovery block which is further divided or used as is by the BAUD Clock Generator logic depending on the BAUD settings.
PLL Clock Generator
The PLL generates a master clock which the other blocks use to generate the various BAUD rates. The PLL supports a wide range of clock inputs to support industrial standard serial port bit rates, as well as custom BAUD rates.
Vendor Specific Command Processor
The bridge logic interfaces to a vendor specific command processor block containing commands/register settings (BAUD settings etc.) which are specific to this device.
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UART Functional Description Overview The UARTs are high performance serial ports that comply with the 16c550 specification. All UARTs are similar in operation and function, and are described in this section. The function of a single UART is described below. Operation Modes The UARTs are backward compatible with 16c450 and 16c550 devices. The operation of the port depends upon the mode settings, which are described throughout the rest of this section. The modes, conditions and corresponding FIFO depth are tabulated below. UART Mode 450 550 FIFO Size 1 16 FCR[0] 0 1
450 Mode After the hardware reset, bit-0 of the FIFO Control Register (FCR) is cleared, and the UART is compatible with the 16c450 mode of operation. The transmitter and receiver FIFOs (referred to as the "Transmitter Holding Register" and "Receiver Holding Register" respectively) have a depth of one. This mode of operation is known as "Byte Mode".
550 Mode After the hardware reset, writing a 1 to FCR[0] will increase the FIFO size to 16, providing compatibility with 16c550 devices. In 16c550 mode, the device has the following features: * RTS/CTS hardware flow control or DSR/DTR hardware flow control * Infrared IrDA format transmit & receive mode * Deeper (16-Byte) FIFOs
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UART Register-Set and Register Descriptions The UART has 10 registers, but only three address lines to access those registers. The mapping of the registers is dependent upon the Line Control Register (LCR). LCR[7] enables the Divider Latch Registers (DLL & DLM). The following table gives the various UART registers and their offsets.
Register Offset R/W Bit-7 Name THR RHR IER 0 0 1 W R R/W
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Data to be transmitted ( Transmitter Holding Register) Data to be received (Receiver Holding Register) Reserved RHR Trigger Level FIFOs Enabled DLE Tx Break Sleep Mode Reserved Reserved Force Parity RTS/CTS Flow Control THR Empty DSR Odd/Even Parity Loop Rx Break CTS Modem Int Mask Reserved Rx Stat Int Mask Flush THR Tx Rdy Int Mask Flush RHR Rx Rdy Int Mask FIFO Enable Interrupt Pending Data Length RTS Overrun Error DSR DTR Rx Rdy CTS
FCR ISR LCR MCR LSR MSR SPR DLL DLM
2 2 3 4 5 6 7 0 1
W R R/W R/W R R R/W R/W R/W
Interrupt Priority Parity Enable Stop Bits
DTR - DSR/ DCD Flow Control Data Tx Error Empty DCD RI
Unused Framing Error DCD Parity Error Teri
Scratch Pad Register Divisor Latch bits[7:0] Divisor Latch bits[15:8]
Additional standard registers - these are accessed when LCR[7] = 1
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Transmitter Holding Register & Receiver Holding Register (THR & RHR): Data is written into the bottom of the THR queue & read from the top of the RHR queue completely asynchronously to the operation of the transmitter & receiver. The size of the FIFOs is dependent upon the setting of the FCR register. Data written to the THR when it is full, is lost. Data read from the RHR when it is empty, is invalid. The empty and full status of the FIFOs is indicated in the Line Status Register.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
THR Data to be transmitted 0 Write Only LCR[7] = 0 (unknown) - based on memory Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Data to be transmitted
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
RHR Data to be received 0 Read Only LCR[7] = 0 (unknown) - based on memory Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Data to be received
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Interrupt Enable Register (IER): Serial channel interrupts are enabled using the Interrupt Enable Register (IER).
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
IER Interrupt Enable Register 1 Read/Write LCR[7] = 0 0x0C Bit[6] Reserved Bit[5] Bit[4] Sleep Mode Bit[3] Modem Int Mask Bit[2] Rx Stat Int Mask Operation Logic 0: Disable the Receiver Ready Interrupt Logic 1: Enable the Receiver Ready Interrupt Logic 0: Disable the Transmitter Ready Interrupt Logic 1: Enable the Transmitter Ready Interrupt Logic 0: Disable the Receiver Status Interrupt (Normal Mode) Logic 1: Enable the Receiver Status Interrupt (Normal Mode) Logic 0: Disable the Modem Status Interrupt Logic 1: Enable the Modem Status Interrupt Logic 0: Disable Sleep Mode Logic 1: Enable Sleep Mode where by the internal clock of the channel is switched OFF Reserved Bit[1] Tx Rdy Int Mask Bit[0] Rx Rdy Int Mask
Bit 0 1
Description Rx Rdy Interrupt Mask Tx Rdy Interrupt Mask Rx Stat Interrupt Mask Modem Interrupt Mask Sleep Mode Reserved
2
3 4 [7:5]
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FIFO Control Register (FCR): The FCR controls the UART behavior in various modes.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
FCR FIFO Control Register 2 Write 0x00 Bit[6] Bit[5] Bit[4] Bit[3] Reserved Bit[2] Flush THR Operation Logic 0: Byte Mode Logic 1: FIFO Mode Logic 0: No change Logic 1: Flushes the contents of RHR, This is operative only in FIFO mode. The RHR is automatically flushed whenever changing between Byte Mode and FIFO Mode. The bit will return to zero after clearing the FIFO. Logic 0: No change Logic 1: Flushes the content of the THR, in the same manner as FCR[1] does the RHR Reserved Reserved See Table Below Bit[1] Flush RHR Bit[0] Enable FIFOs
RHR Trigger Level
Reserved
Bit 0
Description Enable FIFO Mode
1
Flush RHR
2 3 [5:4] [7:6]
Flush THR Reserved Reserved RHR Trigger Level
In 550 Mode, the receiver FIFO trigger levels are defined by FCR[7:6]. The interrupt trigger level & flow control trigger level where appropriate are defined by L2 in the table. L1 defines a lower flow control trigger level. The two trigger levels used together introduce a hysteresis element into the hardware RTS/CTS flow control. In Byte Mode (450 Mode) trigger levels are all set to 1.
FCR[7:6] 2'b00 2'b01 2'b10 2'b11
550 Mode (FIFO = 16) L1 1 1 1 1 L2 1 4 8 14
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Interrupt Status Register (ISR): The source of the highest priority pending interrupt is indicated by the contents of the Interrupt Status Register. There are five sources of interrupts and four levels of priority (1 is the highest) as tabulated below:
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
ISR Interrupt Status Register 2 Read 0x00 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Interrupt Priority (All Modes) Bit[1] Bit[0] Interrupt Pending
FIFOs Enabled
Interrupt Priority (Enhanced Mode)
Priority Level 1 Interrupt Source and Priority Table 2a 2b 3 4
Interrupt Source No interrupt pending Receiver Status Error or address bit detected in 9-bit mode Receiver Data Available Receiver Time-Out Transmitter THR Empty Modem Status Change
ISR[5:0] 6'b000001 6'b000110 6'b000100 6'b001100 6'b000010 6'b000000
Note: ISR[0] indicates whether any interrupt is pending
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Line Control Register (LCR): The LCR specifies the data format that is common to both transmitter and receiver.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7] DLE
LCR Line Control Register 3 Read/Write 0x00 Bit[6] TX Break Bit[5] Force Parity Bit[4] Odd/Even Parity Bit[3] Parity Enable Bit[2] Bit[1] Bit[0] Data Length
Number of Stop-Bits
LCR[1:0] Data Length of serial characters. LCR[2] Number of Stop-Bits per serial character.
LCR[1:0] 2'b00 2'b01 2'b10 2'b11
Data Length 5 bits 6 bits 7 bits 8 bits
LCR[5:3] Parity Type The selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. In 9-bit mode parity is disabled and LCR[5:3] are ignored. LCR[6] Transmission Break Logic 0: Transmission Break Disabled. Logic 1: Forces the transmitter data output SOUT low to alert the communications channel, or sends zeroes in IrDA mode. Divisor Latch Enable Logic 0: Accesses to DLL and DLM registers disabled. Logic 1: Accesses to DLL and DLM registers enabled.
LCR[2] 0 1 1
Data Length 5, 6, 7, 8 5 6, 7, 8
Number of Stop-Bits 1 1.5 2
LCR[5:3] 3'bxx0 3'b001 3'b011 3'b101 3'b111
Parity Type No Parity Odd Parity Even Parity Parity bit forced to 1 Parity bit forced to 0
LCR[7]
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Line Status Register (LSR): This register provides the status of the data transfer to CPU.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7] Data Error Bit 0
LSR Line Status Register 5 Read 0x00 Bit[6] Tx Empty Bit[5] THR Empty Bit[4] Rx Break Bit[3] Framing Error Bit[2] Parity Error Operation Logic 0: RHR is empty Logic 1: RHR is not empty. Data is available to be read Logic 0: No overrun error Logic 1: Data was received when the RHR was full, An overrun has occurred. The error is flagged when the data would normally have been transferred to the RHR. Logic 0: No parity error in normal mode or 9th bit received data is "0" in 9-bit mode. Logic 1: Data has been received that did not have correct parity Logic 0: No framing error Logic 1: Data has been received with an invalid stop-bit. Logic 0: No receiver break error Logic 1: The receiver received a break error Logic 0: Transmitter FIFO is not empty Logic 1: Transmitter FIFO is empty Logic 0: The transmitter is not idle Logic 1: THR is empty & the transmitter has completed the character in the shift register and is in the idle mode Logic 0: Either there is no receiver data error in the FIFO or it was cleared by an earlier read of LSR Logic 1: At least one parity error, framing error or break indication is present in the FIFO. Bit[1] Overrun Error Bit[0] Rx Rdy
Description RHR Data Available RHR Overrun
1
2
Received Data Parity Error Received Data Framing Error Receiver Break Error THR Empty Transmitter & THR Empty
3 4 5
6
7
Receiver Data Error
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Modem Control Register (MCR): This register controls the UART's flow control and self diagnostic features.
Register: Description: Offset: Permissions: Access Condition: Default Value:
MCR Modem Control Register 4 Read/Write 0x00 550 Mode Bit[7] Bit[6] Bit[5] CTS/RTS Flow Control Bit[4] Internal Loop Back Enable Bit[3] Reserved Bit[2] Reserved Bit[1] RTS Bit[0] DTR
DTR-DSR/DCD Flow Control
Bit 0 1 2 3 4 5 6 7
Description DTR RTS Reserved Reserved Loop-Back Mode CTS/RTS Flow Control DTR/DSR Flow Control DCD Flow Control
Operation Logic 0: Forces DTR# output to inactive (high) Logic 1: Forces DTR# output to active (low) Logic 0: Forces RTS# output to inactive (high) Logic 1: Forces RTS# output to active (low) Reserved Reserved Logic 0: Normal operating mode Logic 1: Enable local Loop-Back Mode Logic 0: CTS/RTS flow control disabled in 550 mode Logic 1: CTS/RTS flow control enabled in 550 mode Logic 0: DTR/DSR flow control disabled in 550 mode Logic 1: DTR/DSR flow control enabled in 550 mode Logic 0: DCD flow control disabled in 550 mode Logic 1: DCD flow control enabled in 550 mode
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Modem Status Register (MSR): This register provides the status of the modem control lines to CPU.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7] DCD Bit 0
MSR Modem Status Register 6 Read 0x00 Bit[6] RI Bit[5] DSR Bit[4] CTS Bit[3] DCD Bit[2] Teri Operation Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: Logic 0: Logic 1: No change in the CTS signal Indicates that the CTS input has changed since the last time the MSR was read No change in the DSR signal Indicates that the DSR input has changed since the last time the MSR was read No change in the RI signal Indicates that the RI input has changed from low to high since the last time the MSR was read No change in the DCD signal Indicates that the DCD input has changed since the last time the MSR was read CTS# line is 1 CTS# line is 0 DSR# line is 1 DSR# line is 0 RI# line is 1 RI# line is 0 DCD# line is 1 DCD# line is 0 Bit[1] DSR Bit[0] CTS
Description Delta CTS
1
Delta DSR
2
Trailing Edge of RI
3 4 5 6 7
Delta DCD CTS DSR RI DCD
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Scratch Pad Register (SPR): The scratch pad register does not influence operation of the UART in RS-232 mode in any way, and is used for temporary data storage. When using RS-422/485 Mode, bit[6] and bit[7] of the Scratch Pad Register are used for mode setting and DTR active level settings.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
SPR Scratch Pad Register 7 Read/Write 0x00 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Scratch Pad Register Data
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Divisor Latch Registers (DLL & DLM): The Divisor Latch Registers are used to program the BAUD Rate divisor. This is a value between 1 and 65535 by which the input clock is divided in order to generate serial BAUD rates. After the hardware reset, the BAUD Rate used by the transmitter & receiver is given by: BAUD Rate = Input Clock / (16 * Divisor) where divisor is given by (256 * DLM) + DLL. More flexible BAUD rate generation options are also available.
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
DLL Divisor Latch (Least Significant Byte) 0 Read/Write LCR[7] = 1 0x01 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Least Significant Byte of divisor latch
Register: Description: Offset: Permissions: Access Condition: Default Value: Bit[7]
DLM Divisor Latch (Most Significant Byte) 1 Read/Write LCR[7] = 1 0x00 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Most Significant Byte of divisor latch
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RS-422 / RS-485 Mode Support Two additional modes of serial port operation are supported, these are: * RS-422 Mode - Full Duplex Serial Port for industrial applications * RS-485 Mode - Half Duplex Serial Port for industrial applications
RS-485 The RS-485 mode can be set using the Scratch Pad Register bit[6] and bit[7] for each serial port. This mode is a half duplex mode and the external transceiver is controlled for transmission or reception using the enable signal.
RS-422 This is the full duplex mode. This mode will work without the use of the DTR signal for external transceiver control.
Scratch Pad Scratch Pad Bit[7] Bit[6] 0 X
Operation Summary RS-485 Mode Disabled RS-485 Mode Enabled, DTR High = Rx DTR Low = Tx RS-485 Mode Enabled DTR Low = Rx DTR High = Tx
1
0
1
1
This is the default selection when RS485 mode is selected through driver property sheets.
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Configuration Options Four serial ports can be configured for operation. To program and access the serial ports via software, endpoint numbers have been assigned so that serial ports can be configured from the USB side. Endpoint 0 1 2 3 4 5 6 7 8 9 Type Control Endpoint Bulk-In Bulk-Out Bulk-In Bulk-Out Bulk-In Bulk-Out Bulk-In Bulk-Out Function Default Functionality Serial Port - 1 Serial Port - 1 Serial Port - 2 Serial Port - 2 Serial Port - 3 Serial Port - 3 Serial Port - 4 Serial Port - 4 Size (Bytes) (USB-1.1 / USB-2.0) 8 / 64 64 / 512 64 / 512 64 / 512 64 / 512 64 / 512 64 / 512 64 / 512 64 / 512 5 or 13 *
Interrupt Status Endpoint * Controlled by DCR1 bit-6
Serial Port Set/Get Commands Vendor commands are the vendor specific USB setup commands. The purpose of the vendor commands is to set/get the contents of the application registers. The following table provides information on the various vendor specific commands. Windex [7:0] is the register index from where data is to be read. Brequest specifies whether to read or write. * 0x0E = write to the application register * 0x0D = read from the application register Wvalue specifies the application number and data to be written (ww = data). * 0x01ww is the application number for Serial Port-1 * 0x02ww is the application number for Serial Port-2 * 0x03ww is the application number for Serial Port-3 * 0x04ww is the application number for Serial Port-4 * 0x09ww is the application number for EEPROM Write/Read * 0x00ww is the application number provided for accessing the Control Registers which control the UARTs. It is possible to enable higher BAUD rates, and features like auto hardware flow control using the Control Registers
Note: "N" in Wvalue and Register Name columns indicate the corresponding serial port number.
Windex is the offset of the register to read/write. Wlength is the length of the data to read/write.
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USB-2.0 to Four Serial Ports
bmrequestType 0xC0 0xC0 0xC0 Get Application Vendor Specific Command (Serial Port -N) 0xC0 0xC0 0xC0 0xC0 0xC0 0xC0 0xC0
Brequest 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D 0x0D
Wvalue 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00 0x0N00
Windex 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0000 0x0001
Wlength 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001
Register Name SPN_RHR SPN_IER SPN_IIR SPN_LCR SPN_MCR SPN_LSR SPN_MSR SPN_SPR SPN_DLL SPN_DLM
bmrequestType 0x40 0x40 Set Application Vendor Specific Command (Serial Port -N) 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40
Brequest 0x0E 0x0E 0x0E 0x0E 0x0E 0x0E 0x0E 0x0E 0x0E 0x0E
Wvalue 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww 0x0Nww
Windex 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0000 0x0001
Wlength 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001 0x0001
Register Name SPN_THR SPN_IER SPN_FCR SPN_LCR SPN_MCR SPN_LSR SPN_MSR SPN_SPR SPN_DLL SPN_DLM
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USB-2.0 to Four Serial Ports
USB Device Descriptors Device Descriptor BLength BDescriptorType BcdUSB BcdUSB BDeviceClass BDeviceSubClass BDeviceProtocol bMaxPacketSize0 IdVendor IdVendor IdProduct IdProduct BcdDevice BcdDevice iManufacturer iProduct iSerialNumber BNumConfigurations Location 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Data 8'h12 8'h01 8'h00 8'h02 8'hFF 8'h00 8'hFF 8'h40 8'h10 8'h97 8'h40 8'h78 8'h01 8'h00 8'h00 / 02 * 8'h00 / 03 * 8'h00 / 01 * 8'h01
* Values returned Without / With the Serial EEPROM present.
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Configuration Descriptor BLength BDescriptorType WtotalLength(L) USB Configuration Descriptors WtotalLength(M) BNumInterfaces BConfigurationValue IConfiguration BmAttributes BMaxPower
Index 0 1 2 3 4 5 6 7 8
Data 8'h09 8'h02 8'h51 8'h00 8'h01 8'h01 8'h00 8'hA0 8'h32 (100 mA)
Configuration Descriptor BLength BDescriptorType USB Interface Descriptors BInterfaceNumber BAlternateSetting BNumEndpoints BInterfaceClass BInterfaceSubClass BInterfaceProtocol IInterface
Index 0 1 2 3 4 5 6 7 8
Data 8'h09 8'h04 8'h00 8'h00 8'h09 8'hFF 8'h00 8'hFF 8'h00
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Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8'h07 8'h05 8'h81 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-1 Serial Port 1 Bulk-In
Endpoint-2 Serial Port 1 Bulk-Out
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes WmaxPacketSize(L) WmaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h02 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-3 Serial Port 2 Bulk-In
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h83 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-4 Serial Port 2 Bulk-Out
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h04 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
* Values for Full Speed & High Speed USB Rev. 1.2 Page 25
MCS7840
USB-2.0 to Four Serial Ports
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval Index 0 1 2 3 4 5 6 Data 8'h07 8'h05 8'h85 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-5 Serial Port 3 Bulk-In
Endpoint-6 Serial Port 3 Bulk-Out
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h06 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-7 Serial Port 4 Bulk-In
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h87 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
Endpoint-8 Serial Port 4 Bulk-Out
Configuration Descriptor bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h08 8'h02 8'h40/8'h00 * 8'h00/8'h02 * 8'hFF
* Values for Full Speed & High Speed USB Page 26 Rev. 1.2
MCS7840
USB-2.0 to Four Serial Ports
Configuration Descriptor bLength bDescriptorType bEndpointAddress Endpoint-9 Interrupt Endpoint bmAttributes wMaxPacketSize(L) wMaxPacketSize(M) bInterval
Index 0 1 2 3 4 5 6
Data 8'h07 8'h05 8'h89 8'h03 8'h0A 8'h00
* 8'h01 / 8'h05 (default FS/HS) * programmable using intr_pg_fs , intr_pg_hs
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EEPROM Content Layout Bytes [1:0] [3:2] [5:4] [7:6] 8 9 10 11 12 13 14 15 16 17 18 19 20 21 [23:22] [71:24] [113:72] [129:114] # of Bytes 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 48 42 16 Name EE Check VID PID RN SER1_DCR0 SER1_DCR1 SER1_DCR2 SER2_DCR0 SER2_DCR1 SER2_DCR2 SER3_DCR0 SER3_DCR1 SER3_DCR2 SER4_DCR0 SER4_DCR1 SER4_DCR2 intr_pg_fs intr_pg_hs Language ID Manufacture ID Product Name Serial Number Description EEPROM Present Check value = 0x9710 Vendor ID = 0x9710 Product ID = 0x7840 Release Number in BCD format = 0x0001 Device Configuration Registers (SER1_DCR0) Device Configuration Registers (SER1_DCR1) Device Configuration Registers (SER1_DCR2) Device Configuration Registers (SER2_DCR0) Device Configuration Registers (SER2_DCR1) Device Configuration Registers (SER2_DCR2) Device Configuration Registers (SER3_DCR0) Device Configuration Registers (SER3_DCR1) Device Configuration Registers (SER3_DCR2) Device Configuration Registers (SER4_DCR0) Device Configuration Registers (SER4_DCR1) Device Configuration Registers (SER4_DCR2) Binterval value for Full Speed Binterval value for High Speed Language ID in HEX Format (0x0409 default) "MosChip Semiconductor" in UNICODE "USB-Serial Controller" in UNICODE "X7X6X5X4X3X2X1X0" in UNICODE
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EEPROM Contents for MCS7840 (Example Contents)
EE_Check, VID, PID, RN, SER1_DRC0, SER1_DRC1, SER1_DRC2, SER2_DRC0, SER2_DRC1, SER2_DRC2, SER3_DRC0, SER3_DRC1, SER3_DRC2, SER4_DRC0, SER4_DRC1, SER4_DRC2, INTR_PG_FS, INTR_PG_HS, Language ID, Manufacture ID, MosChip 4D 6F 73 43 68 69 70 Sem i co nduc t o r
20 53 65 6D 69 63 6F 6E 64 75 63 74 6F 72 Product Name, USB-Ser ia l 55 53 42 2D 53 65 72 69 61 6C Cont ro l ler 20 43 6F 6E 74 72 6F 6C 6C 65 72 Serial Number
Location HEX ASCII 0 10 1 97 2 10 3 97 4 40 5 78 6 01 7 00 8 01 9 85 10 24 11 01 12 80 13 24 14 01 15 80 16 24 17 01 18 80 19 24 20 01 21 05 22 09 23 04 24 4D M 25 00 26 6F o 27 00 28 73 s 29 00 30 43 C 31 00 32 68 h 33 00 34 69 i 35 00 36 70 p 37 00 38 20 Space 39 00 40 53 S 41 00 42 65 e 43 00
Location HEX ASCII 44 6D m 45 00 46 69 i 47 00 48 63 c 49 00 50 6F o 51 00 52 6E n 53 00 54 64 d 55 00 56 75 u 57 00 58 63 c 59 00 60 74 t 61 00 62 6F o 63 00 64 72 r 65 00 66 20 Space 67 00 68 20 Space 69 00 70 20 Space 71 00 72 55 U 73 00 74 53 S 75 00 76 42 B 77 00 78 2D 79 00 80 53 S 81 00 82 65 e 83 00 84 72 r 85 00 86 69 i 87 00
Location HEX 88 61 89 00 90 6C 91 00 92 20 93 00 94 43 95 00 96 6F 97 00 98 6E 99 00 100 74 101 00 102 72 103 00 104 6F 105 00 106 6C 107 00 108 6C 109 00 110 65 111 00 112 72 113 00 114 4D 115 00 116 6F 117 00 118 73 119 00 120 43 121 00 122 68 123 00 124 69 125 00 126 70 127 00 128 20 129 00
ASCII a l Space C o n t r o l l e r M o s C h i p Space
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Device Configuration Bit Fields and Descriptions Bytes 4, 5, 6 and 22-30 form twenty-four 8-bit DCR Registers. These Bytes are read from the EEPROM, and loaded into the Global Device Configuration Registers after Power-On Reset. They can be programmed by software using the following application number and register indexes as shown in the table. EEPROM Location 8 9 10 11 12 13 14 15 16 17 18 19 DCR Bit SER1_DCR[7:0] SER1_DCR[15:8] SER1_DCR[23:16] SER2_DCR[7:0] SER2_DCR[15:8] SER2_DCR[23:16] SER3_DCR[7:0] SER3_DCR[15:8] SER3_DCR[23:16] SER4_DCR[7:0] SER4_DCR[15:8] SER4_DCR[23:16] DCR Name SER1_DCR0 SER1_DCR1 SER1_DCR2 SER2_DCR0 SER2_DCR1 SER2_DCR2 SER3_DCR0 SER3_DCR1 SER3_DCR2 SER4_DCR0 SER4_DCR1 SER4_DCR2 Application Number 0 0 0 0 0 0 0 0 0 0 0 0 Register Index 4 5 6 22 23 24 25 26 27 28 29 30 Default Value 0x01 0x85 0x24 0x01 0x84 0x24 0x01 0x84 0x24 0x01 0x84 0x24
The following tables describe the function of each bit in the DCR registers. There are three DCR registers for each Serial Port (IrDA). In the absence of an EEPROM, the default values are taken from the Device Configuration Registers.
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Serial Port 1 - Device Configuration Register 0
Bit[7] Reserved Bit[6] IrDA_ Mode Bit[5] RTS_ CM Bit[4] Bit[3] GPIO_ Mode Bit[2] Bit[1] Reserved Bit[0] RS_ SDM Default Value
DCR0 Bit
Name
Definition RS-232 / RS-422 / RS-485 Transceiver Shut-Down Mode:
0
RS_ SDM
0:
Do not shut down the transceiver Even when USB SUSPEND is engaged
1
1 [3:2]
Reserved GPIO_ Mode
Shut down the transceiver when USB SUSPEND is engaged Reserved 00: GPIO = Input 10: GPIO = Output RTSM RTS Control Method: RTS is controlled by Control Bit Map. Signal is active low; RTS is controlled by Control Bit Map. Signal is active high;
1:
0 00
00:
01: [5:4] RTS_ CM
00 10: Drive RTS active when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS inactive. Drive RTS inactive when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS active. RS-232 / RS-422 / RS-485 Serial Port Mode. IrDA Mode. Reserved
11:
6 7
IrDA_ Mode Reserved
0: 1:
0 0
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Serial Port 1 - Device Configuration Register 1
Bit[7] Reserved Bit[6] Interrupt IN Endpoint Status Bit[5] PLL_ Power-Down Bypass Control Bit[4] RW_ INHB Bit[3] Tx_I_ PMG Bit[2] Bit[1] GPIO_I_ PMG Bit[0]
DCR1 Bit
Name
Definition These two bits set the output current of the GPIO lines:
Default Value
[1:0]
GPIO_I_ PMG
00: 01: 10: 11:
6 mA 8 mA (Default) 10 mA 12 mA These two bits set the output current of Serial output signals TxD, DTR_n and RTS_n: 6 mA 8 mA (Default) 10 mA 12 mA RW_INH Remote Wake Inhibit: Enable the USB Remote Wakeup function Inhibit the USB Remote Wakeup function Enables PLL Power-Down Disables PLL Power-Down Interrupt Endpoint returns 5 Bytes of data. Interrupt Endpoint returns 5 Bytes + 8 Bytes of the Bulk-In/Out memory controller status Reserved
01
[3:2]
Tx_I_ PMG
00: 01: 10: 11:
01
4
RW_ INHB PLL_ Power-Down Bypass Control Interrupt IN Endpoint Status Reserved
0: 1: 0: 1: 0: 1:
0
5
0
6 7
0 1
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Serial Port 1 - Device Configuration Register 2
Bit[7] SHDN_ POL DCR2 Bit 0 Bit[6] Reserved Bit[5] RWU_ Mode Bit[4] EWU_ Rx Bit[3] EWU_ DSR Bit[2] EWU_ RI Bit[1] EWU_ DCD Bit[0] EWU_ CTS Default Value 0
Name EWU_ CTS
Definition Enable Wake Up Trigger on CTS: 0: 1: Disabled Enable Wake Up Trigger on CTS State Changes. Enable Wake Up Trigger on DCD: Disabled Enable Wake Up Trigger on DCD State Changes. Enable Wake Up Trigger on RI: Disabled Enable Wake Up Trigger on RI State Changes. Enable Wake Up Trigger on DSR: Disabled Enable Wake Up Trigger on DSR State Changes. Enable Wake Up Trigger on RXD: Disabled Enable Wake Up Trigger on RXD State Changes. Remote Wakeup Mode: Engages Remote Wakeup, The device issues Disconnect Signal.
1
EWU_ DCD
0: 1:
0
2
EWU_ RI
0: 1:
1
3
EWU_ DSR
0: 1:
0
4
EWU_ Rx
0: 1:
0
5
RWU_ Mode
0:
1
6
Reserved SHDN_ POL
Engages Remote Wakeup, The device issues Resume Signal. Reserved SHDN Polarity: 0: 1: Pin 12 Active Low Shut-Down Signal. Pin 12 Active High Shut-Down Signal.
1:
0
7
0
Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0.
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Serial Port (2, 3, & 4) - Device Configuration Register 0 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options.
Bit[7] Reserved Bit[6] IrDA_ Mode Bit[5] RTS_ CM Bit[4] Bit[3] Bit[2] Bit[1] Reserved Bit[0] RS_ SDM Default Value
Reserved
DCR0 Bit
Name
Definition RS-232 / RS-422 / RS-485 Transceiver Shut-Down Mode:
0
RS_ SDM
0:
Do not shut down the transceiver Even when USB SUSPEND is engaged Shut down the transceiver when USB SUSPEND is engaged Reserved Reserved RTSM RTS Control Method: RTS is controlled by Control Bit Map. Signal is active low; RTS is controlled by Control Bit Map. Signal is active high;
1
1: 1 [3:2] Reserved Reserved
0 00
00:
01: [5:4] RTS_ CM
00 10: Drive RTS active when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS inactive. Drive RTS inactive when Downstream Data Buffer is NOT EMPTY; Otherwise Drive RTS active. RS-232 / RS-422 / RS-485 Serial Port Mode. IrDA Mode. Reserved
11:
6 7
IrDA_ Mode Reserved
0: 1:
0 0
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Serial Port (2, 3, & 4) - Device Configuration Register 1 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options.
Bit[7] Reserved Bit[6] Reserved Bit[5] Reserved Bit[4] RW_ INHB Bit[3] Tx_I_ PMG Bit[2] Bit[1] Bit[0]
Reserved
DCR1 Bit [1:0]
Name Reserved
Definition Reserved These two bits set the output current of Serial output signals TxD, DTR_n and RTS_n: 00: 01: 10: 11: 6 mA 8 mA (Default) 10 mA 12 mA RW_INH Remote Wake Inhibit: Enable the USB Remote Wakeup function Inhibit the USB Remote Wakeup function Reserved Reserved Reserved
Default Value 00
[3:2]
Tx_I_ PMG
01
4 5 6 7
RW_ INHB Reserved Reserved Reserved
0: 1:
0 0 0 1
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Serial Port (2, 3, & 4) - Device Configuration Register 2 The Configuration Registers for these three Serial Ports are all identical. They are very similar to Serial Port 1, but have a few less configuration options.
Bit[7] Reserved Bit[6] Reserved Bit[5] RWU_ Mode Bit[4] EWU_ Rx Bit[3] EWU_ DSR Bit[2] EWU_ RI Bit[1] EWU_ DCD Bit[0] EWU_ CTS Default Value 0
DCR2 Bit 0
Name EWU_ CTS
Definition Enable Wake Up Trigger on CTS: 0: 1: Disabled Enable Wake Up Trigger on CTS State Changes. Enable Wake Up Trigger on DCD: Disabled Enable Wake Up Trigger on DCD State Changes. Enable Wake Up Trigger on RI: Disabled Enable Wake Up Trigger on RI State Changes. Enable Wake Up Trigger on DSR: Disabled Enable Wake Up Trigger on DSR State Changes. Enable Wake Up Trigger on RXD: Disabled Enable Wake Up Trigger on RXD State Changes. Remote Wakeup Mode: Engages Remote Wakeup, The device issues Disconnect Signal. engages remote wakeup, the Device issues resume signal. Reserved Reserved
1
EWU_ DCD
0: 1:
0
2
EWU_ RI
0: 1:
1
3
EWU_ DSR
0: 1:
0
4
EWU_ Rx
0: 1:
0
5
RWU_ Mode
0:
1
1: 6 7 Reserved Reserved
0 0
Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0.
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USB-2.0 to Four Serial Ports
Electrical Specifications Absolute Maximum Ratings: Core Power Supply (VccK) Power Supply of 3.3V I/O (Vcc3I0) Input Voltage of 3.3V I/O (Vin3 ) Input Voltage of 5V Tolerant I/O (Vin5) Operating Temperature Storage Temperature ESD HBM (MIL-STD 883E Method 3015-7 Class 2) ESD MM (JEDEC EIA/JESD22 A115-A) CDM (JEDEC/JESD22 C101-A) Latch-up (JESD No. 78, March 1997) Junction Temperature (Tj) Thermal Resistance of Junction to Ambient (Still Air) -0.3 to 2.16 V -0.3 to 4.0 V -0.3 to 4.0 V -0.3 to 5.8 V 0 to +70 C -40 to +150 C 2000 V 200 V 500 V 200 mA, 1.5 x VCC 115 C 65 C/W
Operating Conditions: Symbol Vcc5A VccK Vcc3IO REG02_V18 IREG02_V18 REG06_VCC33 IREG06_VCC33 I5V I3.3V I1.8V Parameter 5V Power Supply Input Core Power Supply Power Supply of 3.3V I/O 1.8V Regulator Output 1.8V Regulator Current 3.3V Regulator Output 3.3V Regulator Current Operating current of 5V when 3.3V and 1.8V internal regulators are used. No serial load. Operating current of 3.3V. No serial load. Operating current of 1.8V. No serial load. 70 45 25 3.14 3.3 Min 4.5 1.62 2.97 1.71 Typ 5.0 1.8 3.3 1.8 Max 5.5 1.98 3.63 1.89 70 3.46 250 Units V V V V mA V mA mA mA mA
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DC Characteristics of 3.3V I/O Cells Symbol VccK Vcc3IO ViL ViH Vt VtVt+ VoL VoH Parameter Core Power Supply Power Supply Input Low Voltage Input High Voltage Switching Threshold Schmitt Trigger Threshold Voltage Output Low Voltage Output High Voltage Condition Core Area 3.3V I/O LVTTL LVTTL LVTTL LVTTL IoL= 2 to 24mA IoH= -2 to -24mA 2.4 0.8 2.0 1.5 1.1 1.6 2.0 0.4 Min 1.62 2.97 Typ 1.8 3.3 Max 1.98 3.63 0.8 Units V V V V V V V V
DC Characteristics of 5V Tolerant I/O Cells Symbol Vcc5A ViL ViH Vt VtVt+ VoH VoH Parameter 5V Power Supply Input Low Voltage Input High Voltage Switching Threshold Schmitt Trigger Threshold Voltage Output Low Voltage Output High Voltage Condition 5V I/O LVTTL LVTTL LVTTL LVTTL IoL= 2 to 24 mA IoH= -2 to -24 mA 2.4 0.8 2.0 1.5 1.1 1.6 2.0 0.4 Min 4.5 Typ 5.0 Max 5.5 0.8 Units V V V V V V V
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HE E
64 1
49 48
16 17 32
33
D
HD e b
A2 A1
c
L
Symbol A1 A2 b c e L HD D HE E
MIN 0.05 1.35 0.17 0.09
Millimeters TYP MAX 0.15 1.45 0.27 0.20 0.50 0.75 12.25 10.10 12.25 10.10
64-Pin "CV" LQFP Package Dimensions
0.45 11.75 9.90 11.75 9.90
Rev.
1.2
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MCS7840
USB-2.0 to Four Serial Ports
IMPORTANT NOTICE
MosChip Semiconductor Technology, LTD products are not authorized for use as critical components in life support devices or systems. Life support devices are applications that may involve potential risks of death, personal injury or severe property or environmental damages. These critical components are semiconductor products whose failure to perform can be reasonably expected to cause the failure of the life support systems or device, or to adversely impact its effectiveness or safety. The use of MosChip Semiconductor Technology LTD's products in such devices or systems is done so fully at the customer risk and liability. As in all designs and applications it is recommended that the customer apply sufficient safeguards and guard bands in both the design and operating parameters. MosChip Semiconductor Technology LTD assumes no liability for customer's applications assistance or for any customer's product design(s) that use MosChip Semiconductor Technology, LTD's products. MosChip Semiconductor Technology, LTD warrants the performance of its products to the current specifications in effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip Semiconductor Technology, LTD imposes testing and quality control processes that it deems necessary to support this warranty. The customer should be aware that not all parameters are 100% tested for each device. Sufficient testing is done to ensure product reliability in accordance with MosChip Semiconductor Technology LTD's warranty. MosChip Semiconductor Technology, LTD believes the information in this document to be accurate and reliable but assumes no responsibility for any errors or omissions that may have occurred in its generation or printing. The information contained herein is subject to change without notice and no responsibility is assumed by MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document, nor for its use or for infringement of patent or other rights of third parties. MosChip Semiconductor Technology, LTD does not warrant or represent that any license, either expressed or implied, is granted to the user.
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USB-2.0 to Four Serial Ports
Revision History Revision 0.9 0.91 0.92 Changes Preliminary Release Corrected MaxPacketSize values (FS/HS) Corrected Wlength field in "Set Application Vendor Specific Command" Removed Preliminary Notice. Made change to reflect one GPIO port instead of two. Added Driver Support entries on page 1. Made bits 2 and 1 of the MCR register reserved. Made bit 5 of the Mode register reserved. Replaced Raid_reg1 with Rx_sampling_reg1 throughout document. Modified product ID value in EEPROM Content Layout table. Made bit 1 of Device Configuration register 0 reserved and added note. Modified description of bit 1 of Device Configuration register 0. Made bit 6 of Device Configuration register 0 reserved and added note. Clarified Linux Kernel support in Features Deleted Windows CE5.0 and Vista release dates Updated Absolute Maximum Rating table Deleted Leakage Current table Updated Operating Conditions table Updated 3.3V DC Characteristics table Updated 5V DC Characteristics table Removed dimensions in Inches from Package Dimensions table Removed `Confidential' notice from all pages Date 30-May-2006 01-Jun-2006 05-Jun-2006
1.0
28-Aug-2006
1.1
16-Sept-2006
1.2
6-August-2007
Rev.
1.2
Page 41

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