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| All-in-OneMemory SST88VP1107 SST79LF008 Notebook System Controller with 8 Mbit LPC Firmware Flash Fact Sheet FEATURES: * All-in-OneMemory: Managed Memory Subsystem for Code and Data in a Single Package - Execute-in-place (XIP) Non-volatile area - NOR area - Pseudo-NORTM (PNORTM) area - High-speed Pseudo-NOR (High-speed PNOR) area - RAM area - Memory-mapped ATA (mATA) NAND Disk area * Factory Default Memory Configuration - NOR - 512 KByte (fixed) - High-speed PNOR - 128 KByte (re-configurable) - PNOR - 128 MByte (re-configurable) - RAM - 12 MByte (re-configurable) - mATA - 120 MByte (re-configurable) * Simple Host Interface - Standard PSRAM interface for all areas - 16-bit Bus with required WAIT function - Asynchronous/Synchronous Single-access Read/Write cycles - Synchronous operation up to 80MHz - Page Mode and Burst Mode support in Highspeed PNOR, PNOR, and RAM areas - Burst length up to 32 Words * 4Mbit Built-in SST SuperFlash(R) - Standard NOR bus interface and operation - Fast erase and program with SuperFlash - Immediately available upon power-up - Active in the deep power-down mode * Configurable High-speed PNOR and PNOR - Full address range XIP emulated by using RAM as cache and NAND as non-volatile storage - Configurable memory area size to optimize NAND usage for code and data storage - Built-in cache controller provides cache coherence without host intervention - Configurable cache size for optimum performance and RAM usage - Dynamic Paging for optimum memory usage and Static Paging for minimum access latency - Built-in NAND controller provides Flash File System (FFS) without host intervention * Standard PSRAM - Up to 8 MWord (128Mbit) of RAM for host * Memory-Mapped ATA (mATA) NAND Disk Area - Up to 2 Gbit of data storage for host - Standard ATA protocol with bus cycles decoded on memory space - Built-in NAND controller performs NAND Disk function * Fast Asynchronous Access Time - NOR: 50 ns - High-speed PNOR: 90 ns initial, 30 ns page access - PNOR: 150 ns initial, 55 ns page access - RAM: 130 ns initial, 55 ns page access - mATA: 70 ns * Read/Write Performance - NOR: - Read: 40 MBytes/sec, Write: 200 KBytes/sec - High-speed PNOR (cache-hit): - Read: 140 MBytes/sec, Write: 145 MBytes/sec - PNOR (cache-hit): - Read:120 MBytes/sec, Write:130 MBytes/sec - RAM: - Read:120 MBytes/sec, Write: 130 MBytes/sec - mATA: - Read: 22 MBytes/sec, Write: 7 MBytes/sec * Protection and Security in NOR Area - Secure Boot capability - 256 Word unique ID for enhanced security - 32 KWord hardware bottom boot block protection - Two 32 KWord One Time Programmable (OTP) protected areas - 64-bit password protection * Superior NAND Flash Management - Superior data integrity through robust hardware ECC - Corrects random bit errors for SLC and MLC NAND - Built-in Microcontroller with intelligent firmware - Flash File System in embedded SuperFlash - Periodic Refresh to ensure NAND data integrity - Wear-leveling to prolong product life - Multi-tasking technology to boost NAND flash performance * Efficient Power Management Unit - Immediate disabling of unused circuitry - Fast boot time from power-down * Low Power Consumption - Active Mode current: 75 mA (typical) - Stand-by Mode curent: 500 A (typical) - Deep Power-down mode current: 300 A (typical) * 1.8V and 3.0V Power Supplies * Host Interface Voltage Selection Through VDDQ - 1.8V or 3.0V * Temperature Range - 0 to +70C for commercial operation - -25C to +85C for wireless operation * Package Available - 80-Ball Low-Profile Ball Grid Array (LBGA) 10x13mm * All non-Pb (lead-free) devices are RoHS Compliant (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 1 The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. All-in-OneMemory SST88VP1107 Fact Sheet NOR Area * Direct Mapped and Dedicated 512 KWord (4Mb) SuperFlash for Performance-critical Code and Data * Standard NOR Bus Interface and Operation * Immediately Available upon Power-On * Available in the Deep Power-Down Mode * Asynchronous Single-access Read/Write Mode - 50 ns access time * Synchronous Single-access Read/Write Mode up to 80MHz - 4 cycles initial latency for Read - 3 cycles initial latency for Write * Super Fast Word Program - 7 s (typical) * Super Fast Sector-Erase Capability - Uniform 2 KWord sectors - Sector-Erase Time: 18 ms (typical) * Super Fast Block-Erase Capability - Uniform 32 KWord blocks - Block-Erase Time: 18 ms (typical) * NOR Area-Erase Capability - Area-Erase Time: 40 ms (typical) * Erase-Suspend /-Resume Capability - Read while Erase-Suspend - Program while Erase-Suspend * JEDEC Standard Compliant - Flash EEPROM command sets * Optional Two-Cycle Command Mode * End-of-Write detection - Supports both toggle bits and data polling * Secure Boot Capability * Hardware Bottom Boot Block Protection through NWP# Input pin - 32 KWord bottom boot-block protection * Two 32 KWord user-programmable OTP areas * 256 Word Security-ID - SST: 128 Word - User: 128 Word * Volatile and Non-volatile Block Protection * 64-bit Password Protection * Superior Reliability with SST SuperFlash - Endurance: Minimum 100,000 cycles (typical) - Greater than 100 years data retention Pseudo-NORTM Area * Emulates NOR memory using PSRAM and NAND - Offers XIP access - Area size configurable up to 64 MWord - Built-in cache controller and Flash File System - Automatically loads on-demand page from NAND flash to cache * Improved NAND Reliability with Cache - Minimizes Read Disturb Errors - Extends Write Endurance * Standard PSRAM bus Interface and Operation with Required Wait Function * Uniform 1 KWord cache page size * Four configurable regions - All regions combined total size up to 64 MWord - Each region size 0 to 64 MWord - Each region served by a configurable PSRAM cache zone * Four configurable PSRAM cache zones - Four cache zones combined total size up to 8 MWord - Each cache zone size 0 to 8 MWord - Cache zone has Two Host-configurable Options for Cache Operations - Static and Dynamic Paging modes * Asynchronous Single-access Read/Write Mode - 150 ns access time * Asynchronous Page-Read Mode - 55 ns page read time * Synchronous Burst Read/Write Mode up to 80MHz - 10 cycles initial latency for Read - 7 cycles initial latency for Write (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 2 All-in-OneMemory SST88VP1107 Fact Sheet High-Speed Pseudo-NOR Area * Emulating High-speed NOR Memory Using SRAM and NAND without Host Intervention - Offers XIP access - Area size configurable up to 64 MWord - Built-in cache controller and Flash File System - Automatically loads on-demand page from NAND flash to cache * Improved NAND Reliability with Cache - Minimizes Read Disturb Errors - Extends Write Endurance * Standard PSRAM Bus Interface and Operation with Wait Function * Embedded 2 KWord High-speed SRAM as Cache * Uniform 1 KWord Cache Page Size * One Configurable Region up to 64 MWord - Region served by a cache zone in the highspeed SRAM - Cache zone has Two Host-configurable Options for Cache Operations - Static and dynamic paging modes * Asynchronous Single-access Read/Write Mode - 90 ns access time * Asynchronous Page Read Mode - 30 ns page read time * Synchronous Burst Read/Write Mode up to 80MHz - 4 cycles initial latency for Read - 3 cycles initial latency for Write RAM Area * Standard PSRAM Bus Interface and Operation * Served by portion of PSRAM not used by the PNOR Cache Zones - Up to 8 MWord (128Mbit) RAM space * Asynchronous Single-access Read/Write Mode - 130 ns access time * Asynchronous Page-Read Mode - 55 ns page read time * Synchronous Burst Read/Write Mode up to 80 MHz - 9 cycles Initial latency for Read - 6 cycles Initial latency for Write Memory-Mapped ATA NAND Disk Area * Standard ATA Protocol with Bus Cycles Decoded on Memory Space * ATA Task File Registers are Memory-Mapped * Built-in NAND controller performs NAND Disk Function - Up to 128 MWord (2 Gbit) mass storage space * Asynchronous Single-access Read/Write Mode - 70 ns access time * Synchronous Single-Access Read/Write Mode up to 80MHz - 3 cycles Initial latency for Read/Write * 8 Word address space for ATA Task File Registers * 256 Word address space for Data Registers * Performance optimized ATA Controller * Fast Wake-up Time - Standby to Read/Write: 200 ns (typical) (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 3 All-in-OneMemory SST88VP1107 Fact Sheet PRODUCT DESCRIPTION The SST88VP1107 is a reliable, high-performance, singlepackage, managed memory subsystem for code and data storage that is easy to use. Designed for embedded applications including mobile phones and portable consumer electronics, this product provides an all-in-one memory solution through its unique capability to configure its various memory resources. Providing code storage (NOR), data storage (NAND), and system RAM (PSRAM) functions all on a single bus, the SST88VP1107 is well suited for manufacturers who need high density memory with enhanced performance, superior quality, and reliability. The All-in-OneMemory includes a boot NOR Flash, NAND controller, Cache controller, high-speed SRAM, PSRAM, and NAND Flash memory in a Multi Chip Package (MCP). The embedded NOR Flash offers a fast boot time, and provides many advanced data protection features for secure boot and code protection. The dedicated, performanceoptimized NAND controller provides efficient data integrity, defect management, and wear-leveling by combining a robust hardware Error Correction Code (ECC) and a sophisticated Flash File System (FFS) in the embedded SuperFlash(R) memory. A built-in cache controller provides both static and dynamic paging modes, with controller-managed, cache-coherence operations. The SST88VP1107 utilizes the advantages of both NOR and NAND flash memories to attain faster Read, Program, and Erase operations. This unified code and data storage solution allows the host to configure the memory-area and cache sizes for optimum memory utilization. The All-in-OneMemory is highly configurable. The host device can define a variety of memory configurations using any of the following areas: a direct mapped high-performance 4 Mbit boot NOR memory area, two directly addressable Pseudo-NOR memory areas emulated by RAM and NAND, a directly addressable host RAM memory area, and a performance optimized mass storage area. Through advanced data protection features, the SST All-inOneMemory provides robust embedded security. The boot NOR area comes pre-programmed with a 128 Word unique security ID. For greater system security, program the additional 128 Word ID which creates a unique 256 Word security ID. In addition, the boot NOR area offers added security through 32 KWord hardware bottom bootblock protection, two 32 KWord One Time Programmable (OTP) secure areas, volatile block protection, non-volatile block protection, and 64 bit password protection. The SST88VP1107 offers a built-in Flash File System (FFS) that makes the NAND flash memory management transparent to the host system. This eliminates the need for (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 FFS software on the host, and reduces software development effort and time. The FFS also provides efficient defect management and effective wear-leveling algorithms to ensure even use of NAND flash media, which extend the longevity of the storage device. The hardware Error Correction Code (ECC) module ensures superior data integrity and reliability by using an advanced ECC algorithm to correct random bit errors for both SLC and MLC NAND flash. The built-in cache in the High-speed PNOR and PNOR areas improves reliability of these areas. Having a cache in front of the NAND flash helps to reduce the read disturb errors by minimizing repeated direct read access of a page to the NAND flash. The built-in cache also helps to extend the endurance of the storage device by minimizing direct write access to the NAND flash. The SST88VP1107 is offered in both commercial and wireless temperature ranges in an 80-Ball LBGA package. See Figure 2-1 for pin assignments and Table 2-1 for pin descriptions. 4 All-in-OneMemory SST88VP1107 Fact Sheet 1.0 FUNCTIONAL BLOCKS All-in-OneMemory Boot NOR SCI MCU Cache Controller Embedded Flash File System PMU Host Bus Host I/F RAM Controller High-Speed SRAM PSRAM DMA ECC NAND Flash Interface ATA Controller ATA Buffer NAND Flash 1354 B1.0 FIGURE 1-1: Functional Block Diagram (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 5 All-in-OneMemory SST88VP1107 Fact Sheet 2.0 PIN ASSIGNMENTS The pin assignments for the SST88VP1107 are shown in Figure 2-1 below. For the pin descriptions see Table 2-1. The active low signals have the suffix "#." The I/O buffer types are listed in Table 2-2. TOP VIEW (balls facing down) 8 A17 A16 A15 A22 IRQ A23 A24 SCIDI DNU DNU 7 A11 A12 VDDP A18 A19 A20 A21 VDDN SCICLK CRE 6 A8 VSSIO A9 A10 DQ6 DQ15 DQ14 DQ7 VSSIO SCIDO 5 WE# HRST# VREG VSS VSS DNU DNU DQ13 DQ11 UB# 4 NWP# WAIT RY/CRST# VDD DNU VSS A25 DQ12 CLK LB# 3 A14 VSSIO A13 DQ1 DQ2 DQ3 DQ4 DQ5 VSSIO DQ10 2 A7 A6 VDDQ A5 A4 OE# DQ0 VDDP DQ8 DQ9 1 CE1# A3 CE2# A2 CE0# A1 CE3# A0 ADV# CE4# A B C D E F G H J K 1354 80-lbga-LBS P1.0 FIGURE 2-1: Pin Assignments for 80-ball LBGA (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 6 All-in-OneMemory SST88VP1107 Fact Sheet 2.1 Pin Descriptions The pins and functions of each pin are shown in Table 2-1. TABLE Symbol Host Interface CLK HRST# RY/CRST# J4 B5 C4 I I O I1 I1 O1 Clock Input for the Synchronous Mode Hardware Reset Input (active low) Ready/CPU Reset#. Indicates to the host system that the device is in power-up initialization or reset. The host can use this output signal as Ready signal or host CPU Reset signal. A logic high state indicates that the device is ready for normal operations. Active high when used as a Ready signal and active low when used as a Reset. Chip Enable for NOR area (active low) Chip Enable for High-speed PNOR, PNOR, and RAM areas in 3-Chip-Enable mode. (factory default) Must be tied to high in 3-Chip-Enable Mode (factory default). Used for other Chip Enable Modes. (active low) Must be tied to high in 3-Chip-Enable Mode (factory default). Used for other Chip Enable Modes. (active low) Chip Enable for memory-mapped ATA (mATA) area (active low) Host Bus Configuration Register Enable (active high) Address Valid (active low) Output Enable (active low) Write Enable (active low) Upper Byte Select (active low) Lower Byte Select (active low) Write Protect Input for NOR area. Protects Bottom Boot Block from Erase/Program operations (active low) WAIT signal. When asserted, indicates to the host system that the output data is not valid during read operations and that the input data will not be latched by the device during write operations. In NOR and mATA areas, the WAIT output signal should be ignored in the Asynchronous Mode. The polarity of the WAIT output signal can be configured (default active high). mATA area Interrupt Request to Host 2-1: Pin Descriptions (1 of 3) Pin Location Pin Type I/O Type Name and Functions CE0# CE1# CE2# CE3# E1 A1 C1 G1 I I I I I1 I1 I1 I1 CE4# CRE ADV# OE# WE# UB# LB# NWP# WAIT K1 K7 J1 F2 A5 K5 K4 A4 B4 I I I I I I I I OZ I1 I1 I1 I1 I1 I1 I1 I1 OZ1 IRQ E8 O O1 (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 7 All-in-OneMemory SST88VP1107 Fact Sheet TABLE Symbol A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 2-1: Pin Descriptions (Continued) (2 of 3) Pin Location G4 G8 F8 D8 G7 F7 E7 D7 A8 B8 C8 A3 C3 B7 A7 D6 C6 A6 A2 B2 D2 E2 B1 D1 F1 H1 F6 G6 H5 H4 J5 K3 K2 J2 H6 E6 H3 G3 F3 E3 D3 G2 Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 I1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 Bi-directional Host Data Bus [15:0] Host Address Bus [25:0]. This is a word address Name and Functions (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 8 All-in-OneMemory SST88VP1107 Fact Sheet TABLE Symbol Debug Interface SCICLK DNU DNU SCIDI DNU SCIDO DNU Misc. VREG C5 Power PWR1 Internal voltage regulator output. An external ceramic capacitor (4.7F) must be connected between this pin and system ground. Power for Host Bus Interface (1.8V/3.0V) Power for PSRAM (1.8V) Power for NAND Flash (3.0V) Power for core logic (3.0V) GND for IO GND for core logic T2-1.1 1354(01) 2-1: Pin Descriptions (Continued) (3 of 3) Pin Location J7 G5 K8 H8 J8 K6 E4, F5 Pin Type I (PD) I (PU) O O I/O Type I_PD1 I_PU1 O1 O1 Name and Functions Serial Interface Clock Input Do not use. Reserved Do not use. Reserved Serial Interface Data Input Do not use. Reserved Serial Interface Data Output Do not use. Reserved Power and Ground VDDQ VDDP VDDN VDD VSSIO VSS C2 C7, H2 H7 D4 B3, B6, J3, J6 D5, E5, F4 Power Power Power Power Ground Ground PWR1 PWR1 PWR1 PWR1 PWR1 PWR1 TABLE 2-2: Input/Output (I/O) Buffer Types I/O Buffer Type I1 I_PU1 I_PD1 O1 IO1 OZ1 PWR1 Description Input buffer1 Input buffer with internal pull-up Input buffer with internal pull-down Output buffer I/O buffer Output buffer with tri-state Power or Ground pad T2-2.0 1354(01) 1. Any pin configured as input without internal pull-up or pull-down resistor must not be left unconnected. (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 9 All-in-OneMemory SST88VP1107 Fact Sheet 3.0 DEVICE ELEMENTS The All-in-OneMemory contains a boot NOR flash, 32 bit microcontroller, embedded flash file system (FFS), cache controller, ATA controller, PSRAM, and NAND flash all integrated in a LBGA package. This device has five different memory areas: NOR, High-speed Pseudo-NOR (Highspeed PNOR), Pseudo-NOR (PNOR), RAM, and memorymapped ATA (mATA). The host memory bus can write data to, and read data from, these five different memory areas. The default configuration has 3 chip enables with Highspeed PNOR, PNOR, and RAM sharing one chip enable. Refer to Figure 1-1 for the All-in-OneMemory block diagram. All-in-OneMemory interfaces with the host system through a standard PSRAM bus interface, supporting both asynchronous read/write and synchronous read/write operations. The NOR area is directly mapped to the NOR flash and is available for boot access immediately after power-up initialization. Similarly, the RAM area is directly mapped to a partition of the internal PSRAM. In the High-speed PNOR and PNOR areas, a two-way set associative cache controller moves pages between NAND flash and high-speed SRAM for the High-speed PNOR, or PSRAM for the PNOR area. This built-in cache controller supports both static and dynamic paging modes. In the mATA area, the All-in-OneMemory converts standard ATA protocols into flash media data and control signals and performs Flash File System operations to translate the host logical address to NAND physical address. The components that contribute to the All-in-OneMemory operations are described in Sections 3.1 - 3.16. 3.3 Boot NOR The boot NOR flash is used to store the boot code and any time-critical code and data. The boot NOR area is available for host access immediately after power-up initialization, and supports a minimum page size of 2 KWord. 3.4 Embedded Flash File System (FFS) The embedded Flash File System (FFS) is an integral part of the All-in-OneMemory flash memory, handling all data transfers to and from the NAND flash. The controllerembedded flash memory stores the firmware and FFS, and allows for quicker firmware upgrades, if required. The FFS performs the following tasks: * * Translates host side operations into flash memory Read and Write operations Increases longevity by providing wear-leveling to evenly distribute Write actions across the entire NAND memory Performs NAND flash bad-block management Keeps track of FFS data structure Manages system security for selected protection zones * * * 3.5 Cache Controller The built-in cache controller manages access to the Highspeed PNOR and PNOR areas. The cache controller uses a two-way set associative caching scheme to improve cache hit rate. The cache controller supports both static and dynamic paging modes with 1K Word page size. The cache coherence operations are complete managed by the cache controller without any host intervention. However, the host may issue page or flush cache commands through the device control interface, if required. 3.1 Microcontroller Unit (MCU) The 32-bit Microcontroller Unit manages internal operations of the All-in-OneMemory by translating host commands into data and control signals required for internal memory operations. 3.6 RAM Controller The RAM controller is the interface to the high-speed SRAM and the PSRAM memories. 3.2 Host Interface For Write operations, the host interface receives control signals and data from the host bus and directs them to the host-selected memory area. For Read operations, the host interface receives control signals from the host bus and drives data from the host-selected memory area to the host bus. 3.7 High-speed SRAM A 2 KWord cache zone, Zone H, serves the High-speed PNOR area. The 2 KWord high-speed SRAM is used as cache for the Zone H cache zone. (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 10 All-in-OneMemory SST88VP1107 Fact Sheet 3.8 PSRAM The PSRAM is divided into two partitions whose size is configurable by the host. One partition is the cache for the PNOR area cache zones which is served by four size-configurable cache zones--Zone 0 through Zone 3. The other partition is available to the host as system RAM. 3.15 Power Management Unit (PMU) The Power Management Unit (PMU) handles the power consumption of All-in-OneMemory. The PMU dramatically reduces power consumption by automatically putting the circuitry that is not being used in the operation into standby mode. 3.9 ATA Controller The ATA controller supports standard ATA protocols, and receives ATA commands from the host interface. This controller moves data from the host interface to the ATA buffer for ATA Write commands, and from the buffer to the host interface for ATA Read commands. 3.16 Serial Communication Interface (SCI) For additional manufacturing flexibility, the SCI bus can be used for device configuration and error reporting. This bus consists of 3 active signals: SCICLK, SCIDI, and SCIDO. SST strongly recommends providing access to the device SCI interface at the system level during development and manufacturing. 3.10 ATA Buffer A key contributor to the mATA area performance is the SRAM ATA buffer. This 512 Word buffer optimizes data transfers to and from the NAND flash media, beginning transfer when the buffer contains 256 Words. 3.11 NAND Flash Interface The multi-tasking NAND flash interface enables fast, sustained write performance by allowing multiple Read, Program, and Erase operations to several flash media chips or planes. 3.12 Error Correction Code (ECC) The hardware Error Correction Code (ECC) module utilizes an advanced ECC algorithm which corrects random bit errors for both SLC and MLC NAND flash. 3.13 NAND Flash The NAND flash is used as the non-volatile storage media for High-speed PNOR, PNOR, and mATA areas. The size of each area is configurable by the host. 3.14 Direct Memory Access (DMA) SST88VP1107 uses internal DMA engine for instant data transfer between the NAND flash and the High-speed SRAM, PSRAM, or ATA buffer. This implementation eliminates the microcontroller overhead associated with the traditional firmware-based approach and results in increased data transfer rates. (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 11 All-in-OneMemory SST88VP1107 Fact Sheet 4.0 SYSTEM INTERFACE Figure 4-1 is a simplified interface diagram that shows how the All-in-OneMemory is connected to the host through a standard PSRAM bus interface. For a complete list of interface signals, and a detailed description of their functions, please see Table 2-1. 1.8V/3V VDDQ CLK WAIT RY/CRST# IRQ ADV# A[25:0] D[15:0] CE[4:0]# WE# OE# LB# UB# CRE NWP# HRST# VSSIO 1.8V VDDP 3V VDDN 3V VDD SST88VP1107 VREG 4.7F VSS 1354 F2-2.0 FIGURE 4-1: All-in-OneMemory System Interface Diagram (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 12 All-in-OneMemory SST88VP1107 Fact Sheet 5.0 PRODUCT ORDERING INFORMATION SST 88 XX VP XX 1107 - 80 XXXX - XX -5C -XX LBS E XXX X Environmental Attribute E1 = non-Pb (pure Sn) Package Modifier S = 80 balls Package Type LB = LBGA Operation Temperature C = Commercial: 0C to +70C W = Wireless: -25C to +85C Endurance 5 = 100,000 Cycles Frequency 80 = 80 MHz PSRAM Density 07 = 128 Mbit NAND Flash Density 11 = 2 Gbit Function/Core P = PSRAM Host Interface Voltage V = 2.7 - 3.6V Product Series 88 = All-in-OneMemory 1 Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". 5.1 Valid Combinations Valid combinations for SST88VP1107 SST88VP1107-80-5C-LBSE SST88VP1107-80-5W-LBSE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 13 All-in-OneMemory SST88VP1107 Fact Sheet 6.0 PACKAGE DIAGRAMS TOP VIEW 13.0 0.1 BOTTOM VIEW 9.0 1.0 0.50 0.05 (80X) 8 7 6 5 4 3 2 1 8 7 6 10.0 0.1 7.0 1.0 5 4 3 2 1 A A1 CORNER B C D E F G H J K K J H G F E D C B A A1 CORNER DETAIL VIEW 1.31 0.09 SIDE VIEW SEATING PLANE 0.15 0.40 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.15 mm 4. Ball opening size is 0.5 mm ( 0.05 mm) 80-lbga-LBS-10x13-0.0 FIGURE 6-1: 80-Ball Low-Profile Ball Grid Array (LBGA) 10mm x 13mm SST Package Code: LBS TABLE 00 6-1: Revision History Description Date Jul 2007 Number * Initial Release of Fact Sheet Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07 14 |
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