View XRK39351IQ_1151038.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

xr
NOVEMBER 2006
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
REV. 1.0.0
GENERAL DESCRIPTION
The XRK39351 is a low voltage PLL based clock driver designed for high speed clock distribution applications. The XRK39351 has two reference clock inputs, one LVPECL and the other LVCMOS. The REF_SEL input selects clock input to be used as the PLL's reference source. The XRK39351 uses PLL technology to frequency lock its outputs to the clock reference input. The divider in the feedback path will determine the frequency of the VCO. The XRK39351 provides 9 LVCMOS outputs that are separated into 4 banks. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK39351 to generate a variety of output-to-input frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All outputs provide LVCMOS compatible levels while driving 50 terminated transmission lines. The input reference clock can be directly applied to the output dividers bypassing the PLL when PLL_EN FIGURE 1. BLOCK DIAGRAM OF THE XRK39351
REF_SEL
input is pulled low. This is a test mode intended for system debug purposes. The XRK39351 has an output/input frequency range of 25MHz to 200MHz with the PLL enabled and an input frequency range of 2MHz to 300MHz when the PLL is disabled (test mode). FEATURES
* * * * * * * * *
9 LVCMOS Outputs (4 banks) 25 - 200 MHz output frequency range Fully Integrated PLL 2.5V or 3.3V Operation Selectable reference clock input, LVCMOS or LVPECL 150ps max output to output skew Pin compatible with MPC9351 Industrial temp range: -40C to +85C 32-Lead TQFP Packaging
/2 TCLK PECL PECL FB_IN
VDD
0 QA 1
1 Ref 0 FB
0 /4
PLL
1 0 QB 1
/8
PLL_EN SELA SELB SELC SELD
0 1
QC0 QC1 QD0
0 OE 1
QD1 QD2 QD3 QD4
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK39351CQ XRK39351IQ PACKAGE TYPE 32-Lead TQFP 32-Lead TQFP
OPERATING TEMPERATURE RANGE 0C to +70C -40C to +85C
FIGURE 2. PIN OUT OF THE XRK39351
REF_SEL
PLL_EN
VCCQB
TCLK
GND
32 AVCC FB_IN SELA SELB SELC SELD AGND PECL 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 QC0 VCCQC QC1 GND QD0 VCCQD QD1 GND
GND
QA
QB
XRK39351
21 20 19 18 17
10
11
12
13
14
15
16
VCCQD
PECL
GND
VCC
QD4
QD3
2
QD2
OE
rx
REV. 1.0.0
rx
REV. 1.0.0
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
PIN DESCRIPTIONS
NUMBER 1 2 3 4 5 6 7 8 9 10 11 12, 14, 16, 18, 20 13, 17, 21, 25, 29 15, 19 20, 22 23 26 27 28 30 31 32 NAME AVCC FB_IN SELA SELB SELC SELD AGND PECL PECL OE VCC QD[4:0] GND VCCQD QC[1:0] VCCQC QB VCCQB QA TCLK PLL_EN REF_SEL Power Input Input Input Input Input Power Input Input Input Power Output Power Power Output Power Output Power Output Input Input Input pull-down pull-up pull-down pull-down pull-down pull-down pull-down pull-down pull-down TYPE Power supply for PLL External PLL feedback clock input Selects divider value for Bank A output Selects divider value for Bank B output Selects divider value for Bank C outputs Selects divider value for Bank D outputs PLL ground LVPECL - pos differential reference clock LVPECL - neg differential reference clock Output enable/disable and device reset Power supply for core, inputs and bank A output clock Bank D clock outputs Ground Power supply for bank D output clocks Bank C clock outputs Power supply for bank C output clocks Bank B clock output Power supply for bank B output clock Bank A clock output LVCMOS reference clock input Selects PLL or PLL-bypass (test mode) operation Selects primary reference clock source DESCRIPTION
3
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER TABLE 1: CONTROL INPUT FUNCTION TABLE
PIN NAME REF_SEL PLL_EN SELA SELB SELC SELD OE 0 PECL clock inputs selected as reference PLL is bypassed. Test Mode. TCLK reference source drives the divider select blocks Bank A divider = 2 Bank B divider = 4 Bank C divider = 4 Bank D divider = 4 Outputs enabled 1 TCLK input selected as reference
PLL enabled. Normal operation. VCO output drives the divider select blocks Bank A divider = 4 Bank B divider = 8 Bank C divider = 8 Bank D divider = 8 Outputs tri-stated, VCO running at minimum frequency
DC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40C TO +85C)
SYMBOL VCMRa VPP VIH VIL VOH VOL CHARACTERISTICS PECL Clock inputs common mode range PECL Clock peak-to-peak input voltage Input voltage high Input voltage low Output High Voltagea Output Low Voltagea 2.4 0.55 0.30 14-17 +150 3.0 5.0 4 VCC/2 MIN 1.2 500 2.0 TYP MAX VCC-0.9 1000 VCC+0.3 0.8 UNIT V mV V V V V V mA mA V VIN =V CC or VIN =GND AVCC pin All VCCQX pins IOH=-24mA IOL=24mA IOL=12mA CONDITION
ZOUT IIN ICC_PLL ICC VTT
Output Impedance Input leakage current Maximum PLL supply current Maximum Quiescent supply current Output Termination Voltage
a. VCMR is the cross point of the differential input signal.
4
rx
REV. 1.0.0
DEFAULT 0 1 0 0 0 0 0
rx
REV. 1.0.0
.
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40C TO +85C) a
SYMBOL fVCO fref PARAMETER MIN 200 /2 feedback /4 feedback /8 feedback PLL Bypass /2 feedback /4 feedback /8 feedback 100 50 25 2 100 50 25 TYP MAX 400 200 100 50 300 200 100 50 1.0 25 75 UNIT MHz MHz PLL_EN PLL_EN PLL_EN PLL_EN =1 =1 =1 =0 CONDITION
VCO Frequency Input Reference Frequency
fMAX
Max Output Frequency
MHz
tir/tif frefDC tpd
Input Rise/Fall time Input Clock duty cycle Propagation Delay - (SPO, Input clock to FB) TCLK to FB_IN PECL to FB_IN Output-to-Output Skew Cycle-to-Cycle Jitter (RMS) Period Jitter (RMS) I/O Phase Jitter (RMS) PLL bandwidth /2 feedback /4 feedback /8 feedback /2 feedback /4 feedback /8 feedback 45 47.5 48.75 /4 feedback /4 feedback 10 8 4 - 17 9.0-20.0 3.0-9.5 1.2-2.1 50 50 50
ns %
0.8 to 2.0V
-50 -25
150 325 150 22 15
ps ps ps ps ps ps MHz MHz MHz
PLL Locked PLL Locked
tskew tJIT(CC) tJIT(PER) tJIT(I/O) BW
All outputs set to /4 All outputs set to /4
DC
Output duty cycle
55 52.5 51.75 1.0
% % % ms ps ns ns
100 - 200MHz 50 - 100MHz 25 - 50MHz
tLOCK tor/tof tPLZ,HZ tPHZ,LZ
Maximum PLL Lock Time Output Rise/Fall time Output Disable Time Output Enable Time 100
1000 10 10
0.55 to 2.4V
a. AC characteristics apply for parallel output termination of 50 to VTT.
5
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
DC CHARACTERISTICS (VCC= 2.5 + 5%, TA= -40C TO +85C)
SYMBOL VCMRa VPP VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT CHARACTERISTICS PECL Clock inputs common mode range PECL Clock peak-to-peak input voltage Input voltage high Input voltage low Output High Voltage Output Low Voltage Output Impedance Input leakage current Maximum PLL supply current Maximum Quiescent supply current Output Termination Voltage VCC/2 3.0 17-20 +150 5.0 1 1.8 0.6 MIN 1.2 500 1.7 TYP MAX VCC-0.6 1000 VCC+0.3 0.7 UNIT V mV V V V V mA mA V
IOH=-15mA IOL=15mA
VIN =VCC or VIN=GND AVCC pin All VCCQX pins
a. VCMR is the cross point of the differential input signal.
6
rx
REV. 1.0.0
CONDITION
rx
REV. 1.0.0
.
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
AC CHARACTERISTICS (VCC= 2.5 + 5%, TA= -40C TO +85C) a
SYMBOL fVCO fref PARAMETER MIN 200 /2 feedback /4 feedback /8 feedback PLL Bypass /2 feedback /4 feedback /8 feedback 100 50 25 TYP MAX 400 200 100 50 UNIT MHz MHz PLL_EN PLL_EN PLL_EN PLL_EN =1 =1 =1 =0 CONDITION
VCO Frequency Input Reference Frequency
fMAX
Max Output Frequency
100 50 25
200 100 50 1.0
MHz
tir/tif frefDC tpd
Input Rise/Fall time Input Clock duty cycle Propagation Delay - (SPO, Input clock to FB) TCLK to FB_IN PECL to FB_IN Output-to-Output Skew Cycle-to-Cycle Jitter (RMS) Period Jitter (RMS) I/O Phase Jitter (RMS) PLL bandwidth /2 feedback /4 feedback /8 feedback /2 feedback /4 feedback /8 feedback 45 47.5 48.75 /4 feedback /4 feedback 10 8 6 - 25 4.0-15.0 2.0-7.0 0.7-2.0 50 50 50 25
ns %
0.7 to 1.7V
75
-100 0
100 300 150 22 15
ps ps ps ps ps ps MHz MHz MHz
PLL Locked PLL Locked
tskew tJIT(CC) tJIT(PER) tJIT(I/O) BW
All outputs set to /4 All outputs set to /4
DC
Output duty cycle
55 52.5 51.75 1.0
% % % ms ps ns ns
100 - 200MHz 50 - 100MHz 25 - 50MHz
tLOCK tor/tof tPLZ,HZ tPHZ,LZ
Maximum PLL Lock Time Output Rise/Fall time Output Disable Time Output Enable Time 100
1000 12 12
0.6 to 1.8V
a. AC characteristics apply for parallel output termination of 50 to VTT.
7
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER ABSOLUTE MAXIMUM RATINGSa
SYMBOL VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -55
CHARACTERISTICS
MIN -0.3 -0.3 -0.3
MAX 4.6 VCC+0.3 VCC+0.3 +20 +50 150
UNIT V V V mA mA C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL VTT MM HBM LU CIN JA CHARACTERISTICS Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, multi layer test board JC Thermal resistance junction to case Operating junction temperature 200 2000 200 4.0 MIN TYP VCC/2 MAX UNIT V V V mA pF Inputs Natural convection 62.0 47 14 115 C/W C/W C/W C CONDITION
FIGURE 3. OUTPUT-TO-OUTPUT SKEW tSK(O)
VCC VCC/2 GND VCC VCC/2 GND tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device.
8
rx
REV. 1.0.0
CONDITION
rx
REV. 1.0.0
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
FIGURE 4. PROPOGATION DELAY (t(O), STATIC PHASE OFFSET) TEST REFERENCE
VCC CCLKx VCC/2 GND VCC FB_IN VCC/2 GND t(O)
FIGURE 5. OUTPUT DUTY CYCLE (DC)
VCC VCC/2 tp T0 DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
GND
FIGURE 6. I/O JITTER
CCLKx
FB_IN TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t 0 mean in a random sample of cycles
FIGURE 7. CYCLE-TO-CYCLE JITTER
TN
TN+1
TJIT(CC)= |TN-TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
9
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
FIGURE 8. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 9. OUTPUT TRANSITION TIME TEST REFERENCE
VCC=3.3V VCC=2.5V 2.4V 0.55V tof tor 1.8V 0.6V
10
rx
REV. 1.0.0
rx
REV. 1.0.0
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
PACKAGE DIMENSIONS
32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) rev. 2.00
D D1 24 17
25
16
D1 32 9
D
1 B A2 e
8
C A Seating Plane A1 L
Note: The control dimension is the millimeter column INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX
A A1 A2 B C D D1 e L
0.055 0.002 0.053 0.012 0.004 0.346 0.272
0.063 0.006 0.057 0.018 0.008 0.362 0.280
1.40 0.05 1.35 0.30 0.09 8.80 6.90
1.60 0.15 1.45 0.45 0.20 9.20 7.10
0.0315 BSC 0.018 0 0.030 7
0.80 BSC 0.45 0 0.75 7
11
XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REVISION HISTORY
REVISION # DATE DESCRIPTION
1.0.0
November 2006 Initial FINAL release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet November 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
12
rx
REV. 1.0.0

▲Up To Search▲

Price & Availability of XRK39351IQ

	To Download XRK39351IQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .