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PRELIMINARY
CY7C1051DV33
8-Mbit (512K x 16) Static RAM
Features
* High speed -- tAA = 10 ns * Low active power -- ICC = 110 mA @ 10 ns * Low CMOS standby power * * * * * -- ISB2 = 20 mA 2.0V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in lead-free 48-ball FBGA and 44-pin TSOP II packages
Functional Description[1]
The CY7C1051DV33 is a high-performance CMOS Static RAM organized as 512K words by 16 bits. Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from IO pins (IO0-IO7), is written into the location specified on the address pins (A0-A18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO8-IO15) is written into the location specified on the address pins (A0-A18). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0-IO7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the "Truth Table" on page 8 for a complete description of Read and Write modes. The input/output pins (IO0-IO15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation (CE LOW, and WE LOW) is in progress. The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
SENSE AMPS
512K x 16 ARRAY
IO0-IO7 IO8-IO15
COLUMN DECODER
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
BHE WE CE OE BLE
Note 1. For guidelines on SRAM system design, please refer to the "System Design Guidelines" Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-00063 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 9, 2007
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PRELIMINARY
CY7C1051DV33
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 110 20 Unit ns mA mA
Pin Configurations[2]
48-ball Mini FBGA
(Top View) 1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO10 IO 11 IO 12 IO 13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO 1 IO3 IO 4 IO 5 WE A11 6 NC IO 0 IO 2 VCC VSS IO 6 IO 7 NC A B C D E F G H
TSOP II
(Top View)
A0 A1 A2 A3 A4 CE IO 0 IO 1 IO 2 IO 3 VCC VSS IO 4 IO 5 IO 6 IO 7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE BHE BLE IO 15 IO 14 IO 13 IO 12 VSS VCC IO 11 IO 10 IO 9 IO 8 A18 A14 A13 A12 A11 A10
\
Note 2. NC pins are not connected on the die
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PRELIMINARY
CY7C1051DV33
Maximum Ratings
(Exceeding the maximum ratings may impair the useful life of the device. These are for user guidelines, they are not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND
[3]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
.... -0.5V to +4.6V
DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.3V to VCC + 0.3V DC Input Voltage[3] .................................-0.3V to VCC + 0.3V
DC Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL[3] IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power Down Max VCC, CE > VIH Current --TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power Down Max VCC, CE > VCC - 0.3V, Current --CMOS Inputs VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 110 100 90 80 40 20 mA mA Max Unit V V V V A A mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 12 12 Unit pF pF
Thermal Resistance[4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board FBGA Package 28.31 11.4 TSOP II Package 51.43 15.8 Unit C/W C/W
Notes 3. VIL (min) = -2.0V and VIH (max) = VCC + 2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters
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PRELIMINARY
AC Test Loads and Waveforms[5]
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V (a) High-Z Characteristics 3.3V OUTPUT 5 pF R2 351 (c) R 317 30 pF* GND
Rise Time: 1 V/ns
CY7C1051DV33
3.0V
ALL INPUT PULSES 90% 10% 90% 10%
Fall Time: 1 V/ns
(b)
AC Switching Characteristics[6] Over the Operating Range
Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE HIGH to High-Z[8, 9] 3 5 0 10 5 0 6 High-Z[8, 9] CE LOW to Low-Z[9] CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z 0 5 3 10 5 100 10 10 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -10 Min Max Unit
Notes 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads.Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device.
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PRELIMINARY
CY7C1051DV33
AC Switching Characteristics[6] Over the Operating Range (continued)
Parameter Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[8, 9] 7 Byte Enable to End of Write 10 7 7 0 0 7 5 0 3 5 ns ns ns ns ns ns ns ns ns ns ns Description -10 Min Max Unit
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR[4] tR[13] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Conditions[12] Min 2.0 20 0 tRC Max Unit V mA ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR
Notes 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. No inputs may exceed VCC + 0.3V 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document #: 001-00063 Rev. *C
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PRELIMINARY
CY7C1051DV33
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
IICC CC IISB SB
Notes 14. Device is continuously selected. OE, CE, BHE or BHE or both= VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW.
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PRELIMINARY
CY7C1051DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
Notes 17. Data I/O is high-impedance if OE or BHE or BLE or both = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-00063 Rev. *C
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PRELIMINARY
CY7C1051DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE
tHA
tLZWE
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1051DV33-10BAXI CY7C1051DV33-10ZSXI Package Diagram 51-85106 51-85087 Package Type 48-ball FBGA (Pb-Free) 44-pin TSOP II (Pb-Free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-00063 Rev. *C
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PRELIMINARY
CY7C1051DV33
Package Diagrams
Figure 1. 48-Ball FBGA (7.00 mm x 8.5 mm x 1.2 mm) (51-85106)
TOP VIEW BOTTOM VIEW
A1 CORNER O0.05 M C A1 CORNER O0.25 M C A B O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 0.75 8.500.10 8.500.10 5.25 D E F G H
A B C D E 2.625 F G H
A B 7.000.10
A
1.875 0.75 3.75 B 7.000.10
0.530.05
0.25 C
0.210.05
0.15(4X) 0.15 C
51-85106-*E
SEATING PLANE 0.36 C 1.20 MAX.
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PRELIMINARY
CY7C1051DV33
Package Diagrams (continued)
Figure 2. 44-pin TSOP II (51-85087)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1051DV33
Document History Page
Document Title: CY7C1051DV33 8-Mbit (512K x 16) Static RAM Document Number: 001-00063 REV. ** *A ECN NO. Issue Date 342195 380574 See ECN See ECN Orig. of Change PCI SYT New Data Sheet Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC (Ind'l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed the Description of IIX from Input Load Current to Input Leakage Current. Changed tHZBE from 5 ns to 6 ns Updated footnote #7 on High-Z parameter measurement Added footnote #11 Updated the Ordering Information table and Replaced Package Name column with Package Diagram. Changed ball E3 from VSS to NC in FBGA pin configuration Description of Change
*B
485796
See ECN
NXR
*C
866000
See ECN
NXR
Document #: 001-00063 Rev. *C
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