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PRELIMINARY
CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Features
* High speed -- tAA = 10 ns * Low active power -- ICC = 110 mA * Low CMOS standby power -- ISB2 = 20 mA * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features * Available in lead-free 36-ball FBGA and 44-pin TSOP II ZS44 packages
Functional Description[1]
The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1059DV33 is available in 36-ball FBGA and 44-pin TSOP II package with center power and ground (revolutionary) pinout.
Logic Block Diagram
I/O 0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10
ROW DECODER
I/O 1
SENSE AMPS
I/O 2 I/O 3 I/O 4 I/O 5
1M x 8 ARRAY
CE WE OE
COLUMN DECODER
POWER DOWN
I/O 6 I/O 7
Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-00061 Rev. *B
*
198 Champion Court
A19
A11 A12 A13 A14 A15 A16 A17 A18
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 21, 2006
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PRELIMINARY
Pin Configuration
CY7C1059DV33
36-ball FBGA (Top View)
1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 A18 CE A11 A17 A16 A12 A15 A13 2 A1 A2 3 NC WE A19 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 A B C D E F G H
NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
TSOP II Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 A19 NC NC
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 110 20 Unit ns mA mA
Document #: 001-00061 Rev. *B
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[2] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.3V to VCC + 0.3V
CY7C1059DV33
DC Input Voltage[2] ................................ -0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
Electrical Characteristics Over the Operating Range
-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-down Max. VCC, CE > VIH VIN > VIH Current --TTL Inputs or VIN < VIL, f = fMAX Automatic CE Power-down Max. VCC, CE > VCC - 0.3V, Current --CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 110 100 90 80 40 20 mA mA Max. Unit V V V V A A mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 16 16 Unit pF pF
Thermal Resistance[3]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board FBGA TBD TBD TSOP II TBD TBD Unit C/W C/W
Notes: 2. VIL (min.) = -2.0V and VIH (max.) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00061 Rev. *B
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PRELIMINARY
AC Test Loads and Waveforms[4]
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High-Z characteristics: 3.3V OUTPUT 5 pF (c) R2 351 1.5V (a) R 317 Rise Time: 1 V/ns (b) 30 pF* 3.0V 90% GND 10%
CY7C1059DV33
ALL INPUT PULSES 90% 10%
Fall Time: 1 V/ns
AC Switching
Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
Characteristics[5]
Over the Operating Range -10
Description VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[7, 8] CE LOW to Low-Z[8]
Min. 100 10
Max.
Unit s ns
10 3 10 5 0 5 3 5 0 10 10 7 7 0 0 7 5 0 3 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High-Z[7, 8] CE LOW to Power-up CE HIGH to Power-down Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z[7, 8]
Write Cycle[9, 10]
Notes: 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-00061 Rev. *B
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PRELIMINARY
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR[3] tR[12] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Conditions[11]
CY7C1059DV33
Min. 2.0
Max. 20
Unit V mA ns ns
0 tRC
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes: 11. No inputs may exceed VCC + 0.3V 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW.
Document #: 001-00061 Rev. *B
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PRELIMINARY
Switching Waveforms(continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
CY7C1059DV33
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (WE Controlled, OE LOW)[17]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 18 tHZWE
Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied.
tHA tPWE
tHD
DATA VALID tLZWE
Document #: 001-00061 Rev. *B
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PRELIMINARY
Truth Table
CE H L L L OE X L X H WE X H L H I/O0-I/O7 High-Z Data Out Data In High-Z Mode Power-down Read Write Selected, Outputs Disabled
CY7C1059DV33
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI Package Diagram 51-85105 51-85087 Package Type 36-ball FBGA (Pb-Free) 44-pin TSOP II (Pb-Free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
36-Ball FBGA (7.00 mm x 8.5 mm x 1.2 mm) (51-85105)
51-85105-*D
Document #: 001-00061 Rev. *B
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PRELIMINARY
Package Diagrams (continued)
44-pin TSOP II (51-85087)
CY7C1059DV33
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-00061 Rev. *B
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY7C1059DV33 8-Mbit (1M x 8) Static RAM Document Number: 001-00061 REV. ** *A ECN NO. Issue Date 342195 380574 See ECN See ECN Orig. of Change PCI SYT New Data Sheet
CY7C1059DV33
Description of Change Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC (Ind'l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Updated footnote #7 on High-Z parameter measurement Added footnote #11 Changed the Description of IIX from Input Load Current to Input Leakage Current. Updated the Ordering Information table and Replaced Package Name column with Package Diagram.
*B
485796
See ECN
NXR
Document #: 001-00061 Rev. *B
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