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| 3D3701 MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D3701) FEATURES * * * * * * * * All-silicon, low-power CMOS technology Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Frequency range: 0.3MHz through 100MHz Frequency tolerance: 0.5% typical Temperature stability: 1.5% typical (-40C to 85C) Vdd stability: 0.5% typical (3.0V to 3.6V) 14-pin DIP available as drop-in replacements for hybrid delay line oscillators O1 NC NC GND 1 2 3 4 8 7 6 5 PACKAGES VDD NC O2 EN O1 NC NC NC NC NC GND 3D3701-xx 3D3701K-xx 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD NC NC NC O2 NC EN 3D3701Z-xx SOIC-8 DIP-14 NC pins removed For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION The 3D3701 Delay Line Oscillator product family consists of fixedfrequency CMOS integrated circuit oscillators. Each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. The device frequency can range from 0.3MHz through 100MHz. The 3D3701 has two outputs that are in phase when the oscillator is running. The 3D3701 is offered in a standard 14-pin autoinsertable DIP and a space saving surface mount 8-pin SOIC package. PIN DESCRIPTIONS EN O1 O2 VDD GND Oscillator Enable Oscillator Output 1 Oscillator Output 2 +3.3 Volts Ground TABLE 1: PART NUMBER SPECIFICATIONS DASH NUMBER -0.3 -0.4 -0.5 -0.75 -1 -2 -2.5 -3 -4 -5 -7.5 -10 -20 -25 -30 -40 -50 -75 -100 NOTE: OUTPUT FREQUENCY (MHz) 25C -40C to 85C Vdd=3.3V 3.0V Doc #06026 12/5/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3701 APPLICATION NOTES OPERATIONAL DESCRIPTION The 3D3701 delay line oscillator architecture is shown in Figure 1. The internal delay line is composed of a number of delay cells connected in series and is compensated for thermal and supply voltage variations. A low-going edge on the EN input starts the oscillator, with the O2 output responding immediately. The O1 output is delayed by 1/2 cycle. The response of the output when the oscillator is disabled depends on the status of O2 when the EN signal goes high, as shown in Figure 2. If O2 is low, it will remain low, and the final pulse on O1 will be 1/2 of the period. If O2 is high, it will go low as soon as EN goes high, and the final pulse on both outputs will have a width smaller than 1/2 the period. VDD GND Temp & Vdd Compensation O1 Delay Line O2 EN Figure 1: 3D3701 Functional Diagram EN 6ns typ O2 O1 EN 6ns typ 6ns typ O2 O1 Figure 2: 3D3701 Timing Diagrams Doc #06026 12/5/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3701 APPLICATION NOTES (CONT'D) POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3701 oscillator utilizes novel and innovative compensation circuitry to minimize the frequency variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of 1.5% from the roomtemperature frequency setting. The power supply coefficient is reduced, over the 3.0V to 3.6V operating range, to 0.5% of the frequency setting at the nominal 3.3VDC power supply. These specifications hold for the lower frequencies only. For higher dash numbers, the variations will be slightly greater, as noted in Table 1. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 0.8 1.0 1.0 -4.0 TYP 3.5 MAX 5.5 UNITS mA V V A A mA mA 2.5 ns NOTES -20.0 4.0 15.0 2.0 VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/output (pf) F = Device frequency (GHz) Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max Doc #06026 12/5/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3701 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 3.3V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.5V (Rising & Falling) Device Under Test 10K 5pf Digital Scope 470 NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER O1 PULSE GENERATOR OUT TRIG EN DEVICE UNDER TEST (DUT) O2 REF IN TRIG FREQUENCY/ TIME INTERVAL COUNTER Figure 3: Test Setup tFALL EN 2.4V 1.5V 0.6V tRISE VIL 1/fOSC 1.5V 2.4VVIH 1.5V 0.6V tENB O2 1.5V tDIS 1.5V Figure 4: Timing Diagram Doc #06026 12/5/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 |
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