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74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs
October 2000 Revised June 2005
74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs
General Description
The LVTH162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH162373 is designed with equivalent 25: series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162373 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs include equivalent series resistance of 25: to make external termination resistors unnecessary and reduce overshoot and undershoot s Functionally compatible with the 74 series 16373 s Latch-up performance exceeds 500 mA s ESD performance:
Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
Ordering Code:
Order Number 74LVTH162373MEA 74LVTH162373MEX (Note 1) 74LVTH162373MTD 74LVTH162373MTX (Note 1) Package Number MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBES] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
(c) 2005 Fairchild Semiconductor Corporation
DS500354
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74LVTH162373
Connection Diagram
Pin Descriptions
Pin Names OEn LEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Latch Enable Input Inputs 3-STATE Outputs
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L
H L X Z Oo
Outputs I0-I7 X L H X O0-O7 Z L H Oo Outputs I8-I15 X L H X O8-O15 Z L H Oo
OE2 H L L L
HIGH Voltage Level LOW Voltage Level Immaterial HIGH Impedance Previous output prior to HIGH-to-LOW transition of LE
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
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74LVTH162373
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVTH162373
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI GND VO GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50
64 128
r64 r128 65 to 150
qC
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
12
12
40
0
85 10
qC
ns/V
't/'V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH VOL II(HOLD) II(OD) II Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH ICCH ICCL ICCZ Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 3.0 2.7 3.0 3.0 3.0 75 VCC 0.2 2.0 0.2 0.8 2.0 0.8 TA
40qC to 85qC
Max
Min
Units V V V V V II
Conditions
1.2
18 mA
VO d 0.1V or VO t VCC 0.1V IOH IOH IOL IOL VI VI
100 PA 12mA
100 PA 12 mA 0.8V 2.0V
75
500
PA PA
10
(Note 4) (Note 5) VI 5.5V 0V or VCC 0V VCC 0.5V to 3.0V GND or VCC 0.5V 3.0V VI VI VI
500 r1 5
1
PA
r100 r100 5
5 10 0.19 5 0.19
PA PA PA PA PA
mA mA mA
0V d VI or VO d 5.5V VO VI VO VO
VCC VO d 5.5V Outputs HIGH Outputs LOW Outputs Disabled
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74LVTH162373
DC Electrical Characteristics
Symbol ICCZ Parameter Power Supply Current Increase in Power Supply Current (Note 6)
(Continued)
VCC (V) 3.6 TA
40qC to 85qC
Max 0.19
Units mA
Conditions VCC d VO d 5.5V, Outputs Disabled One Input at VCC 0.6V Other Inputs at VCC or GND
Min
'ICC
3.6
0.2
mA
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 7)
TA 25qC Typ 0.8 Max Units V V CL Conditions 50 pF, RL (Note 8) (Note 8) 500:
Min
0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA Symbol Parameter VCC Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time, Dn to LE Hold Time, Dn to LE LE Pulse Width Output to Output Skew (Note 9) Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.3 1.4 1.7 1.4 1.6 1.0 1.6 1.8 1.0 1.0 3.0 1.0 1.0
40qC to 85qC, CL 50pF, RL 500:
3.3V r 0.3V Max 4.8 4.8 5.0 5.1 5.0 5.4 5.1 5.4 VCC Min 1.3 1.4 1.7 1.4 1.6 1.0 1.6 1.8 0.8 1.1 3.0 1.0 1.0 2.7V Max 5.3 5.1 5.1 5.8 6.0 6.6 5.0 5.7 ns ns ns ns ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance VCC VCC OPEN, VI 3.0V, VO Conditions 0V or VCC 0V or VCC Typical 4 8 Units pF pF
Note 10: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
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74LVTH162373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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