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500 MHz, Linear-in-dB VGA with AGC Detector AD8367
FEATURES
Broad-range analog variable gain: -2.5 dB to +42.5 dB 3 dB cutoff frequency of 500 MHz Gain up and gain down modes Linear-in-dB, scaled 20 mV/dB Resistive ground referenced input Nominal ZIN = 200 On-chip, square-law detector Single-supply operation: 2.7 V to 5.5 V
FUNCTIONAL BLOCK DIAGRAM
VPSI
12
VPSO
11
ENBL
2 14 ICOM
ICOM 1 INPT 3
AD8367
9-STAGE ATTENUATOR BY 5dB BIAS
9
DECL
13 HPFL
gm CELLS SQUARE LAW DETECTOR
10 VOUT
GAUSSIAN INTERPOLATOR ICOM 7
8 4 5 6
OCOM
02710-001
APPLICATIONS
Cellular base stations Broadband access Power amplifier control loops Complete, linear IF AGC amplifiers High speed data I/O
MODE
GAIN
DETO
Figure 1.
GENERAL DESCRIPTION
The AD8367 is a high performance 45 dB variable gain amplifier with linear-in-dB gain control for use from low frequencies up to several hundred megahertz. The range, flatness, and accuracy of the gain response are achieved using Analog Devices' X-AMP(R) architecture, the most recent in a series of powerful proprietary concepts for variable gain applications, which far surpasses what can be achieved using competing techniques. The input is applied to a 9-stage, 200 resistive ladder network. Each stage has 5 dB of loss, giving a total attenuation of 45 dB. At maximum gain, the first tap is selected; at progressively lower gains, the tap moves smoothly and continuously toward higher attenuation values. The attenuator is followed by a 42.5 dB fixed gain feedback amplifier--essentially an operational amplifier with a gain bandwidth product of 100 GHz--and is very linear, even at high frequencies. The output third order intercept is +20 dBV at 100 MHz (+27 dBm, re 200 ), measured at an output level of 1 V p-p with VS = 5 V. The analog gain-control input is scaled at 20 mV/dB and runs from 50 mV to 950 mV. This corresponds to a gain of -2.5 dB to +42.5 dB, respectively, when the gain up mode is selected and +42.5 dB to -2.5 dB, respectively, when gain down mode is selected. The gain down, or inverse, mode must be selected when operating in AGC in which an integrated square-law detector with an internal setpoint is used to level the output to 354 mV rms, regardless of the crest factor of the output signal. A single external capacitor sets up the loop averaging time. The AD8367 can be powered on or off by a voltage applied to the ENBL pin. When this voltage is at a logic LO, the total power dissipation drops to the milliwatt range. For a logic HI, the chip powers up rapidly to its normal quiescent current of 26 mA at 25C. The AD8367 is available in a 14-lead TSSOP package for the industrial temperature range of -40C to +85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD8367 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 Input Attenuator and Gain Control ......................................... 11 Input and Output Interfaces...................................................... 11 Power and Voltage Metrics........................................................ 12 Noise and Distortion.................................................................. 12 Output Centering ....................................................................... 12 RMS Detection ........................................................................... 13 Applications..................................................................................... 14 Input and Output Matching...................................................... 14 VGA Operation .......................................................................... 15 Modulated Gain Mode .............................................................. 15 AGC Operation .......................................................................... 15 Modifying the AGC Setpoint.................................................... 16 Evaluation Board ........................................................................ 19 Characterization Setup and Methods ...................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
7/05--Rev. 0 to Rev. A Changes to Format .............................................................Universal Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 3............................................................................ 6 Changes to Figure 8.......................................................................... 7 Changes to Figure 9, Figure 12, and Figure 14 ............................. 8 Changes to Input and Output Interfaces Section ....................... 11 Changes to Output Centering Section and Figure 31................ 12 Changes to RMS Detection Section ............................................. 13 Changes to Figure 32, Table 4, and Table 5 ................................. 14 Changes to Figure 33, Figure 34, and AGC Operation Section................................................................. 15 Changes to the Modifying the AGC Set Point Section.............. 16 Changes to Figure 38...................................................................... 17 Changes to Figure 42...................................................................... 19 Changes to Table 7.......................................................................... 20 Moved Table 7 to Page ................................................................... 20 Moved Characterization Setup and Methods Section to Page . 20 Moved Figure 45 to Page ............................................................... 20 Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 21 10/01--Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8367 SPECIFICATIONS
VS = 5 V, TA = 25C, system impedance ZO = 200 , VMODE = 5 V, f = 10 MHz, unless otherwise noted. Table 1.
Parameter OVERALL FUNCTION Frequency Range GAIN Range INPUT STAGE Maximum Input Input Resistance GAIN CONTROL INTERFACE Scaling Factor Gain Law Conformance Maximum Gain Minimum Gain VGAIN Step Response Small Signal Bandwidth OUTPUT STAGE Maximum Output Voltage Swing Output Source Resistance Output Centering Voltage 1 SQUARE LAW DETECTOR Output Set Point AGC Small Signal Response Time POWER INTERFACE Supply Voltage Total Supply Current Disable Current vs. Temperature MODE CONTROL INTERFACE Mode LO Threshold Mode HI Threshold ENABLE INTERFACE Enable Threshold Enable Response Time Enable Input Bias Current f = 70 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point Conditions Min LF 45 Pins INPT and ICOM To avoid input overload From INPT to ICOM Pin GAIN VMODE = 5 V, 50 mV VGAIN 950 mV VMODE = 0 V, 50 mV VGAIN 950 mV 100 mV VGAIN 900 mV VGAIN = 0.95 V VGAIN = 0.05 V From 0 dB to 30 dB From 30 dB to 0 dB VGAIN = 0.5 V Pin VOUT RL = 1 k RL = 200 Series resistance of output buffer Pin DETO CAGC = 100 pF, 6 dB gain step Pins VPSI, VPSO, ICOM, and OCOM 2.7 ENBL high, maximum gain, RL = 200 (includes load current) ENBL low -40C TA +85C Pin MODE Device in negative slope mode of operation Device in positive slope mode of operation Pin ENBL Time delay following LO to HI transition until device meets full specifications. ENBL at 5 V ENBL at 0 V Maximum gain Minimum gain 26 1.3 354 1 5.5 30 1.6 1.8 mV rms s V mA mA mA V V V s A nA dB dB mV/dB dB dB dBm dBV rms dBm dBV rms 700 200 +20 -20 0.2 +42.5 -2.5 300 300 5 4.3 3.5 50 VS/2 Typ Max 500 Unit MHz dB mV p-p mV/dB mV/dB dB dB dB ns ns MHz V p-p V p-p V
175
225
1.2 1.4 2.5 1.5 27 32 +42.5 -3.7 19.9 -5.6 6.2 36.5 29.5 8.5 1.5
Maximum gain f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V VGAIN = 0.5 V
Rev. A | Page 3 of 24
AD8367
Parameter f = 140 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 190 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 240 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point Conditions Maximum gain Minimum gain Min Typ +43.5 -3.6 19.7 -5.3 7.4 32.7 25.7 8.4 1.4 +43.5 -3.8 19.6 -5.3 7.5 30.9 23.9 8.4 1.4 +43 -4.1 19.7 -5.2 7.6 29.2 22.2 8.1 1.1 Max Unit dB dB mV/dB dB dB dBm dBV rms dBm dBV rms dB dB mV/dB dB dB dBm dBV rms dBm dBV rms dB dB mV/dB dB dB dBm dBV rms dBm dBV rms
Maximum gain f1 = 140 MHz, f2 = 141 MHz, VGAIN = 0.5 V VGAIN = 0.5 V
Maximum gain Minimum gain
Maximum gain f1 = 190 MHz, f2 = 191 MHz, VGAIN = 0.5 V VGAIN = 0.5 V
Maximum gain Minimum gain
Maximum gain f1 = 240 MHz, f2 = 241 MHz, VGAIN = 0.5 V VGAIN = 0.5 V
1
The output dc centering voltage is normally set at VS/2 and can be adjusted by applying a voltage to DECL.
Rev. A | Page 4 of 24
AD8367 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VPSO, VPSI ENBL Voltage MODE Select Voltage VGAIN Control Voltage Input Voltage Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V VS + 200 mV VS + 200 mV 1.2 V 600 mV 250 mW 150C/W 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 24
AD8367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ICOM 1 ENBL 2 INPT 3 MODE 4 DETO 6 ICOM 7
14 13
ICOM HPFL VPSI
AD8367
12
11 VPSO TOP VIEW GAIN 5 (Not to Scale) 10 VOUT
02710-002
9 8
DECL OCOM
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 7, 14 2 3 4 5 6 8 9 10 11 12 13 Mnemonic ICOM ENBL INPT MODE GAIN DETO OCOM DECL VOUT VPSO VPSI HPFL Description Signal Common. Connect to low impedance ground. A HI Activates the Device. Signal Input. 200 to ground. Gain Direction Control. HI for positive slope; LO for negative slope. Gain Control Voltage Input. Detector Output. Provides output current for RSSI function and AGC control. Power Common. Connect to low impedance ground. Output Centering Loop Decoupling Pin. Signal Output. To be externally ac-coupled to load. Positive Supply Voltage. 2.7 V to 5.5 V. VPSI and VPSO are tied together internally with back-to-back PN junctions. They should be tied together externally and properly bypassed. Positive Supply Voltage. 2.7 V to 5.5 V. High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop.
Rev. A | Page 6 of 24
AD8367 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25C, system impedance ZO = 200 , VMODE = 5 V, unless otherwise noted.
50 1V 0.9V 0.8V 30
GAIN (dB)
10 +85C 9 +25C
NOISE FIGURE (dB)
40
0.7V 0.6V
8 -40C 7
20
0.5V 0.4V
10
0.3V 0.2V
6
0
0.1V
02710-003
5
02710-006
-10 10
100 FREQUENCY (MHz)
1000
4 70
90
110
130
150
170
190
210
230
250
FREQUENCY (MHz)
Figure 3. Gain vs. Frequency for Values of VGAIN
45 40 35
Figure 6. NF (re 200 ) vs. Frequency at Maximum Gain
60
50
NOISE FIGURE (dB)
02710-004
30 GAIN (dB) 25 20 15 10 5 0 -5 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0 MODE = 5V 10MHz 70MHz 140MHz 240MHz MODE = 0V 10MHz 70MHz 140MHz 240MHz
40
30
20
10
02710-007
0 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9
1.0
Figure 4. Gain vs. VGAIN (Mode LO and Mode HI)
45 40 35 30 -40C 2.0 1.6 1.2 0.8 0.4 +25C +85C 15 10 5 0 -5 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 -0.4 -0.8 -1.2 -1.6 -2.0 1.0
02710-005
Figure 7. NF (re 200 ) vs. VGAIN at 70 MHz
40 35 30 25 20 15 10
02710-008
70MHz
10MHz
LINEARITY ERROR (dB)
140MHz 240MHz
20
0
OIP3 (dBm)
GAIN (dB)
25
5 0 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0
Figure 5. Gain Conformance at 70 MHz for T = -40C, +25C, and +85C
Figure 8. OIP3 vs. VGAIN
Rev. A | Page 7 of 24
AD8367
40 33 0 -10 35 28 -20
OIP3 (dBV rms)
30
23
OUTPUT IMD3 (dBc)
OIP3 (dBm re 200)
-30 -40 240MHz -50 10MHz -60 70MHz 140MHz
25
18
20
13
15
8
02710-009 02710-012
-70 -80 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9
10 10
100 FREQUENCY (MHz)
3 1000
1.0
Figure 9. OIP3 vs. Frequency for VGAIN = 500 mV
4
OUTPUT 1dB COMPRESSION (dBV rms)
Figure 12. IMD3 vs. Gain (VOUT = 1 V p-p Composite)
11
OUTPUT 1dB COMPRESSION (dBm re 200) OUTPUT 1dB COMPRESSION (dBV rms)
2 140MHz 0 200MHz -2
9
2
9
7
0
7
5
-2
5
-4
3
-4
3
-6
1
-6
1
02710-010
OUTPUT 1dB COMPRESSION (dBm re 200)
10MHz 70MHz
4
11
-8 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9
-1 1.0
-8 2.5
3.0
3.5
4.0 VS (V)
4.5
5.0
-1 5.5
Figure 10. Output P1dB vs. VGAIN
Figure 13. Output Compression Point vs. Supply Voltage at 70 MHz, VGAIN = 500 mV
12 11 10 9 8 7 6 5 4 3 2 1000
OUTPUT 1dB COMPRESSION (dBm re 200)
5
OUTPUT 1dB COMPRESSION (dBV rms)
40 35
OUTPUT IP3 (dBm re 200)
33 28 23 18 13 8 3
02710-014
4 3 2 1 0 -1 -2 -3 -4 -5 10
25 20 15 10 5 0 2.5
02710-011
-2 -7 5.5
100 FREQUENCY (MHz)
3.0
3.5
4.0 VS (V)
4.5
5.0
Figure 11. Output P1dB vs. Frequency at VGAIN = 500 mV
Figure 14. Output Third-Order Intercept vs. Supply Voltage at 70 MHz, VGAIN = 500 mV
Rev. A | Page 8 of 24
OUTPUT IP3 (dBV rms)
30
02710-013
AD8367
250 0
120 90 60
200
-25
SERIES REACTANCE ()
RESISTANCE ()
150 500mV 180 700mV 300mV
30
150
-47
100
-73
0
50
-95
02710-015
210
330
0 0 100 200 300 400 FREQUENCY (MHz)
-120 500
240
300 270
02710-018
Figure 15. Input Resistance and Series Reactance vs. Frequency at VGAIN = 500 mV
90 120 60
Figure 18. Output Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN
0.5
VGAIN
0.4
150
30
0.3
VOUT
0.2
180 0
V (V)
0.1 0
210
300mV 500mV 700mV 240 300
330
-0.1
02710-019
-0.2
02710-016
-0.3 TIME (200ns/DIV)
270
Figure 16. Input Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN
70 20
25
Figure 19. AGA Time Domain Response (3 dB Steps)
65
15
SERIES REACTANCE ()
20 10nF
RESISTANCE ()
60
10
GAIN (dB)
15 1nF 10pF 10 100pF
55
5
50
0
45
-5
02710-017
5 NO CAP 0 0.1 1 10 100 1k 10k
02710-020
40 0 100 200 300 400 FREQUENCY (MHz)
-10 500
100k
FREQUENCY (kHz)
Figure 17. Output Resistance and Series Reactance vs. Frequency at VGAIN = 500 mV
Figure 20. Gain vs. Frequency for Multiple Values of HPFL Capacitor at VGAIN = 500 mV
Rev. A | Page 9 of 24
AD8367
1.0 0.9 0.8 0.7
RSSI (V)
2.0 1.5 140MHz 10MHz 70MHz 140MHz 240MHz 1.0 0.5 0 240MHz 10MHz -0.5 -1.0 -1.5 -2.0
02710-021
0.8
VAGC
LINEARITY ERROR (dB)
70MHz
0.7 CAGC = 100pF
0.6 0.5 0.4 0.3 0.2 0.1 0 -60
V (V)
0.6
VOUT
0.5
02710-024
-2.5 -3.0 -50 -40 -30 -20 -10 0 INPUT LEVEL (dBV rms)
0.4 -2-5
-1-5
0 TIME (Seconds)
1-5
2-5
Figure 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz
1.0 0.9 0.8 0.7
RSSI (V)
Figure 24. AGC Time Domain Response (3 dB Step)
2.0 +25C -40C +85C +85C +25C 1.5 1.0 0.5 0 -0.5 -40C -1.0 -1.5 -2.0 -2.5 -3.0 -50 -40 -30 -20 -10 0 INPUT LEVEL (dBV rms)
02710-022
0.6 0.5 0.4 0.3 0.2 0.1 0 -60
LINEARITY ERROR (dB)
19.0097
19.7297
19.9097
20.0897
20.2697
GAIN SCALING (mV/dB)
Figure 22. AGC RSSI (Voltage on DETO Pin) vs. Input Power over Temperature at 70 MHz
1.0 0.9 0.8 0.7
WCDMA 256QAM 64QAM 16QAM SINE
Figure 25. Gain Scaling Distribution at 70 MHz
2.5 2.0 1.5 1.0 0.5 0 -0.5
RSSI (V)
0.6 0.5 0.4 0.3 0.2 0.1 0 -60
IS95FWD
-1.0 -1.5
-2.5 -50 -40 -30 -20 -10 0 INPUT LEVEL (dBV rms)
-6.4
-6.2
-6.0
-5.8
-5.6
-5.4
-5.2
-5.0
-4.8
INTERCEPT (dB)
Figure 23. AGC RSSI (Voltage on DETO Pin) vs. Input Power for Various Modulation Schemes
Figure 26. Gain Intercept Distribution at 70 MHz
Rev. A | Page 10 of 24
02710-026
-2.0
02710-023
LINEARITY ERROR (dB)
02710-025
AD8367 THEORY OF OPERATION
The AD8367 is a variable gain, single-ended, IF amplifier based on Analog Devices' patented X-AMP architecture. It offers accurate gain control with a 45 dB span and a 3 dB bandwidth of 500 MHz. It can be configured as a traditional VGA with 50 dB/V gain scaling or as an AGC amplifier by using the built in rms detector. Figure 27 is a simplified block diagram of the amplifier. The main signal path consists of a voltage controlled 0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed gain amplifier. The AD8367 is designed to operate optimally in a 200 impedance system.
INTEGRATOR GAIN gm GAIN INTERPOLATOR gm gm -10dB gm -45dB VOUT -42.5dB OUTPUT BUFFER VOUT
deviation from Equation 1, that is, the gain conformance error, is also illustrated in Figure 28. The ripples in the error are a result of the interpolation action between tap points. The AD8367 provides better than 0.5 dB of conformance error over >40 dB gain range at 200 MHz and 1 dB at 400 MHz.
44 40 LO MODE 36 32 28 50dB/V GAIN SLOPE 2.0 1.6 1.2
0.4 0 -0.4 -0.8 -1.2 -1.6 HI MODE
24 20 16 12 8 4
0dB -5dB INPT 200
02710-027
0 -2.4 -4 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0
ATTENUATOR LADDER
Figure 27. Simplified Architecture
INPUT ATTENUATOR AND GAIN CONTROL
The variable attenuator consists of a 200 single-ended resistive ladder that comprises of nine 5 dB sections and an interpolator that selects the attenuation factor. Each tap point down the ladder network further attenuates the input signal by a fixed decibel factor. Gain control is achieved by sensing different tap points with variable transconductance stages. Based on the gain control voltage, an interpolator selects which stage(s) are active. For example, if only the first stage is active, the 0 dB tap point is sensed; if the last stage is active, the 45 dB tap point is sensed. Attenuation levels that fall between tap points are achieved by having neighboring gm stages active simultaneously, creating a weighted average of the discrete tap point attenuations. In this way, a smooth, monotonic attenuation function is synthesized, that is, linear-in-dB with a very precise scaling. The gain of the AD8367 can be an increasing or decreasing function of the control voltage, VGAIN, depending on whether the MODE pin is pulled up to the positive supply or down to ground. When the MODE pin is high, the gain increases with VGAIN, as shown in Figure 28. The ideal linear-in-dB scaled transfer function is given by Gain (dB) = 50 x VGAIN - 5 where VGAIN is expressed in volts. Equation 1 contains the gain scaling factor of 50 dB/V (20 mV/dB) and the gain intercept of -5 dB, which represents the extrapolated gain for VGAIN = 0 V. The gain ranges from -2.5 dB to +42.5 dB for VGAIN ranging from 50 mV to 950 mV. The (1)
Figure 28. The gain function can be either an increasing or decreasing function of VGAIN, depending on the MODE pin.
The gain is a decreasing function of VGAIN when the MODE pin is low. Figure 28 also illustrates this mode, which is described by Gain (dB) = 45 - 50 x VGAIN (2)
This gain mode is required in AGC applications using the builtin, square-law level detector.
INPUT AND OUTPUT INTERFACES
The AD8367 was designed to operate best in a 200 impedance system. Its gain range, conformance law, noise, and distortion assume that 200 source and load impedances are used. Interfacing the AD8367 to other common impedances (from 50 used at radio frequencies to 1 k presented by data converters) can be accomplished using resistive or reactive passive networks, whose design depends on specific system requirements, such as bandwidth, return loss, noise figure, and absolute gain range. The input impedance of the AD8367 is nominally 200 , determined by the resistive ladder network. This presents a 200 dc resistance to ground, and, in cases where an elevated signal potential is used, ac coupling is necessary. The input signal level must not exceed 700 mV p-p to avoid overloading the input stage. The output impedance is determined by an internal 50 damping resistor, as shown in Figure 29. Despite the fact that the output impedance is 50 , the AD8367 should still be presented with a load of 200 . This implies that the load is mismatched, but doing so preserves the distortion performance of the amplifier.
Rev. A | Page 11 of 24
02710-028
-2.0
LINEARITY ERROR (dB)
0.8
GAIN (dB)
AD8367
60 50 VB1 FROM INTEGRATOR VB2
02710-029
60 50 NF 40 30 20 IIP3 10 0 -10 -20 -30 1.0
02710-030
50
40 VOUT 30
IIP3 (dBV)
20 10 0 -10
Figure 29. A 50 resistor is added to the output to prevent package resonance.
POWER AND VOLTAGE METRICS
Although power is the traditional metric used in the analysis of cascaded systems, most active circuit blocks fundamentally respond to voltage. The relationship between power and voltage is defined by the impedance level. When input and output impedance levels are the same, power gain and voltage gain are identical. However, when impedance levels change between input and output, they differ. Thus, one must be very careful to use the appropriate gain for system chain analyses. Quantities such as OIP3 are quoted in dBV rms as well as dBm referenced to 200 . The dBV rms unit is defined as decibels relative to 1 V rms. In a 200 environment, the conversion from dBV rms to dBm requires the addition of 7 dB to the dBV rms value. For example, a 2 dBV rms level corresponds to 9 dBm.
-20 -30 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9
Figure 30. Noise Figure and Input Third-Order Intercept vs. Gain (RSOURCE = 200 )
OUTPUT CENTERING
To maximize the ac swing at the output of the AD8367, the output level is centered midway between ground and the supply. This is achieved when the DECL pin is bypassed to ground via a shunt capacitor. The loop acts to suppress deviations from the reference at outputs below its corner frequency while not affecting signals above it, as shown in Figure 31. The maximum corner frequency with no external capacitor is 500 kHz. The corner frequency can be lowered arbitrarily by adding an external capacitor, CHP:
NOISE AND DISTORTION
Since the AD8367 consists of a passive variable attenuator followed by a fixed gain amplifier, the noise and distortion characteristics as a function of the gain voltage are easily predicted. The input-referred noise increases in proportion to the attenuation level. Figure 30 shows noise figure, NF, as a function of VGAIN for the MODE pin pulled high. The minimum NF of 7.5 dB occurs at maximum gain and increases 1 dB for every 1 dB reduction in gain. In receiver applications, the minimum NF should occur at the maximum gain where the received signal presumably is weak. At higher levels, a lower gain is needed, and the increased NF becomes less important. The input-referred distortion varies in a similar manner to the noise. Figure 30 illustrates how the third-order intercept point at the input, IIP3, behaves as a function of VGAIN. The highest IIP3 of 20 dBV rms (27 dBm re 200 ) occurs at minimum gain. The IIP3 then decreases 1 dB for every 1 dB increase in gain. At lower levels, a degraded IIP3 is acceptable. Overall, the dynamic range, represented by the difference between IIP3 and NF, remains reasonably constant as a function of gain. The output distortion and compression are essentially independent of the gain. At low gains, when the input level is high, input overload can occur, causing premature distortion.
f HP (kHz) =
10 C HP (nF) + 0.02
A 100 in series with the CHP capacitor is recommended to de-Q the resonant tank that is formed by the bond-wire inductance and CHP. Failure to insert this capacitor can potentially cause oscillations at higher frequencies at high gain settings.
MAIN AMPLIFIER FROM INPUT gm HPFL CHP RHP DECL VMID AV = 1
02710-031
VOUT
Figure 31. The dc output level is centered to midsupply by a control loop whose corner frequency is determined by CHP.
Rev. A | Page 12 of 24
NF (dB)
(3)
AD8367
RMS DETECTION
The AD8367 contains a square-law detector that senses the output signal and compares it to a calibrated setpoint of 354 mV rms, which corresponds to a 1 V p-p sine wave. This setpoint is internally set and cannot be modified to change the AGC setpoint and the resulting VOUT level without using additional external components. This is described in the Modifying the AGC Setpoint section. Any difference between the output and setpoint generates a current that is integrated by an external capacitor, CAGC, connected from the DETO pin to ground, to provide an AGC control voltage. There is also an internal 5 pF capacitor on the DETO pin. The resulting voltage is used as an AGC bias. For this application, the MODE pin is pulled low and the DETO pin is tied to the GAIN pin. The output signal level is then regulated to 354 mV rms. The AGC bias represents a calibrated rms measure of the received signal strength (RSSI). Since in AGC mode the output signal is forced to the 354 mV rms setpoint (-9.02 dBV rms), Equation 2 can be recast to express the strength of the received signal, VIN-RMS, in terms of the AGC bias VDETO. VIN - RMS (dBV rms) = 54.02 + 50 x VDETO where -54.02 dBV rms = -45 dB - 9.02 dBV rms. For small changes in input signal level, VDETO responds with a characteristic single-pole time constant, AGC, which is proportional to CAGC. AGC (s) = 10 x CAGC (nf) where the internal 5 pF capacitor is lumped with the external capacitor to give CAGC. (5) (4)
Rev. A | Page 13 of 24
AD8367 APPLICATIONS
The AD8367 can be configured either as a VGA whose gain is controlled externally through the GAIN pin or as an AGC amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply to the VPSO and VPSI pins should be decoupled using a low inductance, 0.1 F surface-mount, ceramic capacitor as close as possible to the device. Additional supply decoupling can be provided by a small series resistor. A 10 nF capacitor from Pin DECL to Pin OCOM is recommended to decouple the output reference voltage. Minimum-loss, L-pad networks are used on the evaluation board (see Figure 45) to allow easy interfacing to standard 50 test equipment. Each pad introduces an 11.5 dB power loss (5.5 dB voltage loss).
1
0.3333
3
INPUT AND OUTPUT MATCHING
The AD8367 is designed to operate in a 200 impedance system. The output amplifier is a low output impedance voltage buffer with a 50 damping resistor to desensitize it from load reactance and parasitics. The quoted performance includes the voltage division between the 50 resistor and the 200 load. The AD8367 can be reactively matched to an impedance other than 200 by using traditional step-up and step down matching networks or high quality transformers. Table 4 lists the 50 S-parameters for the AD8367 at a VGAIN = 750 mV. Figure 32 illustrates an example where the AD8367 is matched to 50 at 140 MHz. As shown in the Smith Chart, the input matching network shifts the input impedance from ZIN to 50 with an insertion loss of <2 dB over a 5 MHz bandwidth. For the output network, the 50 load is made to present 200 to the AD8367 output. Table 5 provides the component values required for 50 matching at several frequencies of interest. When added loss and noise can be tolerated, a resistive pad can be used to provide broadband, near-matched impedances at the device terminals and the terminations.
RSOURCE 0.3333 1 3 ZIN SERIES L SHUNT C
-0.3333
-3
-1 fC = 140MHz, ZIN = 197 - j34.2, RSOURCE = 50 XSIN 100nH RSOURCE 50 VS ZIN XPIN 8.2pF ZIN
AD8367
ZOUT
CAC 0.1F
XSOUT 13pF
ZLOAD XPOUT 120nH
02710-032
RLOAD 50
Figure 32. Reactive Matching Example for f = 140 MHz
Table 4. S-Parameters for 200 System for VS = 5 V and VGAIN = 0.75 V
Frequency (MHz) 10 70 140 190 240 S11 0.04 -43.8 0.09 -81.5 0.17 -103.4 0.21 -111.7 0.26 -103.8 S21 41.1 178.8 43.6 163.4 48.0 141.4 47.5 124.0 48.3 107.6 S12 0.0003 76.1 0.0002 63.7 0.0009 130.8 0.0017 96.8 0.0018 113.5 S22 0.56 -179.3 0.55 +176.1 0.56 +170.2 0.54 +166.5 0.48 +164.6
Table 5. Reactive Matching Components for a 50 System where RSOURCE = 50 , RLOAD = 50
Frequency (MHz) 10 70 140 190 240 XSIN 1.5 H 220 nH 100 nH 82 nH 68 nH XPIN (pF) 120 15 8.2 2.7 1.5 XSOUT (pF) 180 27 13 10 7 XPOUT 1.8 H 270 nH 120 nH 100 nH 82 nH
Rev. A | Page 14 of 24
AD8367
VGA OPERATION
The AD8367 is a general-purpose VGA suitable for use in a wide variety of applications where voltage control of gain is needed. While having a 500 MHz bandwidth, its use is not limited to high frequency signal processing. Its accurate, temperature- and supply-stable linear-in-dB scaling is valuable wherever it is important to have a more dependable response to the control voltage than is usually offered by VGAs of this sort. For example, there is no preclusion to its use in speech-bandwidth systems. Figure 33 shows the basic connections. The CHP capacitor at Pin HPFL can be used to alter the high-pass corner frequency of the signal path and is associated with the offset control loop that eliminates the inherent variation in the internal dc balance of the signal path as the gain is varied (offset ripple). This frequency should be chosen to be about a decade below the lowest frequency component of the signal. If made much lower than necessary, the offset loop is not able to track the variations that occur when there are rapid changes in VGAIN. The control of offset is important even when the output is ac-coupled because of the potential reduction of the upper and lower voltage range at this pin. However, in many applications these components are unnecessary because an internal network provides a default high-pass corner of about 500 kHz. For CHP = 1 nF, the modified corner is at ~10 kHz; it scales downward with increasing capacitance. Figure 20 shows representative response curves for the indicated component values.
C1 1F CHP R HP 10nF 100 VP R6 4.7 C2 0.1F R5 4.7 C3 0.1F
1 2
AGC OPERATION
The AD8367 can be used as an AGC amplifier, as shown in Figure 34. For this application, the accurate internal, square-law detector is employed. The output of this detector is a current that varies in polarity, depending on whether the rms value of the output is greater or less than its internally-determined setpoint of 354 mV rms. This is 1 V p-p for sine-wave signals, but the peak amplitude for other signals, such as Gaussian noise, or those carrying complex modulation, is invariably somewhat greater. However, for all waveforms having a crest factor of <5, and when using a supply voltage of 4.5 V to 5.5 V, the rms value is correctly measured and delivered at VOUT. When using lower supplies, the rms value of VOUT is unaffected (the setpoint is determined by a band gap reference), but the peak crest factor capacity is reduced. The gain pin is connected to the base of a transistor internally and thus requires only 1 A of current drive. The output of the detector is delivered to Pin DETO. The detector can source up to 60 A and can sink up to 11 A. For a sine-wave output signal, and under conditions where the AGC loop is settled, the detector output also takes the form of a sine-wave, but at twice the frequency and having a mean value of 0. If the input to the amplifier increases, the mean of this current also increases and charges the external loop filter capacitor, CAGC, toward more positive voltages. Conversely, a reduction in VOUT below the setpoint of 354 mV rms causes this voltage to fall toward ground. The capacitor voltage is the AGC bias; this can be used as a received signal strength indicator (RSSI) output and is scaled exactly as VGAIN, that is, 20 mV/dB.
C1 1F CHP R HP 10nF 100 VP R6 4.7 C2 0.1F R5 4.7 C3 0.1F
AD8367
1 2
ICOM ENBL INPT MODE GAIN DETO ICOM
ICOM 14 HPFL 13 VPSI 12 VPSO 11 VOUT 10 DECL 9 OCOM 8
AD8367
ICOM ENBL INPT MODE GAIN DETO ICOM ICOM 14 HPFL 13 VPSI 12 VPSO 11 VOUT 10 DECL 9 OCOM 8
VIN
3 4
VGAIN
5 6 7
VOUT
02710-033
VIN
3 4
C5 10nF
C4 0.1F
VAGC CAGC 0.1F
5 6 7
VOUT
02710-034
C4 0.1F C5 10nF
Figure 33. Basic Connections for Voltage Controlled Gain Mode
MODULATED GAIN MODE
The AD8367 can be used as a means of modulating the signal level. Keep in mind, however, that the gain is a nonlinear (exponential) function of VGAIN; thus, it is not suitable for normal amplitude-modulation functions. The small signal bandwidth of the gain interface is ~5 MHz, and the slew rate is of the order of 500 dB/s. During gain slewing from close to minimum to maximum gain (or vice versa), the internal interpolation processes in an X-AMP-based VGA rapidly scan the full range of gain values. The gain and offset ripple associated with this process can cause transient disturbances in the output. Therefore, it is inadvisable to use high amplitude pulse drives with rise and fall times below 200 ns.
Figure 34. Basic Connections for AGC Operation
A valuable feature of using a square law detector is that the RSSI voltage is a true reflection of signal power and can be converted to an absolute power measurement for any given source impedance. The AD8367 can thus be employed as a true-power meter, or decibel-reading ac voltmeter, as distinct from its basic amplifier function. The AGC mode of operation requires that the correct gain direction is chosen. Specifically, the gain must fall as VAGC increases to restore the needed balance against the setpoint. Therefore, the MODE pin must be pulled low. This accurate leveling function is shown in Figure 35, where the rms output is
Rev. A | Page 15 of 24
AD8367
held to within 0.1 dB of the setpoint for >35 dB range of input levels. The dynamics of this loop are controlled by CAGC acting in conjunction with an on-chip equivalent resistance, RAGC, of 10 k which form an effective time-constant TAGC = RAGC CAGC. The loop thus operates as a single-pole system with a loop bandwidth of 1/(2 TAGC). Because the gain control function is linear in decibels, this bandwidth is independent of the absolute signal level. Figure 36 illustrates the loop dynamics for a 30 dB change in input signal level with CAGC = 100 pF.
-1.2 -1.3 -1.4
Most AGC loops incorporating a true error-integrating technique have a common weakness. When driven from an increasingly larger signal, the AGC bias increases to reduce the gain. However, eventually the gain falls to its minimum value, for which further increase in this bias has no effect on the gain. That is, the voltage on the loop capacitor is forced progressively higher because the detector output is a current, and the AGC bias is its integral. Consequently, there is always a precipitous increase in this bias voltage when the input to the AD8367 exceeds that value that overdrives the detector, and because the minimum gain is -2.5 dB, that happens for all inputs 2.5 dB greater than the setpoint of ~350 mV rms. If possible, the user should ensure that this limitation is preserved, preferably with a guard-band of 5 dB to 10 dB below overload In some cases, if driven into AGC overload, the AD8367 requires unusually long times to recover; that is, the voltage at DETO remains at an abnormally high value and the gain is at its lowest value. To avoid this situation, it is recommended that a clamp be placed on the DETO pin, as shown in Figure 37.
1
POUT (dBm re 200)
-1.5 -1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -50
02710-035
AD8367
14 13 12
2
+VS RB 0.5V RA VAGC Q1 2N2907 CAGC 0.1F
3 4 5 6 7
-40
-30
-20
-10
0
10
PIN (dBm re 200)
MODE GAIN DETO ICOM
11 10 9 8
02710-037
Figure 35. Leveling Accuracy of the AGC Function
1.0 VAGC 0.8 0.6
VACG (V); VOUT (arb)
Figure 37. External Clamp to Prevent AGC Overload. The resistive divider network, RA and RB, should be designed such that the base of Q1 is driven to 0.5 V.
0.4 0.2 VOUT 0 -0.2
02710-036
MODIFYING THE AGC SETPOINT
If an AGC setpoint other than the internal one is desired, an external detector must be used. Figure 38 shows a method that uses an external true-rms detector and error integrator to operate the AD8367 as a closed-loop AGC system with a usersettable operating level. The AD8361 (U2) produces a dc output level that is proportional to the rms value of its input, taken as a sample of the AD8367 (U1) output. This dc voltage is compared to an externally-supplied setpoint voltage, and the difference is integrated by the AD820 (U3) to form the gain control voltage that is applied to the GAIN input of the AD8367 through the divider composed of R4 and R5. This divider is included in order to minimize overload recovery time of the loop by having the integrator saturate at a point that only slightly overdrives the gain control input of the AD8367. The scale factor at VAGC is influenced by the values of R4 and R5; for the values shown, the factor is 86 mV/dB.
-0.4 -0.6 0 5 10 15 20 TIME (s) 25 30 35
40
Figure 36. AGC Response to a 32 dB Step in Input Level (f = 50 MHz)
It is important to understand that RAGC does not act as if in shunt with CAGC. Rather, the error-correction process is that of a true integrator, to guarantee an output that is exactly equal in rms amplitude to the specified setpoint. For large changes in input level, the integrating action of this loop is most apparent. The slew rate of VAGC is determined by the peak output current from the detector and the capacitor. Thus, for a representative value of CAGC = 3 nF, this rate is about 20 V rms or 10 dB/s, while the small-signal bandwidth is 1 kHz.
Rev. A | Page 16 of 24
AD8367
2.2 5V 10nF C2 VOUT INTO A 0.27F 200 LOAD U2 0.1F
1
AD8367
1
ICOM
ICOM 14
J1 INPUT R6 57.6
10nF
2 3 4 5 6 7
ENBL U1 HPFL 13 INPT MODE GAIN DETO ICOM VPSI 12 VPSO 11 VOUT 10 DECL 9 OCOM 8
CHP R HP 10nF 100
10nF
AD8361
VPOS IREF RFIN SREF 8 VRMS 7 FLTR 6 R1 200k
2 3
C5 10nF
C1 3.3nF R3 82k 2
4
PWDN COMM 5
Vg VAGC R4 33k R5 10k 6 4 U3
20pF
R2 150k 12k
Vrms
AD820
0.1F 7
3
VSET
02710-038
5V
Figure 38. Example of Using an External Detector to Form an AGC Loop
Note that in this circuit the AD8367's MODE pin must be pulled high to obtain correct feedback polarity because the integrator inverts the polarity of the feedback signal. The relationship between the setpoint voltage and the rms output voltage of the AD8367 is
VOUT -RMS = VSET x
The component values shown in Figure 38 were chosen for a 64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz. The response time of the loop as shown is roughly 5 ms for an abrupt input level change of 40 dB. Figure 41 shows the dynamic performance of the loop with a step-modulated CW signal applied to the input for a VSET of about 1 V. (6) For a linear-in-dB response, detectors such as the AD8318 or the AD8362 can be used in place of the AD8361.
4.0 3.5 3.0 10MHz 2.5
(R1 + 225)
225 x 7.5
where 225 is the input resistance of the AD8361 and 7.5 is its conversion gain. For R1 = 200 , this reduces to VOUT -RMS = VSET x 0.25. Capacitor C2 sets the averaging time for the rms detector. This should be made long enough to provide sufficient smoothing of the detector's output in the presence of the modulation on the RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p at the AD8361's output is a reasonable value. A considerably longer time constant needlessly lowers the AGC bandwidth, while a short time constant can degrade the accuracy of the true-rms measurement process. Components C1, R2, and R3 set the control loop's bandwidth and stability. The maximum stable loop bandwidth is limited by the rms detector's averaging time constant as previously discussed. For an input signal consisting of a 4.096 MS/s QPSK modulated carrier, the relationship between VSET and the output power for this setup is shown in Figure 39. The exponential shape reflects the linear-in-magnitude response of the AD8361. The adjacent channel power ratio (ACPR) as a function of output power is illustrated in Figure 40. The minima occur where the distortion and integrated noise powers cross over.
VSET (V)
380MHz 2.0 1.5 1.0
02710-039
0.5 0 -20
-15
-10
-5
0
5
10
POUT (dBm INTO 200)
Figure 39. AGC Setpoint Voltage vs. Output Power (QPSK: 4.096 MS/s; = 0.22; 1 User)
Rev. A | Page 17 of 24
AD8367
-20 -25 0.5 -30 -35 -40 -45 -50 -55 -60 -20 1.0 Vg
140MHz 380MHz
Vg (V); VOUT (arb)
0 VOUT -0.5
ACPR (dBc)
-1.0
10MHz
02710-041 02710-040
70MHz
-1.5
-2.0 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 TIME (Seconds)
-15
-10
-5
0
5
10
0.040
POUT (dBm INTO 200)
Figure 40. ACPR vs. Output Power for QPSK Waveform (QPSK: 4.096 MS/s; = 0.22; 1 User)
Figure 41. AGC Dynamic Response: 8367 AGC with an External Detector
Table 6. Suggested Component Values for External AGC Detector Circuit
Modulation Type QPSK QPSK /4 DQPSK 64 QAM 64 QAM 64 QAM Rate Sys/s 1.23 M 4M 24.3 K 100 K 500 K 4M C1 (F) 0.0022 0.0022 0.033 0.015 0.0068 0.0022 C2 (F) 0.033 0.015 0.68 1.5 0.33 0.068 R2 (k) 150 150 150 150 150 150 R3 (k) 62 39 51 51 62 100
Rev. A | Page 18 of 24
AD8367
EVALUATION BOARD
Figure 42 shows the schematic of the AD8367 evaluation board. The board is powered by a single supply of 2.7 V to 5.5 V.
SW2 R7 10k LK1
1 2 3
TP3 MODE J1 INPUT R1 57.6 R2 174 TP4 GAIN SW1
AD8367
ICOM ENBL INPT MODE GAIN DETO ICOM ICOM 14 HPFL 13 VPSI 12 VPSO 11 VOUT 10 DECL 9 OCOM 8
C1 1F CHP R HP 10nF 100
TP1 VP R6 4.7 C2 0.1F R5 4.7 C3 0.1F
4 5 6
J2 R4 C4 C5 174 0.1F 10nF R1 57.6 OUTPUT
02710-042
CAGC 0.1F
7
Figure 42. Evaluation Board Schematic
02710-043
Figure 43. Layout of Component Side
Figure 44. Silkscreen of Component Side
Rev. A | Page 19 of 24
02710-044
AD8367
Table 7 details the various configuration options of the evaluation board.
Table 7. Evaluation Board Configuration Options
Component TP1, TP2 TP3, TP4 SW1 SW2 LK1 R1, R2 Function Supply and Ground Vector Pins. Mode and Gain Vector Pins. VGA/AGC Select: Used to select VGA (Position A) or AGC (Position B) mode of operation. SW2 must be set for Position A for AGC mode of operation. MODE Select. Used to select positive or negative VGA slope. Set to Position B for an increasing gain with VGAIN, Position A for decreasing gain law. Device Enable. When LK1 is installed, the ENBL pin is connected to the positive supply and the AD8367 is in operating mode. Input Interface. R1 and R2 are used to provide an L-pad impedance-transforming network. The broadband matching network transforms a 50 source to match a 200 load with 11.5 dB of insertion loss. Output Interface. R3 and R4 are used to transform a 50 load termination to look like a 200 load with 11.5 dB of insertion loss. The ac coupling capacitor, C4, can be increased to obtain a lower high-pass corner frequency. Power Supply Decoupling. The nominal supply decoupling consists of a 1 F capacitor to ground, a 4.7 series resistor, and a 0.1 F capacitor to ground. The same decoupling network should be used on both the VPSI and VPSO supply lines. Internal Supply Decoupling. Capacitor C5 provides midsupply decoupling. Filter Capacitor. HPFL capacitor, sets the high-pass corner frequency. AGC Filter Capacitor. Capacitor, CAGC, sets closed-loop AGC response time. Mode Pull-Up Resistor. High-Pass Filter Resistor. Default Condition Not Applicable Not Applicable SW1 = A SW2 = B LK1 = Installed R1 = 57.6 (Size 0603) R2 = 174 (Size 0603) R3 = 57.6 (Size 0603) R4 = 174 (Size 0603) C4 = 0.1 F (Size 0603) C1 = 1 F (Size 0603) R5 = R6 = 4.7 (Size 0805) C2 = C3 = 0.1 F (Size 0603) C5 = 10 nF (Size 0603) CHP = 0.01 F (Size 0805) RHP = 0 (Size 0603) CAGC = 0.1 F (Size 0805) R7 = 10 k (Size 0805) RHP = 100 (Size)
R3, R4, C4
C1, C2, C3, R5, R6
C5 CHP CAGC R7 RHP
CHARACTERIZATION SETUP AND METHODS
Minimum-loss, L-pad matching networks were used to interface standard 50 . A test equipment to the 200 input impedance during the characterization process. Using a 57.6 shunt resistor followed by a 174 series resistor provides a broadband match between the 50 test equipment and the 200 device impedance, as illustrated in Figure 45. The insertion loss of this network is 11.5 dB.
AD8367
174 57.6 174 57.6
02710-045
Figure 45. Characterization Test Setup
Rev. A | Page 20 of 24
AD8367 OUTLINE DIMENSIONS
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 46. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimension shown millimeters
ORDERING GUIDE
Model AD8367ARU AD8367ARU-REEL-7 AD8367ARUZ 1 AD8367ARUZ-RL71 AD8367-EVAL
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 14-Lead TSSOP, Tube 14-Lead TSSOP, 7" Tape and Reel 14-Lead TSSOP, Tube 14-Lead TSSOP, 7" Tape and Reel Evaluation Board
Package Option RU-14 RU-14 RU-14 RU-14
Z = Pb-free part.
Rev. A | Page 21 of 24
AD8367 NOTES
Rev. A | Page 22 of 24
AD8367 NOTES
Rev. A | Page 23 of 24
AD8367 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02710-0-7/05(A)
Rev. A | Page 24 of 24

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