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Dual Ultrafast Voltage Comparator ADCMP567
FEATURES
250 ps propagation delay input to output 50 ps propagation delay dispersion Differential PECL compatible outputs Differential latch control Robust input protection Input common-mode range -2.0 V to +3.0 V Input differential range 5 V ESD protection >3 kV HBM, >200 V MM Power supply sensitivity >65 dB 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth Typical output rise/fall of 165 ps
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING INPUT Q OUTPUT
ADCMP567
INVERTING INPUT LATCH ENABLE INPUT Q OUTPUT
LATCH ENABLE INPUT
03632-0-001
Figure 1.
GENERAL DESCRIPTION
The ADCMP567 is an ultrafast voltage comparator fabricated on Analog Devices' proprietary XFCB process. The device features 250 ps propagation delay with less than 35 ps overdrive dispersion. Overdrive dispersion, a particularly important characteristic of high speed comparators, is a measure of the difference in propagation delay under differing overdrive conditions. A fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from -2.0 V to +3.0 V. Outputs are complementary digital signals fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 to VDD - 2 V. A latch input is included, which permits tracking, track-and-hold, or sample-and-hold modes of operation. The ADCMP567 is available in a 32-lead LFCSP package.
APPLICATIONS
High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Clock drivers Automatic test equipment
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADCMP567 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Considerations.............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Timing Information ......................................................................... 8 Application Information.................................................................. 9 Clock Timing Recovery ............................................................... 9 Optimizing High Speed Performance ........................................9 Comparator Propagation Delay Dispersion ..............................9 Comparator Hysteresis .............................................................. 10 Minimum Input Slew Rate Requirement ................................ 10 Typical Application Circuits ..................................................... 11 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCMP567 SPECIFICATIONS
Table 1. ADCMP567 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = -5.2 V, VDD = +3.3 V, TA = 25C, unless otherwise noted.)
Parameter DC INPUT CHARACTERISTICS (See Note) Input Common-Mode Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Open Loop Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Common-Mode Range Latch Enable Differential Input Voltage Input High Current Input Low Current Latch Setup Time Latch to Output Delay Latch Pulsewidth Latch Hold Time OUTPUT CHARACTERISTICS Output Voltage--High Level Output Voltage--Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Propagation Delay Tempco Prop Delay Skew--Rising Transition to Falling Transition Within Device Propagation Delay Skew-- Channel to Channel Propagation Delay Dispersion vs. Duty Cycle Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Slew Rate Propagation Delay Dispersion vs. Common-Mode Voltage Symbol VCM VOS DVOS/dT IBC Condition Min -2.0 -5 -5.0 Typ Max +3.0 +5 +5.0 Unit V V mV mV V/C A nA/C A pF k k dB dB mV V V A A ps ps ps ps V V ps ps ps ps ps/C ps ps ps ps ps ps
-10 -8.0
CIN
CMRR
VCM = -2.0 V to +3.0 V
1.0 1.0 10.0 +24 10.0 0.5 0.75 100 600 60 69 1.0
+42 +8.0
VLCM VLD @ 0.0 V @ -2.0 V 250 mV overdrive 250 mV overdrive 250 mV overdrive 250 mV overdrive PECL 50 to -2.0 V PECL 50 to -2.0 V 20% to 80% 20% to 80% 1 V overdrive 20 mV overdrive
VDD - 2.0 0.4 -12 -12
tS tPLOH, tPLOL tPL tH VOH VOL tR tF tPD tPD
+6 +6 50 300 150 90
VDD 2.0 +12 +12
VDD - 1.1 VDD - 1.95 175 140 250 300 0.5 10 10 10
VDD - 0.81 VDD - 1.54
50 mV to 1.5 V 20 mV to 1.5 V 0 V to 1 V swing, 20% to 80%, 50 ps and 600 ps 1 V swing, -1.5 V to 2.5 VCM
35 50 50
5
ps
Rev. 0 | Page 3 of 16
ADCMP567
Parameter AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth Symbol BW Condition 0 V to 1 V swing, 20% to 80%, 50 ps tR, tF >50% output swing tPD from 10 ns to 200 ps < 25 ps Min 3500 Typ 5000 Max Unit MHz
Toggle Rate Minimum Pulsewidth Unit to Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current Negative Supply Current Logic Supply Current Logic Supply Current Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Power Dissipation Power Dissipation Power Supply Sensitivity--VCC Power Supply Sensitivity--VEE Power Supply Sensitivity--VDD
PW
5 200 10
Gbps ps ps 20 95 18 80 5.25 -5.45 5.0 615 675 mA mA mA mA V V V mW mW dB dB dB
IVCC IVEE IVDD IVDD VCC VEE VDD
@ +5.0 V @ -5.2 V @ 3.3 V, without load @ 3.3 V, with load Dual Dual Dual Dual, without load Dual, with load
7 60 8 50 4.75 -4.96 2.5 415
13 78 13 65 5.0 -5.2 3.3 515 575 69 85 70
PSSVCC PSSVEE PSSVDD
NOTE: Under no circumstances should the input voltages exceed the supply voltages.
Rev. 0 | Page 4 of 16
ADCMP567 ABSOLUTE MAXIMUM RATINGS
Table 2. ADCMP567 Absolute Maximum Ratings
Supply Voltages Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VDD to GND) Ground Voltage Differential Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Current Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -6.0 V to +0.5 V -0.5 V to +6.0 V -0.5 V to +0.5 V -3.0 V to +4.0 V -7.0 V to +7.0 V -0.5 V to +5.5 V 30 mA -40C to +85C 125C -65C to +150C
THERMAL CONSIDERATIONS
The ADCMP567 LFCSP 32-lead package option has a JA (junction-to-ambient thermal resistance) of 27.2C/W in still air.
Input Voltages
Output Temperature
Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADCMP567 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND LEA LEA NC VDD 32 31 30 29 28 27 26 25 QA QA VDD
GND -INA +INA VCC VCC +INB -INB GND
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADCMP567
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
VEE NC VEE VCC VCC VEE NC VEE
NC = NO CONNECT
03632-0-002
Figure 2. ADCMP567 Pin Configuration
Table 3. ADCMP567 Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic GND -INA +INA VCC VCC +INB -INB GND GND LEB Function Analog Ground Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting analog input of the differential input stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. Positive Supply Terminal Positive Supply Terminal Noninverting analog input of the differential input stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Analog Ground Analog Ground One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator's being placed in the latch mode. LEB must be driven in conjunction with LEB. One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator's being placed in the latch mode. LEB must be driven in conjunction with LEB. No Connect. Leave pin unconnected. Logic Supply Terminal One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. Logic Supply Terminal Negative Supply Terminal No Connect. Leave pin unconnected. Negative Supply Terminal Positive Supply Terminal Positive Supply Terminal
Rev. 0 | Page 6 of 16
11
LEB
12 13 14
NC VDD QB
15
QB
16 17 18 19 20 21
VDD VEE NC VEE VCC VCC
GND LEB LEB NC VDD QB QB VDD
9 10 11 12 13 14 15 16
ADCMP567
Pin No. 22 23 24 25 26 Mnemonic VEE NC VEE VDD QA Function Negative Supply Terminal No Connect. Leave pin unconnected. Negative Supply Terminal Logic Supply Terminal One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. Logic Supply Terminal No Connect. Leave pin unconnected. One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator's being placed in the latch mode. LEA must be driven in conjunction with LEA. One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator's being placed in the latch mode. LEA must be driven in conjunction with LEA. Analog Ground
27
QA
28 29 30
VDD NC LEA
31
LEA
32
GND
Rev. 0 | Page 7 of 16
ADCMP567 TIMING INFORMATION
LATCH ENABLE 50% LATCH ENABLE
tS tH
tPL
DIFFERENTIAL INPUT VOLTAGE
VIN VOD
VREF VOS
tPDL
Q OUTPUT
tPLOH
50%
tPDH
tF
50%
Q OUTPUT
tPLOL tR
03633-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP567 compare and latch features. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions
Symbol tPDH Timing Input to output high delay Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output lowto-high transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output highto-low transition
Symbol tH
Timing Minimum hold time
tPL
tS
tPDL
Input to output low delay
Minimum latch enable pulsewidth Minimum setup time
tR
tPLOH
Latch enable to output high delay
Output rise time
tF
Output fall time
tPLOL
Latch enable to output low delay
VOD
Voltage overdrive
Description Minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs Minimum time that the Latch Enable signal must be high to acquire an input signal change Minimum time before the negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs Amount of time required to transition from a low to a high output as measured at the 20% and 80% points Amount of time required to transition from a high to a low output as measured at the 20% and 80% points Difference between the differential input and reference input voltages
Rev. 0 | Page 8 of 16
ADCMP567 APPLICATION INFORMATION
The ADCMP567 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP567 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 F electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP567 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input should be attached to VDD (VDD is a PECL logic high), and the complementary input, LATCH ENABLE, should be tied to VDD - 2.0 V. This will disable the latching function. Occasionally, one of the two comparator stages within the ADCMP567 will not be used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described above. The best performance is achieved with the use of proper PECL terminations. The open emitter outputs of the ADCMP567 are designed to be terminated through 50 resistors to VDD -2.0 V, or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP567. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP567. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP567 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 k source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is significantly slower than the sub 500 ps capability of the ADCMP567. Source impedances should be significantly less than 100 for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP567 should be free from oscillation when the comparator input signal passes through the switching threshold.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP567 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP567 is far less sensitive to input variations than most comparator designs. Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined
Rev. 0 | Page 9 of 16
ADCMP567
as the variation in propagation delay as the input overdrive conditions are changed (Figure 4). For the ADCMP567, overdrive dispersion is typically 35 ps as the overdrive is changed from 100 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP567 has equal delays for positive and negative going inputs. The 35 ps propagation delay overdrive dispersion of the ADCMP567 offers considerable improvement of the 100 ps dispersion of other similar series comparators.
1.5V OVERDRIVE
0 -VH 2 0V INPUT 1 +VH 2
INPUT VOLTAGE 20mV OVERDRIVE
OUTPUT
03633-0-005
VREF VOS
Figure 5. Comparator Hysteresis Transfer Function
DISPERSION Q OUTPUT
03633-0-004
60
50
Figure 4. Propagation Delay Dispersion
HYSTERESIS (mV)
40
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 5. If the input voltage approaches the threshold from the negative direction, the comparator will switch from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator will remain in a 1 state until the threshold -VH/2 is crossed coming from the positive direction. In this manner, noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by VH/2. Positive feedback from the output to the input is often used to produce hysteresis in a comparator (Figure 9). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. Another method to implement hysteresis is generated by introducing a differential voltage between LATCH ENABLE and LATCH ENABLE. inputs (Figure 10). Hysteresis generated in this manner is independent of output swing and is symmetrical around zero. The variation of hysteresis with input voltage is shown in Figure 6.
30
20
10
0 -25
-20
-15 -10 -5 LATCH = LE - LEB (mV)
0
5
Figure 6. Comparator Hysteresis Transfer Function Using Latch Enable Input
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 5 V/s or faster to ensure a clean output transition. If slew rates less than 5 V/s are used, then hysteresis should be added to reduce the oscillation.
Rev. 0 | Page 10 of 16
03632-0-006
ADCMP567
TYPICAL APPLICATION CIRCUITS
VIN
VIN
ADCMP567
VREF
ADCMP567
OUTPUTS
OUTPUTS
LATCH ENABLE INPUTS
VDD - 2V
HYSTERESIS VOLTAGE
450
VDD - 2V
ALL RESISTORS 50
ALL RESISTORS 50 UNLESS OTHERWISE NOTED
03632-0-007 03632-0-010
Figure 7. High Speed Sampling Circuits
Figure 10. Hysteresis Using Latch Enable Input
+VREF
50
50
ADCMP567
VIN
OUTPUTS
VIN
ADCMP567
100
50 100
50
(VDD - 2) x 2
03632-0-011
-VREF
ADCMP567
Figure 11. How to Interface a PECL Output to an Instrument with a 50 to Ground Input
LATCH ENABLE INPUTS
VDD - 2V
ALL RESISTORS 50
03632-0-008
Figure 8. High Speed Window Comparator
VIN
ADCMP567
OUTPUTS
VREF
R1
R2 VDD - 2V
ALL RESISTORS 50
03632-0-009
Figure 9. Hysteresis Using Positive Feedback
Rev. 0 | Page 11 of 16
ADCMP567 TYPICAL PERFORMANCE CHARACTERISTICS
(VCC = +5.0 V, VEE = -5.2 V, VDD = +3.3 V, TA = 25C, unless otherwise noted.)
30
23.0 22.9
25
+IN INPUT BIAS CURRENT (A) (+IN = 1V, -IN = 0V)
22.8 22.7 22.6 22.5 22.4 22.3 22.2 22.1
INPUT BIAS CURRENT (A)
20
15
10
5
03632-0-013
0 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V)
22.0 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 12. Input Bias Current vs. Input Voltage
60
Figure 15. Input Bias Current vs. Temperature
2.0 1.8
50
1.6
OFFSET VOLTAGE (mV)
1.2 1.0 0.8 0.6 0.4 0.2 0 -40
03632-0-014
HYSTERESIS (mV)
1.4
40
30
20
10
-20
0
20 40 TEMPERATURE (C)
60
80
0 -25
-20
-15 -10 5 LATCH = LE - LEB (mV)
0
5
Figure 13. Input Offset Voltage vs. Temperature
Figure 16. Hysteresis vs. Latch
195 185 175 165 155 145 135
03632-0-015
195 185 175
TIME (ps)
TIME (ps)
165 155 145 135 125 -40 -30 -20 -10
03632-0-018
125 -40 -30 -20 -10
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
Figure 14. Rise Time vs. Temperature
Figure 17. Fall Time vs. Temperature
Rev. 0 | Page 12 of 16
03632-0-017
03632-0-016
ADCMP567
240 238
236 235
PROPAGATION DELAY (ps)
PROPAGATION DELAY (ps)
236 234 232 230 228 226 224 -40 -30 -20 -10
03632-0-019
234 233 232 231 230 229 -2
03632-0-022 03632-0-023
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
-1 0 1 2 INPUT COMMON-MODE VOLTAGE (V)
3
Figure 18. Propagation Delay vs. Temperature
Figure 21. Propagation Delay vs. Common-Mode Voltage
60
0 -5
PROPAGATION DELAY ERROR (ps)
PROPAGATION DELAY ERROR (ps)
03632-0-020
50
-10 -15 -20 -25 -30 -35 -40 0.15
40
30
20
10
0 0 0.2 0.4 0.6 0.8 1.0 1.2 OVERDRIVE VOLTAGE (V) 1.4 1.6
2.15
4.15 6.15 PULSEWIDTH (ns)
8.15
Figure 19. Propagation Delay Error vs. Overdrive Voltage
Figure 22. Propagation Delay Error vs. Pulsewidth
2.5
2.3
OUTPUT RISE AND FALL (V)
2.1
1.9
1.7
1.5
1.3 1.0
1.1
1.2
1.3
1.4 1.5 1.6 TIME (ns)
1.7
1.8
1.9
2.0
Figure 20. Rise and Fall of Outputs vs. Time
03632-0-021
Rev. 0 | Page 13 of 16
ADCMP567 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 2.70 SQ 1.25
8
0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
17 16
9
3.50 REF
1.00 0.90 0.80 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters
ORDERING GUIDE
Model ADCMP567BCP Temperature Range -40C to +85C Package Description LFCSP-32 Package Option CP-32
Rev. 0 | Page 14 of 16
ADCMP567 Notes
Rev. 0 | Page 15 of 16
ADCMP567 Notes
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03632-0-10/03(0)
Rev. 0 | Page 16 of 16
Filename: ADCMP567_Oct 21.doc Directory: C:\Documents and Settings\fburns\Desktop Template: C:\Documents and Settings\aakers\Desktop\Data Sheet Template v3.2.dot Title: ADCMP567 Dual Ultrafast Voltage Comparator Data Sheet (REV. 0) Subject: Author: Analog Devices, Inc. Keywords: Comments: Creation Date: 10/15/2003 1:35 PM Change Number: 15 Last Saved On: 10/21/2003 4:57 PM Last Saved By: Frumie Burns Total Editing Time: 77 Minutes Last Printed On: 10/21/2003 4:58 PM As of Last Complete Printing Number of Pages: 16 Number of Words: 4,011 (approx.) Number of Characters: 20,422 (approx.)

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