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ASAHI KASEI
[AKD4125-A]
AKD4125-A
AK4125 Evaluation Board Rev.0
GENERAL DESCRIPTION The AKD4125-A is an evaluation board for AK4125, the digital sample rate converter. The AKD4125-A has the digital audio interface and can achieve the interface with digital audio system via opt-connector. Ordering guide
AKD4125-A --AK4125 Evaluation Board
FUNCTION * DIR/DIT with optical input/output * 10pin Header for AKM AD/DA evaluation board
5V Opt In AK4114 Regulator GND AK4114 Opt Out
COAX
COAX
10pin Header
AK4125
10pin Header
DSP Data
DSP Data
Figure 1. AKD4125-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
-1-
2005/06
ASAHI KASEI
[AKD4125-A]
Operation sequence
1) Set up the power supply lines. [VCC] (red) = +5V (for regulator) [DGND] (black) = 0V Each supply line should be distributed from the power supply unit. The regulator can be supplied 3.3V to all circuits. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4125 should be reset once bringing SW1 (PDN) "L" upon power-up.
Evaluation mode
(1) Setting for Input port (1) When using DIR function of AK4114 (U3) When using PORT1 (DIR) or J1 (COAX), nothing should be connected to PORT2 (INPUT).
JP2 IBICK JP3 SDTI JP4 ILRCK
* SW3 setting (See Table 1) Upper-side is "H" and lower-side is "L". The audio interface format of the AK4114 is fixed to 24bit, MSB justified. IDIF2-0 and PLL2-0 of SW3 should be used by default setting. SW3 No. 1 2 3 4 5 6 7 Name DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2 ON ("H") Dither ON OFF ("L") Dither OFF Default L H L H L H L
PLL Mode Setting Fixed to default AK4125 Audio I/F Format Setting Fixed to default Table 1. SW3 Setting
-2-
2005/06
ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2 IBICK JP3 SDTI JP4 ILRCK
* SW3 setting (See Table 2) Upper-side is "H" and lower-side is "L". SW3 No. 1 2 3 4 5 6 7 Name DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2 ON ("H") Dither ON OFF ("L") Dither OFF Default L H L H L H L
PLL Mode Setting Refer to Table 3 AK4125 Audio I/F Format Setting Refer to Table 4 Table 2. SW3 Setting
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Master / Slave
PLL2 L L
PLL1 L L
PLL0 L H
ILRCK Freq 8k 96kHz 8k 216kHz 16k 216kHz (Note 1)
IBICK Freq Depending on IDIF2-0
IMCLK Not needed.
SMUTE (Note 4) Manual Semi-Auto
Slave IMCLK = DVSS IBICK = Input ILRCK = Input
Master IMCLK = Input IBICK = Output ILRCK = Output
L L H H H H L L L L H H H H
H L H H Reserved L L 32fsi (Note 3) Not L H 64fsi 8k 216kHz needed. (Note 2) H L 128fsi 64fsi H H L L 128fs 8k 216kHz L H 256fs 8k 108kHz H L 512fs 8k 54kHz H H 128fs 8k 216kHz 64fs L L 192fs 8k 216kHz L H 384fs 8k 108kHz H L 768fs 8k 54kHz H H 192fs 8k 216kHz Table 3. PLL Setting (Input PORT)
Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to "PLL Loop Filter" in the datasheet. 470, 0.22F and 1nF are implemented on the evaluation board. Note 2. The IBCIK must be continuous except when the clocks are changed. Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. Note 4. Refer to "Soft Mute Operation" for Manual mode and Semi-Auto mode in the datasheet.
-3-
2005/06
ASAHI KASEI
[AKD4125-A]
Mode 0 1 2 3 4 5 6 7
IDIF2 L L L L H H H H
IDIF1 L L H H L L H H
IDIF0 L H L H L H L H
SDTI Format 16bit, LSB justified 20bit, LSB justified 24/20bit, MSB justified 24/16bit, I2S Compatible 24bit, LSB justified 24bit, MSB justified 24bit, I2S Compatible
ILRCK
IBICK
Input
Input
Output
Output
IBICK Freq 32fsi 40fsi 48fsi 48fsi or 32fsi 48fsi 64fs 64fs
Master / Slave
Slave
Master
Reserved Table 4. Input Audio Interface Format (Input PORT)
(2) Setting for Output port (1) When using DIT function of AK4114 (U4) When using PORT4 (DIT) or J2 (TX), nothing should be connected to PORT3 (OUTPUT). When BICK and LRCK frequencies are changed, the value of X'tal (X1) frequency should be changed.
JP6 OBICK JP7 OLRCK
* SW4 setting (See Table 5) Upper-side is "H" and lower-side is "L". The audio interface format of the AK4114 is fixed to 24bit, MSB justified. ODIF2-0, CMODE2-0 and OBIT1-0 of SW3 should be used by default setting. SW4 No. 1 2 3 4 5 6 7 Name ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0 ON ("H") OFF ("L") AK4125 Output Audio I/F Format Setting Fixed to default AK4125 Mode Setting Fixed to default AK4125 Output bit Length Setting Fixed to default Table 5. SW4 Setting Default H L H L L H H
-4-
2005/06
ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT).
JP6 OBICK JP7 OLRCK
* SW4 setting (See Table 6) Upper-side is "H" and lower-side is "L". SW4 No. 1 2 3 4 5 6 7 Name ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0 ON ("H") OFF ("L") AK4125 Output Audio I/F Format Setting Refer to Table 7 AK4125 Mode Setting Refer to Table 8 AK4125 Output bit Length Setting Refer to Table 9 Table 6. SW4 Setting Default H L H L L H H
Mode ODIF1 ODIF0 SDTO Format 0 L L LSB justified 1 L H (Reserved) 2 H L MSB justified 3 H H I2S Compatible Table 7. Output Audio Interface Format 1 (Output PORT) Mode 0 1 2 3 4 5 6 7 CMODE2 CMODE1 CMODE0 Master / Slave OMCLK L L L Master 256fso L L H Master 384fso L H L Master 512fso L H H Master 768fso H L L Slave Not used. Set to DVSS. H L H Master 128fso H H L Master 192fso H H H Master (Bypass) Not used. Set to DVSS. Table 8. Master/Slave Control (Output PORT) Mode OBIT1 OBIT0 SDTO Output 0 L L 16bit 1 L H 18bit 2 H L 20bit 3 H H 24bit Table 9. Output Audio Interface Format 2 (Output PORT) fso 8k 108kHz 8k 108kHz 8k 54kHz 8k 54kHz 8k 216kHz 8k 216kHz 8k 216kHz 8k 216kHz
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2005/06
ASAHI KASEI
[AKD4125-A]
Other jumper pins set up
1. JP1 (RX) : Select of RX input COAX: COAX input. RX: Optical input. 2. JP5 (CKSO) : AK4114 BICK and LRCK setting H: BICK: 2.048MHz 12.288MHz, LRCK: 32kHz 192kHz L: BICK: 2.048MHz 6.144MHz, LRCK: 32kHz 96kHz When BICK and LRCK frequencies are changed, the value of X'tal (X1) frequency should be changed. 3. JP8 (TX) : Select of TX output BNC: BNC connector (J2) output. OPT: Optical (PORT4) output.
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (PDN): Resets the AK4125 and the AK4114. Keep "H" during normal operation. The AK4125 and the AK4114 should be resets once bringing "L" upon power-up. [SW2] (SMUTE): Soft mute of AK4125
Indication for LED
[LED1] (UNLOCK): Monitor UNLOCK pin of the AK4125. LED turns on when unlock occurs. [LED2] (ERF): Monitor INT0 pin of the AK4114 (U3). LED turns on when unlock or parity error occurs.
-6-
2005/06
ASAHI KASEI
[AKD4125-A]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * Power Supply * Band width * Temperature [Measurement Result] SRC Characteristics THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 44.1kHz/8kHz) Dynamic Range (Input = 1kHz, -60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 192kHz/192kHz) Dynamic Range (Input = 1kHz, -60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz Result 130.2 124.9 130.6 124.3 116.7 136.2 136.4 136.1 132.3 132.2 139.6 Unit dB dB dB dB dB dB dB dB dB dB dB
: Audio Precision, System Two Cascade : AVDD = DVDD = 3.3V : 10Hz FSO/2 : Room
-7-
2005/06
ASAHI KASEI
[AKD4125-A]
[Plot]
AK4125 THD+N vs Input Level (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,fin=1KHz
-120 -122 -124 -126 -128 -130 -132 d B F S -134 -136 -138 -140 -142 -144 -146 -148 -150 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Fig 1. THD+N vs. Input Level
AK4125 THD+N vs Input Frequency (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input Level=0dBFS
-80 -85 -90 -95 -100 -105 -110 d B F S -115 -120 -125 -130 -135 -140 -145 -150 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 2. THD+N vs. Input Frequency (Input = 0dBFS)
-8-
2005/06
ASAHI KASEI
[AKD4125-A]
AK4125 THD+N vs Input Frequency (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input Level=-60dBFS
-100 -105 -110 -115 -120 -125 -130 d B F S -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Fig 3. THD+N vs. Input Frequency (Input = -60dBFS)
AK4125 Linearity (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,fin=1KHz
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -150
-140
-130
-120
-110
-100
-90
-80 dBFS
-70
-60
-50
-40
-30
-20
-10
+0
Fig 4. Linearity
-9-
2005/06
ASAHI KASEI
[AKD4125-A]
AK4125 Frequency_Response (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=0dBFS
+1 +0.5 -0 -0.5 -1 -1.5 -2 d B F S -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k 22k
Fig 5. Frequency Response
AK4125 FFT Plot (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=0dBFS,fin=1KHz
+0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Fig 6. FFT Plot (Input = 0dBFS)
- 10 -
2005/06
ASAHI KASEI
[AKD4125-A]
AK4125 FFT Plot (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=-60dBFS,fin=1KHz
+0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Fig 7. FFT Plot (Input = -60dBFS)
AK4125 Frequency_Response (Blue:fsi=48KHz, Red:fsi=96KHz, Green:fsi=192KHz) AVDD=DVDD=3.3V,fso=48KHz
+1 +0.5 -0 -0.5 -1 -1.5 -2 -2.5 d B F S -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k 12k Hz 14k 16k 18k 20k 22k
fsi=192kHz fsi=96kHz fsi=48kHz
Fig 8. Frequency Response
- 11 -
2005/06
ASAHI KASEI
[AKD4125-A]
AK4125 Frequency_Response (Yellow:fsi=44.1KHz, Blue:fsi=48KHz, Red:fsi=96KHz,Green:fsi=192KHz) AVDD=DVDD=3.3V,fso=44.1KHz
+1 +0.5 -0 -0.5 -1 -1.5 -2 -2.5 d B F S -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k 22k
fsi=44.1kHz fsi=192kHz fsi=96kHz fsi=48kHz
Fig 9. Frequency Response
- 12 -
2005/06
ASAHI KASEI
[AKD4125-A]
Revision History
Date (YY/MM/DD) 05/06/30 Manual Revision KM078700 Board Reason Revision First Edition 0 Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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2005/06
A
B
C
D
E
REG
2
E
1
D1 HSU119
R1 10k
1 2 3 4
E
PDN REG T1 TA48M33F
GND OUT IN
L
H
3
1
SW1 ATE1D-2M3 PDN
2
C1 0.1u
U1A 74HC14
U1B 74HC14
VCC For 74HC14 x 1 REG C3 C4 0.1u 47u + C6 0.1u
C5 1n
1
U2 C2 0.1u
FILT AVDD 30
REG
D
C7 0.22u
R2 470
2 AVSS DVSS 29
C8 0.1u C10 0.1u
+ C9 10u
D
2
1
D2 HSU119
R3 10k
5 6 9 8
3
PDN
DVDD
28
R4 51
4 SMUTE OMCLK 27
OMCLK R5 51
L
H
3
1
SW2 ATE1D-2M3 SMUTE
2
C11 0.1u
U1C 74HC14
U1D 74HC14
5 DITHER OLRCK 26
OLRCK R6 51
6
PLL2
OBICK
25
OBICK R8 51
R7 51 ILRCK R9 51
C
7
ILRCK
SDTO
24
SDTO
IBICK R10 51 SDTI
8
IBICK
ODIF1
23
C
9
SDTI
ODIF0
22
10
IDIF0
CMODE2
21
11
IDIF1
CMODE1
20
REG SW3 DSS107
1 2 3 4 5 6 7 14 13 12 11 10 9 8
12
IDIF2
CMODE0
19
R11 51
13 PLL0 IMCLK 18
REG IMCLK
1 2 3 4 5 6 7
B
RP1 M8-1-473
7 6 5 4 3 2 1
DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2
SW4 DSS107
14 13 12 11 10 9 8
14
PLL1
OBIT1
17
15
INPUT
11
UNLOCK
OBIT0
16
ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0
B
OUTPUT
U1E 74HC14
10
AK4125
RP2 M8-1-473
7 6 5 4 3 2 1
47K LED1 SML-210JT REG
A
R12 1k
47K
1
2
UNLOCK
A
Title Size Document Number
AKD4125-A
AK4125
Sheet
E
Rev
A3
Date:
A B C D
0 1
of
Monday, May 23, 2005
3
A
B
C
D
E
RX(COAX)
E
J1 BNC-R-PC R13 75
C12 0.1u
E
DIF2 DIF1 DIF0 PORT1 TORX141 RX(OPT)
VCC GND OUT 3 2 1
Setting 24bit, MSB justified
L1 47u + C13 0.1u R14 470 OPT COAX JP1 RX HIF3G-50P-2.54DSA (3x1)
REG
H
L
L
OCKS1 C14 10u C15 0.1u
1
OCKS0 H
Setting 128fs, 192kHz
H
CM1 ERF L
CM0 L
Setting PLL=ON, RX Mode
D
D
C16 0.47u
39
2
R15 18k
LED2 SML-210JT
45
41
47
43
48
46
44
42
40
38
U3
VCOM
AVSS
R
TEST1
AVDD
NC
NC
INT1
RX3
RX2
RX1
RX0
37
1
IPS0
2
NC
3
DIF0
C
4
TEST2
5
DIF1
6
NC
AK4114
7
DIF2
8
IPS1
9
P/SN
B
10
XTL0
11
XTL1
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
13
14
15
16
17
18
19
20
21
22
23
C17 0.1u C19 10u +
C18 0.1u C20 10u +
A
24
A
B
+
R16 1k
U1F 74HC14
INT0 36 13 12
OCKS0
35
OCKS1
34
CM1
33
C
CM0
32
R17 100 IMCLK PDN IBICK R19 100
PDN
31
R18 100 PORT2 A1-10PA-2.54DSA IMCLK IBICK ILRCK SDTI
1 2 3 4 5 10 9 8 7 6
XTI
30
XTO
29
ILRCK R20 100 SDTI
DAUX
28
INPUT
B
MCKO2
27
R21 220k JP2 HIF3G-50P-2.54DSA (2x1) IBICK
R22 220k
R23 220k
R24 220k
BICK
26
JP3 HIF3G-50P-2.54DSA (2x1) SDTI
SDTO 25
JP4 HIF3G-50P-2.54DSA (2x1) ILRCK
A
Title Size Document Number
AKD4125-A
INPUT
Sheet
E
Rev
A3
Date:
C D
0 2
of
Monday, May 23, 2005
3
A
B
C
D
E
REG + DIF2 DIF1 DIF0 H L L Setting 24bit, MSB justified
E
C21 10u C22 0.1u
E
OCKS1 L C23 0.47u
39 38 37
OCKS0 L H
Setting 256fs, 96kHz 128fs, 192kHz
H
47
45
43
41
48
46
44
U4
42
40
VCOM
AVSS
R
TEST1
AVDD
NC
NC
1
D
INT1
RX3
RX2
RX1
RX0
IPS0
2
NC
OCKS0
35
L
3 DIF0 OCKS1 34
4
TEST2
CM1
33
5
DIF1
CM0
32
6
NC
AK4114
PDN
31
1
7
C
DIF2
XTI
30
X1 HC-49/U 11.2896MHz
IPS1 XTO 2 8 29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
B
13
14
15
16
17
18
19
20
21
22
23
C26 0.1u C28 10u +
C27 0.1u C29 10u +
PORT4 TOTX141 TX(OPT)
IN VCC GND
A
3 2 1
OPT C31 0.1u JP8 TX
BNC
C30 0.1u
R33 240 R34 150
T2 DA-02F
J2 BNC-R-PC TX(BNC)
HIF3G-50P-2.54DSA (3x1)
1:1
24
A
B
C
H
+
CM1 L
CM0 H
Setting PLL=OFF, X'tal Mode
INT0
36
D
JP5 HIF3G-50P-2.54DSA (3x1) CKSO OMCLK
R25 100
R26 100 OBICK R27 100 OLRCK PDN C24 (open) SDTO R29 220k R30 220k R31 220k R32 220k R28 100
PORT3 A1-10PA-2.54DSA OMCLK OBICK OLRCK SDTO
1 2 3 4 5 10 9 8 7 6
OUTPUT
C
C25 (open)
JP6 HIF3G-50P-2.54DSA (2x1) OBICK
B
JP7 HIF3G-50P-2.54DSA (2x1) OLRCK
A
Title Size Document Number
AKD4125-A
OUTPUT
Sheet
E
Rev
A3
Date:
D
0 3
of
Monday, May 23, 2005
3

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