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ICs for TV
AN5392FBQ
Luminance and color difference drive/cutoff signal processor IC with I2C bus
Unit: mm
16.20.3
(1.0)
s Overview
The AN5392FBQ is an RGB processor IC which converts the luminance and color difference signal into a primary color signal. This IC supports all kinds of input signal from hi-vision, wide, NTSC, PAL, VGA, etc. for maximum rationalization and high performance of the end products.
48 49
14.00.2 33
32
64
17 1 (1.0) 0.8 16
1.950.2 0.10.1 0.90.1
s Features
* A wider band signal processing (Y: 30 MHz/-3 dB, color difference: 15 MHz/-3 dB) * High picture quality thanks to a large variety of built-in correction circuit for Y signal * Y, C-Y signal conversion circuit built in for RGB signal for a personal computer * Possible to mount in a high density thanks to SMD package
0.35-0.05
+0.10
0.90.1
0.15-0.05
+0.10
14.00.2 16.20.3
Seating plane
0.550.2
QFS064-P-1414
s Applications
* Hi-vision TV, wide TV, projection TV, plasma display panel (PDP)
1
AN5392FBQ
s Block Diagram
ICs for TV
DC regenaration rate 47 Analog V CC 46 Blooming level in 45 Black peak det. 44 White peak det. 43 APL det. 42 R-CLP 41 G-CLP 40 B-CLP 39 OSD-R in 38 OSD-G in 37 OSD-B in 36 Y in S 35 Y in
R, G, B limiter in 34
48
VM out 49 ABL/ACL in 50 R-Y (S) in 51 Y (S) in 52 B-Y (S) in 53 54 Y, U, V V
CC
33
Spot killer in
M
ABL/ACL block
R Y R
32 G-V CC 31 G-out 30 G-GND 29 B-V Output block
CC
Video block
Y
Matrix block
G B
SW block
G B
28 B-out 27 B-GND 26 R-V CC 25 R-out 24 R-GND 23 Analog GND 22 Pulse V CC 21 DI in 20 CRT mute 19 Neck mute 18 R,G,B mute 17 BLK in
M/S in 55 CLP (M1) in 56 R-Y (M1) in 57 Y (M1) in 58 B-Y (M1) in 59 CLP (M2) in 60 R-Y (M2) in 61 Y (M2) in 62 B-Y (M2) in 63 Y, U, V GND 64 Input block
R-Y
R-Y G-Y B-Y
Chrominance block B-Y
R, G, B Y, U, V block
I2C DAC block
BLK block
2
1 I2L GND 2 R,G,B GND 3 B-Y out 4 Y-out 5 R-Y out 6 CLP (R, G, B) in 7 R-in 8 G-in 9 B-in 10 R, G, B VCC 11 VP in 12 Slave address SW 13 SDA 14 SCL 15 I2L VCC 16 Pulse GND
ICs for TV
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I2L GND Description Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
AN5392FBQ
Description Spot killer input R, G, B limiter input YM input YS input OSD-B input OSD-G input OSD-R input B-CLP filter G-CLP filter R-CLP filter APL detection filter White peak detection filter Black peak detection filter Blooming level input Analog VCC DC regenaration rate VM output ABL/ACL input R-Y (S) input (Pr (S) input) Y (S) input B-Y (S) input (Pb (S) input) Y, U, V VCC M/S input CLP (M1) input R-Y (M1) input (Pr (M1) input) Y (M1) input B-Y (M1) input (Pb (M1) input) CLP (M2) input R-Y (M2) input (Pr (M2) input) Y (M2) input B-Y (M2) input (Pb (M2) input) Y, U, V GND
R, G, B GND B-Y output Y-output R-Y output CLP (R, G, B) input R-input G-input B-input R, G, B VCC VP input Slave address SW SDA SCL I2L VCC
Pulse GND BLK input R, G, B mute input Neck mute input CRT mute input DI input Pulse VCC Analog GND R-GND R-output R-VCC B-GND B-output B-VCC G-GND G-output G-VCC
3
AN5392FBQ
s Absolute Maximum Ratings
Parameter Supply voltage VCC Symbol VCC1 VCC2 Supply current
*2 *1
ICs for TV
Rating 10.0 5.6 70.0 34.0 685 -20 to + 70 -55 to + 150
Unit V
ICC
ICC1 ICC2
mA
Power dissipation
PD Topr Tstg
*1
mW C C
Operating ambient temperature Storage temperature
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: The power dissipation PD shown is for the independent IC without a heat sink in the free air at Ta = 70C.
s Recommended Operating Range
Parameter Supply voltage Symbol VCC1 VCC2 Range 8.1 to 9.9 4.5 to 5.5 Unit V
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C
Parameter DC characteristics Circuit current 1 *1 Circuit current 2 *1 Y-system Video voltage gain Video voltage gain variation amount Frequency characteristics Typical output pedestal Brightness variable range Contrast ratio APL detection voltage APL detection ratio AYG AY fY DCP VBR ACON VAPL APL Input: Sine wave 0.2 V[p-p] f = 1 MHz, contrast: max. Ratio between R,G and B Drive: typ. Input: Sine wave 0.2 V[p-p] f = 30 MHz, contrast: max. Brightness: typ. Brightness: min. max. Contrast: min. max. Input: Total white 0.7 V[0-p] APL detection pin 43 voltage 4.7 -2.5 -6 2.6 1.8 25 0.7 5.6 0 -3 3.0 2.2 30 1.0 0.54 6.7 +2.5 +1 3.4 2.6 1.3 0.66 Times dB dB V V dB V Times ICC1 ICC2 VCC1 = 9 V, VCC2 = 5 V No signal input VCC1 = 9 V, VCC2 = 5 V No signal input 39 20 51 25 63 30 mA mA Symbol Conditions Min Typ Max Unit
Input: Total white 0.7 V[0-p] 0.35 V[0-p] 0.46 APL detection pin 43 voltage ratio
Note) *1: ICC1 is a total amount of the current flowing through pin 10, pin 26, pin 29, pin 32, pin 47 and pin 54. ICC2 is a total amount of the current flowing through pin 15 and pin 33.
4
ICs for TV
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
Parameter Y-system (continued) DC regeneration ratio 1 DC regeneration ratio 2 DC regeneration ratio 3 Output blooming level Output blooming level variation amount White gradation correction 1 *2 White gradation correction 2 *2 Black extension characteristics 1 *3 Black extension characteristics 2 *3 Black extension characteristics 3 *3 Black extension characteristics 4 *4 Black extension characteristics 5 *4 Black extension characteristics 6 *4 White character correction 1 *2 White character correction 2 *2 DC1 DC2 DC3 VBL VBL Y1 Y2 YBL1 YBL2 YBL3 YBL4 YBL5 YBL6 VW1 VW2 Input signal: APL 10% 90%, APL det. pin 0 V Input signal: APL 10% 90%, DC regeneration SW/on, polarity: - Input signal: APL 10% 90%, DC regeneration SW: On, polarity: + Blooming DC = 3.8 V, pin 43: 0 V, brightness: max. Blooming DC = 3.8 V 4.2 V, pin 43: 0 V, brightness: max. Gain: max., level: typ. max. White gradation SW: On Gain: max., level: typ. min. White gradation SW: On Output amplitude: 0 V[p-p] Level: typ., gain: min. max. Output amplitude: 1.0 V[0-p] Level: typ., gain: min. max. Output amplitude: 2.2 V[0-p] Level: typ., gain: min. max. Black detection: Open 3 V Level: typ., gain: typ. Black detection: Open 3 V Level: typ., gain: max. Black detection: Open 3 V Level: min. max., gain: typ. Blooming DC adjustment Level: max., gain: min. typ. Blooming DC adjustment Level: min., gain: min. max. PR, PB input: +0.2 V[p-p] Level: max., gain: min. max. ABL/ACL pin: 7.5 V Level: min., gain: min. max. ABL/ACL pin: 3 V Level: min. max., gain: max. 96 65 115 5.7 102 75 125 6.7 Symbol Conditions Min Typ
AN5392FBQ
Max
Unit
107 85 135 7.7
% % % V V % % V V V V V V % % V V V
-1.18 - 0.93 - 0.68 9.0 -24 - 0.1 14 -18 0 18.0 -12 +0.1
- 0.49 - 0.37 - 0.25 - 0.1 0 +0.1
-1.10 - 0.82 - 0.55 -2.00 -1.55 -1.00 - 0.48 - 0.30 - 0.12 10.0 -9.3 - 0.2 - 0.1 0.28 25.0 0 0 0 0.39 40.0 9.3 +0.2 +0.1 0.50
White character correction off *2 WOFF ABL off *5 ABL start 1*5 VABL1 VABL2
Note) *2: Control a blooming DC voltage (pin 46) *3: Black gradation SW: On *4: Black gradation SW: On, brightness: max. *5: ABL SW: On, brightness: max.
5
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
Parameter Y-system (continued) ABL start 2*5 ABL gain 1*5 ACL off *6 ACL start 1 *6 ACL start 2 *6 ACL gain 1 *6 Color difference-system Color difference voltage gain *7 Color difference frequency characteristics *7 B-Y axis gain adjusting range NTSC 1 *7 B-Y axis gain adjusting range NTSC 2 *7 B-Y axis gain adjusting range HD 1 *7 B-Y axis gain adjusting range HD 2 *7 Tint variable range Color control *7 Color residue *7 R-Y angle adjusting range *7
Note) *5: ABL SW: On, brightness: max. *6: ACL SW: On *7: Adjust tint, drive R, B.
ICs for TV
Symbol
Conditions
Min
Typ
Max
Unit
VABL3 AABL AACL1 AACL2 AACL3 AACL4
ABL/ACL pin: 3 V Level: min., gain: min. max. ABL/ACL pin: 5 V 3 V Level: typ., gain: max. ABL/ACL pin: 7.5 V Level: min., gain: min. max. ABL/ACL pin: 3 V Level: min. max., gain: typ. ABL/ACL pin: 3 V Level: min., gain: min. typ. ABL/ACL pin: 5 V 3 V Level: typ., gain: typ.
- 0.84 - 0.64 - 0.44 - 0.48 - 0.37 - 0.26 -5 10 -45 -34 0 20 -35 -22 +5 30 -25 -10
V V % % % %
GR fc GB-Y1 GB-Y2 GB-Y3 GB-Y4 TC CCON CMIN R
Input: Sine wave 0.2 V[p-p] f = 1 MHz, R-Y in R-out Input: Sine wave 0.2 V[p-p] f = 10 MHz B-Y gain: min., brightness: max. Tint SW: NTSC B-Y gain: max., brightness: max. Tint SW: NTSC B-Y gain: min., brightness: max. Tint SW: HD B-Y gain: max., brightness: max. Tint SW: HD Tint: min. max. B-Y gain, drive RB: Adjustment Color: typ. max. Contrast: typ. Color: min., B-Y gain: max. Contrast: max. R-Y axis: min. max.
9.5 -6 0.28 1.00 0.50 1.18 33 3 - 50 10
11.4 -3 0.45 1.25 0.78 2.00 48 6 0 17
13.7 +2 0.61 1.60 1.18 2.80 68 9
Times dB Times Times Times Times dB
+50 mV[p-p] 24
6
ICs for TV
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
Parameter Symbol Conditions Min Typ
AN5392FBQ
Max
Unit
Color difference-system (continued) Matrix ratio (G-Y/R-Y) HD *7 Matrix ratio (G-Y/R-Y) NTSC 1 *7 Matrix ratio (G-Y/R-Y) NTSC 2 *7 Matrix ratio (G-Y/R-Y) NTSC 3 *7 Matrix ratio (G-Y/B-Y) HD *7 Matrix ratio (G-Y/B-Y) NTSC 1 *7 Matrix ratio (G-Y/B-Y) NTSC 2 *7 Matrix ratio (G-Y/B-Y) NTSC 3 *7 OSD YS input threshold voltage *8 M/S input threshold voltage *8 YM input threshold voltage *8 CLP input threshold voltage Pulse width can be clamped OSD gain OSD frequency characteristics OSD contrast ratio 1 OSD contrast ratio 2 YSTH M/STH YMTH CLPTH WM GOSD fOSD OSDC1 OSDC2 Pin 36 > 2.1 V: OSD Pin 36 < 0.9 V: Main & sub Pin 55 > 2.1 V: Sub Pin 55 < 0.9 V: Main (M1, M2) Pin 35 > 2.1 V: Half tone Pin 35 < 0.9 V: Main & sub Pin 56, 60 (main, sub, OSD) Pin 6 (RGB) Pin 56, 60 (main, sub, OSD) Pin 6 (RGB) Input: Sine wave 0.2 V[p-p] f = 1 MHz, YS pin: 5 V Input: Sine wave 0.2 V[p-p] f = 30 MHz, YS pin: 5 V Contrast: max. typ. YS pin: 5 V Contrast: typ. min. YS pin: 5 V 0.9 0.9 0.9 0.9 0.8 5.0 -7 -3 -16 1.5 1.5 1.5 15 6.0 -3 -1 -11 2.1 2.1 2.1 2.1 7.2 +1 +1 -7 V V V V s Times dB dB dB M1 M2 M3 M4 M5 M6 M7 M8 Tint SW: HD G-Y matrix: HD Tint SW: NTSC G-Y matrix: NTSC 1 Tint SW: NTSC G-Y matrix: NTSC 2 Tint SW: NTSC G-Y matrix: NTSC 3 Tint SW: HD G-Y matrix: HD Tint SW: NTSC G-Y matrix: NTSC 1 Tint SW: NTSC G-Y matrix: NTSC 2 Tint SW: NTSC G-Y matrix: NTSC 3 0.23 0.38 0.26 0.26 0.07 0.15 0.22 0.13 0.30 0.51 0.34 0.34 0.10 0.19 0.28 0.17 0.35 0.58 0.40 0.40 0.13 0.23 0.34 0.21 Times Times Times Times Times Times Times Times
Note) *7: Adjust tint, drive R, B *8: SW priority: YS > M/S > M1/M2 (I2C), YS: YM is valid at low.
7
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
Parameter Y, U, V Y, U, V frequency characteristics Y, U, V output pedestal Y, U, V output pedestal potential difference Y, U, V matrix ratio 1 Y, U, V matrix ratio 2 Y, U, V matrix ratio 3 Cutoff drive BLK input threshold voltage*9 Neck mute input threshold voltage *9 CRT mute input threshold voltage *9 RGB mute input threshold voltage *9 DI input threshold voltage Cutoff variable range (R, B)*10 Cutoff variable range (G) Drive variable range (R, B) R, G, B pedestal potential difference Output blanking level I2C * DAC VTH VACK ADTH VPTH VCC2 = 5 V I = 3 mA, when pull-up is 1.6 k VCC2 = 5 V VCC2 = 5 V VCC2 = 5 V
(I2C) > BLK SW
ICs for TV
Symbol
Conditions Input: Sine wave 0.2 V[p-p], f = 30 MHz
Min -6 2.6 - 0.3
Typ -2 3.0 0 0.3 0.59 0.11
Max +2 3.4 +0.3 0.36 0.71 0.14
Unit
fYUV DCYUV VYUV MYUV1 MYUV2 MYUV3
dB V V Times Times Times
R-in: Sine wave 0.2 V[p-p], f = 1 MHz Y-out G-in: Sine wave 0.2 V[p-p], f = 1 MHz Y-out B-in: Sine wave 0.2 V[p-p], f = 1 MHz Y-out
0.24 0.47 0.08
BLKTH NTH CTH MTH DTH LRB LG GD VP BLK
BLK SW: On
0.9 0.9 0.9 0.9
1.5 1.5 1.5 1.5 1.5 2.0 1.0 11.5 0 1.5 2.2 1.5
2.1 2.1 2.1 2.1 2.1 2.4 1.3 14.0 +0.3 1.9
V V V V V V V dB V V
Pin 21 > 2.1 V: Detection inhibited Pin 21 < 0.9 V: Normal Cutoff R, B: min. max. Cutoff SW: min. max. Cutoff G: min. max. Drive R, B: min. max. Cutoff: typ., brightness: typ. BLK SW: On, BLK (pin 17): 5 V
0.9 1.6 0.7 9.0 - 0.3 1.1
SCL * SDA input threshold voltage Sink ability at ACK Maximum clock frequency Slave address changeover threshold voltage VP input threshold voltage
1.5 100 0.7 0.9
(I2C)
3.0 0.4 4.0 2.1
V V kHz V V
Note) *9: Priority: RGB mute, CRT mute, neck mute > single color adjustment *10: Drive R, B adjustment
> BLK pulse
8
ICs for TV
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
* Design reference data
AN5392FBQ
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter Y system Y (M1) input dynamic range Y (M2) input dynamic range Y (sub) input dynamic range R, G, B output dynamic range APL detection stop
Symbol
Conditions VCC1 = 9 V, V46 = 1.5 V Contrast: typ. VCC1 = 9 V, V46 = 1.5 V Contrast: typ. VCC1 = 9 V, V46 = 1.5 V Contrast: typ. VCC1 = 9 V for pedestal 3 V BLK, DI = 5 V BLK, delay from DI input Input signal: APL10% 90% DC regeneration pin: Open Band width 20 MHz -20C to +70C f = 5 MHz Input: Sine wave 0.2 V[p-p], f = 1 MHz
Min
Typ
Max
Unit
DYIN1 DYIN2 DYIN3 DOUT APLS DC4 S/N Y/T tdY AVM DCVM VPM/S
1.4 1.4 1.4 4.5 0 60 100 -56 2 15 1.0 3.9 50
V[p-p] V[p-p] V[p-p] V[p-p] V ns % dB % ns Times V mV
Black extension inhibition delay tHBLACK DC regeneration ratio 4 S/N Y output amplitude dependence on ambient temperature Y signal delay time VM out gain VM out pedestal level Pedestal level fluctuation at M/S changeover Color difference system Pr, Pb input (M1) dynamic range Pr, Pb input (M2) dynamic range Pr, Pb input (sub) dynamic range B-Y input (M1) dynamic range B-Y input (M2) dynamic range B-Y input (sub) dynamic range R-Y angle adjusting range 2 Color difference contrast ratio DCIN1 DCIN2 DCIN3 DPB1N DPB2N DPB3N R2 CCONT
At high speed switching within 1H period
Tint SW: HD mode Tint SW: HD mode Tint SW: HD mode Tint SW: NTSC mode Tint SW: NTSC mode Tint SW: NTSC mode R-Y axis: min. Contrast: min. max.

0.7 0.7 0.7 1.3 1.3 1.3 0 29

V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] dB
9
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
ICs for TV
Parameter
Symbol
Conditions -20C to +70C Tint SW: HD mode Contrast: max., color: typ. Tint SW: NTSC mode Contrast: max., color: typ. f = 5 MHz -20C to +70C
Min
Typ 2 1.3 1.0 30 4
Max
Unit Times Times ns %
Color difference system (continued) Tint dependence on ambient temperature (C-Y)/Y ratio HD (C-Y)/Y ratio NTSC Color difference signal delay time Color difference output amplitude ambient temperature dependence Cross-talk Y cross-talk Y (M1 M2) Y cross-talk (M1, M2 Sub) Y cross-talk (M1, M2, sub OSD) Color difference cross-talk (M1 M2) Color difference cross-talk Pr, Pb (M1, M2 Sub) Color difference cross-talk (M1, M2, sub OSD) Color difference cross-talk (OSD M1, M2, sub) Cross-talk between OSDs OSD OSD signal delay YS rise delay YS fall delay YM rise delay YM fall delay M/S rise delay M/S fall delay Pedestal fluctuation at YS changeover Pedestal fluctuation at YM changeover tdOSD tRYS tFYS tRYM tFYM tRM/S tFM/S VPYS VPYM YS: Variation amount from low to high YM: Variation amount from low to high f = 5 MHz 10 19 18 20 15 24 25 -60 -10 ns ns ns ns ns ns ns mV mV CT1 CT2 CT3 CT4 CT5 CT6 CT7 CT8 f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz f = 10 MHz -52 -54 -53 -52 -54 -52 -47 -42 dB dB dB dB dB dB dB dB TC/T C/YHD C/YNTSC tdC C/T
10
ICs for TV
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
* Design reference data
AN5392FBQ
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter OSD (continued) OSD input dynamic range
Symbol
Conditions
Min
Typ
Max
Unit
DOSD -20C to +70C
1.4 2
V[p-p] %
OSD output amplitude OSD ambient temperature dependency T Cutoff drive Drive variable range (G) Blanking delay Pedestal fluctuation to contrast variation Pedestal fluctuation to color variation Pedestal fluctuation to tint variation Output pedestal potential ambient temperature dependency Spot killer operation I2C DAC L1 L2 L3 L4 L5 GD tdBLK1 VPCONT VPCOLOR VPTINT VP T VSP
Drive G: min. max. BLK BLK output Contrast: min. max. Contrast: min. max.

2.6 40 0 0 0 -1.2 7.8

dB ns mV mV mV mV/C V
-20C to +70C Lower 9 V-system VCC, pin 33: C = 10 F 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) 1LSB = {data (max.) - data (min.)}/ (2N-1) R, G, B in Y, C-Y out, f = 5 MHz

4 * 5 * 6 DAC DNLE 8-bit DAC DNLE (excluding 40, 80, C0) 8-bit DAC DNLE (only for 40, 80, C0) 7-bit DAC DNLE (excluding 40) 7-bit DAC DNLE (only for 40) Y, U, V Y, U, V signal delay Y, U, V input dynamic range Y, U, V matrix ratio 4 Y, U, V matrix ratio 5 Y, U, V matrix ratio 6 Y, U, V matrix ratio 7
0.1 0.1 -1.0 0.1 -1.0
1.0 1.0 1.0 1.0 1.0
1.9 1.9 +2.0 1.9 +2.0
LSB Step LSB Step LSB Step LSB Step LSB Step
tdYUV DYUV MYUV4 MYUV5 MYUV6 MYUV7

5 1.4 0.7 - 0.3 - 0.59 - 0.59

ns V Times Times Times Times
R-in: Sine wave 0.2 V[p-p], f = 1 MHz R-Y out R-in: Sine wave 0.2 V[p-p], f = 1 MHz B-Y out G-in: Sine wave 0.2 V[p-p], f = 1 MHz R-Y out G-in: Sine wave 0.2 V[p-p], f = 1 MHz B-Y out
11
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25C (continued)
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
ICs for TV
Parameter Y, U, V (continued) Y, U, V matrix ratio 8 Y, U, V matrix ratio 9
Symbol
Conditions
Min
Typ - 0.11 0.89
Max
Unit
MYUV8 MYUV9
B-in: Sine wave 0.2 V[p-p], f = 1 MHz R-Y out B-in: Sine wave 0.2 V[p-p], f = 1 MHz B-Y out
Times Times
s Terminal Equivalent Circuits
Pin No. 1 2 Equivalent circuit Description GND: GND pin * Pin 1: I2L GND pin * Pin 2: Y,U,V R,G,B conversion circuit GND pin * Pin 16: Pulse-system GND pin * Pin 23: Main signal-system GND pin * Pin 24: R signal output circuit GND pin * Pin 27: B signal output circuit GND pin * Pin 30: G signal output circuit GND pin * Pin 64: Input circuit GND pin Y, R-Y, B-Y out: Y, R-Y, B-Y output pin for R, G, B Y, U, V conversion circuit * Pin 3: B-Y output pin * Pin 4: Y output pin
Pins 3, 4, 5
1 24
2 27
16 30
23 64
3 4 5
VCC 9 V (R,G,BY,U,V VCC /pin 10) 200 A 200
80
200 A
200
* Pin 5: R-Y output pin * Output dynamic range: 1.5 V to 7.5 V * Output pedestal is about 3 V. * Recommended use range: -4 mA to +4 mA CLP (R, G, B) in:
6
VCC 9 V (R,G,BY,U,V VCC /pin 10) 40 A
Clamp pulse input pin for R, G, B Y, U, V conversion circuit * Input threshold voltage: 1.5 V (to clamp at high) * Clamps the signal inputted from the next pin Pin 7, pin 8, pin 9 * Recommended clamp pulse width NTSC: 2.5 s HD: 1.0 s * Recommended use range: 0 V to 5 V
6 5V
200 40 A 2.25 V
0V
12
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 7 8 9
0.7 V[0-p]
AN5392FBQ
Equivalent circuit
Description R, G, B in: R, G, B input pin for R, G, B Y, U, V conversion circuit * Pin 7: R signal input pin * Pin 8: G signal input pin * Pin 9: B signal input pin * Input 0.7 V[0-p] for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation on white balance with user volume. * Clamps the input signal with pin 6 clamp pulse * Recommended use range: Do not apply DC voltage from outside. VCC 9 V: Signal-system power supply pin * Pin 10: Power supply pin for Y, U, V R, G, B conversion circuit (pair with Pin 2 GND) * Pin 26: R signal output circuit power supply pin (pair with pin 24 GND) * Pin 29: B signal output circuit power supply pin (pair with pin 27 GND) * Pin 32: G signal output circuit power supply pin (pair with pin 30 GND) * Pin 47: Main power supply pin (pair with pin 23 GND) * Pin 54: Input circuit power supply pin (pair with pin 64 GND) * Apply 9 V for use. * Recommended use range: 8.1 V to 9.9 V
VCC 9 V (R,G,BY,U,V VCC /pin 10) 1 k 1 k
4.5 V Pins 7, 8, 9 NP, 1 F 200 40 A 3.75 V 400 A
10
9V
Pins 10, 26, 29 32, 47, 54 Circuit
47 F
0.01 F
13
AN5392FBQ
s Terminal Equivalent Circuits (continued)
Pin No. 11
VCC 5 V (I2L VCC /pin 15) 5V 0V 11 200 5 k 500 40 k 40 A 40 A 1.5 V
ICs for TV
Equivalent circuit
Description VP in: V-latch DAC VP pulse input pin * Input threshold voltage: 1.5 V High input: V11 > 2.1 V Low input: V11 > 0.9 V * The data for color, tint, brightness and contrast are rewritten at the timing of high-tolow-going VP pulse in DAC SW13-6 (V-latch mode). In the through mode, the data are rewritten at the timing of the data sent, regardless of VP pulse. * This pin does not affect a blanking operation. * Recommended use range: 0 V to 5 V Slave address SW: Slave address changeover pin for this IC * V12 = 5 V: Slave address 86 V12 = 0 V: Slave address 84 Set a slave address carefully so as not to overlap with the other ICs in the same set. * Recommended use range: 0 V to 5 V SDA: I2C bus data input pin * Input threshold voltage: 2 V * Recommended use range: 0 V to 5 V
12
VCC 5 V (I2L VCC /pin 15) DC 0 V to 5 V 41 k 12 20 k
13
VCC 5 V (I2L VCC /pin 15) 20 A 3.25 V Data 13 200 2.75 V 1 k 50 A
14
VCC 5 V (I2L VCC /pin 15) 3.25 V Data 14 1 k 200 20 A 50 A 2.75 V
SCL: I2C clock input pin * Input threshold voltage: 2 V * Recommended use range: 0 V to 5 V
15
5V
Pins 15, 22 Circuit
47 F
0.01 F
VCC 5 V: Power supply pin for I2L and pulse-system * Pin 15: I2L power supply pin (pair with pin 1 GND) * Pin 22: Pulse-system power supply pin (pair with pin 16 GND) * Apply 5 V for use. * Recommended use range: 4.5 V to 5.5 V
14
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 16 17
5V 0V 17 200
AN5392FBQ
Equivalent circuit Refer to pin 1
VCC 5 V (pulse VCC /pin 22) 16 A 40 A 2.25 V
Description Refer to pin 1 BLK in: BLK input pin * Input threshold voltage: 1.5 V High-level input: V17 2.1 V Low-level input: V17 0.9 V * Gives BLK to R, G, B output at input = high * Inhibits black gradation correction, white gradation correction and APL detection (DC transfer amount correction) at input = high. * Recommended use range: 0 V to 5 V
500
5 k
18 19 20
5V 0V Pins 18, 19, 20
VCC 5 V (pulse VCC /pin 22) 16 A 40 A
200
500
5 k
R, G, B mute, neck mute, CRT mute: Input pin for R, G, B mute, neck mute, CRT mute * Pin 18: R, G, B mute * Pin 19: Neck mute * Pin 20: CRT mute * Input threshold voltage: 1.5 V 2.25 V High-level input: V18,19,20 2.1 V Low-level input: V18,19,20 0.9 V * If input is high, R, G and B output are forcibly given BLK. And as pin 18, pin 19 are ORed, BLK is given whenever any of those pins are given high level. At this time, BLK in (pin 17), BLK-SW (I2C) and single color adjustment SW (I2C) become invalid. * Recommended use range: 0 V to 5 V DI in: DI input pin * Input threshold voltage: 1.5 V High-level input: V21 2.1 V Low-level input: V21 0.9 V * Inhibiting black gradation correction, white gradation correction and APL detection (DC transmission amount correction) at input = high. * Recommended use range: 0 V to 5 V Refer to pin 15 Refer to pin 1 Refer to pin 1
21
5V 0V 21
VCC 5 V (pulse VCC /pin 22) 16 A 40 A 2.25 V
200
500
5 k
22 23 24
Refer to pin 15 Refer to pin 1 Refer to pin 1
15
AN5392FBQ
s Terminal Equivalent Circuits (continued)
Pin No. 25 Equivalent circuit
VCC 9 V (R,G,B output VCC/pins 26, 29, 32)
ICs for TV
Description R, G, B out: R, G, B output pin * Pin 25: R output pin * Pin 28: B output pin * Pin 31: G output pin * Output dynamic range: 1.5 V to 7.5 V * Use output pedestal typ. value of approx. 3 V. * Recommended use range: -4 mA to +4 mA
200 A
50
80 Pins 25, 28, 31 200 A 50
26 27 28 29 30 31 32 33
Refer to pin 10 Refer to pin 1 Refer to pin 25 Refer to pin 10 Refer to pin 1 Refer to pin 25 Refer to pin 10
VCC 9 V (G output VCC /pin 32) 10 k 1.75 k 33 10 F 100 k VCC 9 V
Refer to pin 10 Refer to pin 1 Refer to pin 25 Refer to pin 10 Refer to pin 1 Refer to pin 25 Refer to pin 10 Spot killer in: Spot killer pin * Use this pin to discharge electricity on CRT swiftly when the set is turned off. * This pin raises DC voltage of R, G, B output pins (pin 25, pin 28, pin 31) when G output VCC 9 V (pin 32) is lowered. R, G, B limiter in: R, G, B output upper limiter pin * Limits R, G, B output pin voltage (pin 25, pin 28, pin 31) so as not to become higher than pin 34 voltage plus 1 VBE. * Recommended use range: 3 V to 9 V
To RGB output circuit
34
VCC 9 V (G output VCC /pin 32) DC 3 V to 9 V 34 5 k
RGB output circuit
66 A
35
VCC 5 V (pulse VCC /pin 22) 40 A
35 5V 0V
200 2.25 V
40 A
YM in: Half tone switching signal input pin * Input threshold voltage: 1.5 V 1) 2.1 V < V35 Lowers the signal amplitude inputted from M1, M2 and sub by 9 dB. 2) V35 < 0.9 V Normal * Priority order of signal switching M1/M2 (I2C SW) < M/S < YM < YS * Recommended use range: 0 V to 5 V
16
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 36 Equivalent circuit
VCC 5 V (pulse VCC /pin 22) 40 A
AN5392FBQ
Description YS in: OSD signal switching signal input pin * Input threshold voltage: 1.5 V 1) 2.1 V < V36 Outputs OSD signal inputted from pin 37, pin 38, pin 39. 2) V36 < 0.9 V Normal * Signal switching priority order M1/M2 (I2C SW) < M/S < YM < YS * Recommended use range: 0 V to 5 V OSD in: OSD signal input pin for analog signal * Pin 37: B signal input pin * Pin 38: G signal input pin * Pin 39: R signal input pin * Input signal typ. is 0.7 V[0-p] from black to white level. * Drive with a low impedance. * Clamps the input signal with the clamp pulse of the following pins: Pin 56, I2C bus M1/M2 switch: M1 Pin 60, I2C bus M1/M2 switch: M2 * Recommended use range: Do not apply DC voltage from outside.
36 5V 0V
200 40 A 2.25 V
37 38 39
0.7 V[0-p]
VCC 9 V (main VCC /pin 47) 1 k 1 k
3.75 V NP, 1 F Pins 37 38 39
200
40 A
3.0 V
500 A
40 41 42
VCC 9 V (main VCC /pin 47) 2 k DC voltage Pins 40 41 42 1 k
200
0.1 F
14 k 200 3V 1 k
B, G, R CLP: Pin to clamp the main signal with the voltage proportioned to bright data. * Pin 40: B signal clamp pin 400 A * Pin 41: G signal clamp pin * Pin 42: R signal clamp pin * Shorten the distance from the pin to the 3.75 V external capacitor. * Recommended use range: 0 V to 5 V (Do not apply the DC voltage from outside.) 1 k 1 k APL det.: Main signal APL detection pin * Output the voltage in proportion to the APL of main signal * Fit an RC filter to this pin. R: adjusts detection sensitivity C: adjusts tracking characteristics * Recommended use range: 0 V to 3 V
43
VCC 9 V (main VCC /pin 47) 3 k 50 A DC voltage 43 C R 200 200 3V 3 k
17
AN5392FBQ
s Terminal Equivalent Circuits (continued)
Pin No. 44
9V CR VCC 9 V (main VCC /pin 47) 50 A 200 44 DC voltage 200 200
ICs for TV
Equivalent circuit
Description White peak det.: Detects the brightest level of main signal 200 A * Fit an external RC filter between this pin and VCC * Carrying out white gradation correction and blooming control with this detection voltage R: Adjusts detection sensitivity C: Adjusts tracking characteristics * Recommended use range: 0 V to 9 V
40 A
250 50 4 k k
45
VCC 9 V (main VCC /pin 47) 40 A 1.5 k 6 k
DC voltage 45 C R
200 200
300 7 k 300 A 40 A 18 pF
Black peak det.: Detects the darkest level of main signal * Fit an external RC filter * Carries out black gradation correction with this detected voltage R: Adjusts detection sensitivity C: Adjusts tracking characteristics * Recommended use range: 0 V to 9 V
46
VCC 9 V (main VCC /pin 47) 100 A DC voltage 46 5.25 V 100 50 A A 24 k 50 A 3.3 k 1 k 300
Blooming level in: Input pin to determine a blooming level Output clip level
3V
5V
* Recommended use range: 1.5 V to 5 V 47 Refer to pin 10 Refer to pin 10
18
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 48 Equivalent circuit
VCC 9 V (main VCC /pin 47) 50 A DC voltage 48 50 A 4 k 4 k
AN5392FBQ
Description DC regeneration ratio: Pin to determine DC regeneration ratio * Adjusting DC regeneration ratio with the resistor to be connected between this pin and GND * DC regeneration ratio comes closer to 100% when R is raised. * Recommended use range: 0 A to -200 A
200
5.5 V 63 A
49
VCC 9 V (main VCC /pin 47) 200 A 50
80
VM out: VM output pin * Output dynamic range: 1.5 V to 7.5 V * Use output pedestal typ. value of approx. 3 V * Recommended use range: -4 mA to +4 mA
49
200 A
50
50
VCC 9 V (main VCC /pin 47) 3.5 V 100 A 3.5 V 100 A
DC voltage 50
40 k 5.2 k 7V 4 k 5.2 k
40 k
7V 4 k
ABL/ACL in: Control voltage input pin for ABL/ACL * Apply the voltage inversely proportioned to CRT screen brightness * Operating range is 7 V to 2 V * Possible to control contrast and brightness in inverse proportion to the applied voltage (controlling main signal and OSD signal) * Recommended use range: 0 V to 9 V
51
VCC 9 V (Y,U,V VCC /pin 54) 0.35 V 1 k 1 k
4.5 V Pins 51, 53 NP, 1 F 200 16 A 3.75 V 400 A
R-Y (S) in, B-Y (S) in: Sub signal R-Y,B-Y input pin * Pin 51: R-Y (S) signal input pin * Pin 53: B-Y (S) signal input pin * Input 0.35 V for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation of white balance with the user volume. * Clamps the input signal with the clamp pulse of the following pins: Pin 56, I2C bus M1/M2 switch: M1 Pin 60, I2C bus M1/M2 switch: M2 * Recommended use range: Do not apply DC voltage from outside. 19
AN5392FBQ
s Terminal Equivalent Circuits (continued)
Pin No. 52
VCC 9 V (Y,U,V VCC /pin 54) 0.7 V[0-p] 1 k 1 k
ICs for TV
Equivalent circuit
Description Y (S) in: Sub signal Y input pin * Input 0.7 V[0-p] (B-W) for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation of white balance with the user volume. * Clamps the input signal with the clamp pulse of the following pins: Pin 56, I2C bus M1/M2 switch: M1 Pin 60, I2C bus M1/M2 switch: M2 * Recommended use range: Do not apply DC voltage from outside Refer to pin 51 Refer to pin 10 M/S in: M/S (main/sub) switching signal input pin * Input threshold voltage: 1.5 V 1) 2.1 V < V55 Outputs the signal inputted from M1 or M2. 2) V55 < 0.9 V Outputs the signal inputted from M1 or M2.
2.25 V
Note) If you switch over a multi-screen in a high speed within 1H period, WB will be changed. Be careful on use. The degree of WB changes depending upon the setting of DAC.
4.5 V NP, 1 F 52
200
40 A
3.75 V
400 A
53 54 55
Refer to pin 51 Refer to pin 10
VCC 9 V (Y,U,V VCC /pin 54) 40 A
55 5V 0V
200
40 A
* Priority order of signal switching over M1/M2 (I2C SW) < M/S < YM < YS * Recommended use range: 0 V to 5 V 56
VCC 9 V (Y,U,V VCC /pin 54) 40 A
56 5V 0V
200 2.25 V
40 A
CLP (M1) in: Main signal (M1) signal clamp pulse input pin * Input threshold voltage: 1.5 V (clamps at high) * Clamps the signal inputted from the next pin Pin 57, pin 58, pin 59 * Recommended clamp pulse width NTSC: 2.5 s, HD: 1.0 s * Recommended use range: 0 V to 5 V
20
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 57
VCC 9 V (Y,U,V VCC /pin 54) 0.35 V 1 k 1 k
AN5392FBQ
Equivalent circuit
Description R-Y (M1) in, B-Y (M1) in: Main (M1) signal R-Y, B-Y input pin * Pin 57: R-Y (M1) signal input pin * Pin 59: B-Y (M1) signal input pin * Input 0.35 V for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation of white balance with the user volume. * Clamps the input signal with the clamp pulse of pin 56: * Recommended use range: Do not apply DC voltage from outside. Y (M1) in: Main signal (M1) Y input pin * Input 0.7 VBW for both HD and NTSC. * Drive this pin with a low impedance. If it is driven with a high impedance, WB is likely to be changed. * Clamps the input signal with pin 56 clamp pulse. * Recommended use range: Do not apply DC voltage from outside.
4.5 V Pins 57, 59 NP, 1 F 200 16 A 3.75 V 400 A
58
0.7 V[0-p]
VCC 9 V (Y,U,V VCC /pin 54) 1 k 1 k
4.5 V NP, 1 F 58
200
40 A
3.75 V
400 A
59 60
Refer to pin 57
VCC 9 V (Y,U,V VCC /pin 54) 40 A
Refer to pin 57 CLP (M1) in: Main (M2) signal clamp pulse input pin * Input threshold voltage: 1.5 V (clamps at high) * Clamps the signal inputted from the next pin. Pin 61, pin 62, pin 63 * Recommended clamp pulse width NTSC: 2.5 s HD: 1.0 s * Recommended use range: 0 V to 5 V
60 5V 0V
200 2.25 V
40 A
21
AN5392FBQ
s Terminal Equivalent Circuits (continued)
Pin No. 61
VCC 9 V (Y,U,V VCC /pin 54) 0.35 V 1 k 1 k
ICs for TV
Equivalent circuit
Description R-Y (M2) in, B-Y (M2) in: Main (M2) signal R-Y, B-Y input pin * Pin 61: R-Y (M2) signal input pin * Pin 63: B-Y (M2) signal input pin * Input 0.35 V for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation of white balance with the user volume. * Clamps the input signal with the clamp pulse of pin 60: * Recommended use range: Do not apply DC voltage from outside. Y (M2) in: Main (M2) signal Y input pin * Input 0.7 VBW for both HD and NTSC. * Drive this pin with a low impedance. High impedance is likely to cause variation of white balance with the user volume. * Clamps the input signal with the clamp pulse of pin 60: * Recommended use range: Do not apply DC voltage from outside.
4.5 V Pins 61, 63 NP, 1 F 200 16 A 3.75 V 400 A
62
VCC 9 V (Y,U,V VCC /pin 54) 0.7 V[0-p] 1 k 1 k
4.5 V NP, 1 F 62
200
40 A
3.75 V
400 A
63 64
Refer to pin 61 Refer to pin 1
Refer to pin 61 Refer to pin 1
22
ICs for TV
s Application Circuit Example (Basic Circuit)
AN5392FBQ
18 k
DC regenaration rate Analog VCC (9 V) Blooming level in
R, G, B limiter in
VCC 9V
4.7 F
82 k
10 F
White peak det. APL det.
Black peak det.
OSD-G in
OSD-R in
OSD-B in YS in
G-CLP
270 k
R-CLP
B-CLP
Spot killer in 33
V34
22 F
YM in
6.4 k
48
47
46
45
44
41
40
39
37
36
35
43
42
VM out ABL/ACL in R-Y (S) in Y (S) in B-Y (S) in Y, U, V VCC (9 V) M/S in CLP (M1) in R-Y (M1) in Y (M1) in B-Y (M1) in CLP (M2) in R-Y (M2) in Y (M2) in B-Y (M2) in Y, U, V GND
49
V50
38
34
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
ABL/ACL block
R Y R
VCC 9 V
V46
10 F
32 31 30 29 Output block 28 27 26 25 Video block
Y
G-VCC (9 V) G-out G-GND B-VCC (9 V) B-out B-GND R-VCC (9 V) R-out R-GND Analog GND Pulse VCC (5 V) DI in CRT mute Neck mute R,G,B mute BLK in
Matrix block
G B
SW block
G B
R-Y
R-Y
Input block
24 23 22 21 20 19 18 17
Chrominance G-Y block B-Y B-Y
R, G, B Y, U, V block
I2C
DAC block
BLK block
10
11
12
13
14
15 I2L V
R,G,B VCC (9 V)
I2L GND
Slave address SW
R,G,B GND
CC (5 V)
VP in
SDA
CLP (R, G, B) in
Pulse GND
B-Y out
Y-out
R-Y out
SCL
R-in
G-in
B-in
16
1
2
3
4
5
6
7
8
9
23

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