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APLUS
MAKE YOUR PRODUCTION A-PLUS
ASM12712C DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail: Mr. Jason sales@aplusinc.com.tw Technology E-mail: Mr. George service@aplusinc.com.tw
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
ASM12712C
ASM12712C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description The ASM12712C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5V Internal Program ROM: 4K x 10-bit 1 sets of 19-bit DPR can access up to 512K x 10 bits data memory space Data Registers: * 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 4-bit Output Port B (2Dh) * PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction * One 8-bit COUT output for ASMxxxxx
1
ASM12712C
FIGURE 1.1 : Block Diagram of ASM12712C
Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[18:12]) =0000000b ADDR[18:0] Stack(12) (2-Level) 0 ROM_ADDR[18:0] 1 DPR3,2,1 DPR[18:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder
PCLATCH(8) PCH(8)
DLATCH(10) ROM_Data[9:0]
Data Bus[3:0] Accumlator(4)
Instruction Bus [9:0]
SRAM
ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh
Timer0(9)
PRA(4) PRB(4) PRC(4)
P1,P2,P3,P4 enter test mode
( Voice synthesizer )
Clock Generator Test select Power on Reset RESET pin PRA0
weak or strong pull-low for PRA, PRB, PRC OSC VDD/GND PRASL(4)
One-Channel
Reset Chip Reset Chip
COUT
COUT
2
Instruction Bus [9:0]
Control Signal
ASM12712C
FIGURE 1.2 : External ROM Map of ASM12712C
PC[11:0]
12bit x 2 STACK 19-bit Data Pointer Reset Vector
00000h
00080h
Reserved for Testing
Program and data ROM
00080h-003FFh 00400h 00000h-00FFFh
00000h-7FFFFh
00FFFh(4K)
Data ROM
7FFFFh(512Kx10-bits)
3
ASM12712C
1.2 Pin-Out ASM12712C Pin-Out
VDD3 PRC1 PRC0/RESET PRA3-1 PRA0/RESET I I I I/O I/O STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Std./O.D. STI Std./O.D. Third Power supply during operation Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Third Circuit Ground Potential
OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 GND3
I I O I I O I O I I
1.3 Application circuit
4
ASM12712C
1.4 Bonding Diagram
(256K x 10 bit) x 2-B lock R O M
ASM12712C
Y= 3140 + 100 (um)
C H IP SIZE: X= 309 0 + 100 (u m), Y = 314 0 + 100 (u m)
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15 16 17 18 19 20 21
X= 3090 + 100 (um)
ASM12712C Pad Location
PAD# PAD Name X Y Chip Size: X= 3090 + 100 (um) , Y= 3140 + 100 (um) PAD # PAD Name X Y
1 2 3 4 5 6 7 8 9 10 11
VDD3 RC_PAD[1] RC_PAD[0]
RA_PAD[3]
RA_PAD[2] RA_PAD[1]
RA_PAD[0]/RESET
AOSC_PAD VDD1 ACOUT GND1
-1445.96 -1325.24 -1202.92 -1080.6 -958.28 -835.96 -713.64 -591.32 -414.36 -162.24 38.72
-1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1450.56
12 13 14 15 16 17 18 19 20 21
GND2 TEST_PAD VDD2 RB[0] RB[1] RB[2] RB[3] RC_PAD[2] RC_PAD[3] GND3
118.72 319.68 575.32 714.48 836.8 959.12 1081.44 1203.76 1326.08 1449.36
-1450.56 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08 -1456.08
5
ASM12712C
1.5 DC Characteristics for ASMXXXX SYMBOL VDD Isb Iop PARAMETER OPERATING VOLTAGE SUPPLY CURREN T
STANDBY OPERATING
VDD MIN. TYP. MAX. UNIT 2.4 3 5 3 5 3 5 5 3 5 3 5 -10 -20 3 5 1 1 2 7 3 9 -5.2 -3 -8 7 20 10 20 V uA mA
CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) 4MHz, RM (IO ports) Fosc(3v)Fosc(2.4v) Fosc (3v) VDD=3V, Rosc=740k, 4MHz
Iih
INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT FREQUENCY STABILITY Fosc VARIATION
uA
Ioh Iol dF/F dF/F
mA
% %
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm) 3v Freq.(MHz)
1200
2.47
1000
3.04
820
3.31
470
6.25
Rosc & Freq. 8 Freq. MHz 6 4 2 0 0 200 400 600 800 1000 1200 1400 Rosc k ohm 6.25 3.31 3.04
2.47
6

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