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AT91RM9200 Development Kit
..............................................................................................
User Guide
Table of Contents
Section 1 Overview............................................................................................... 1-1
1.1 1.2 1.3 Scope ........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91RM9200 Development Board ....................................................1-1
Section 2 Setting Up the AT91RM9200 Development Board ............................... 2-1
2.1 2.2 2.3 2.4 2.5 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Powering Up the Board .............................................................................2-1 Connecting the Board ...............................................................................2-2 Getting Started with the AT91RM9200 .....................................................2-3
Section 3 Board Description ................................................................................. 3-1
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 AT91RM9200 Processor...........................................................................3-1 Memory .....................................................................................................3-2 Memory Card ............................................................................................3-2 Clock Circuitry and Analog Functions .......................................................3-2 Reset Circuitry...........................................................................................3-2 Power Supply Circuitry..............................................................................3-2 Remote Communication............................................................................3-3 User Interface ...........................................................................................3-3 Expansion Slots ........................................................................................3-3 Debug Interface ........................................................................................3-3
Section 4 Configuration Straps ............................................................................. 4-1
4.1 Configuration Straps and Jumper Settings ...............................................4-1
Section 5 Schematics ........................................................................................... 5-1
5.1 Schematics ...............................................................................................5-1
AT91RM9200 Development Kit User Guide
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Table of Contents
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AT91RM9200 Development Kit User Guide
Section 1 Overview
1.1
Scope
The AT91RM9200 Development Board enables real-time code development and evaluation. It supports the AT91RM9200 ARM9-based 32-bit RISC microcontroller. This guide focuses on the AT91RM9200 Development Board as an evaluation and demonstration platform:
n Section 1 is this overview. n Section 2 gives information on setting up the installation. n Section 3 contains a description of the development board. n Section 4 details the configuration straps. n Section 5 shows board schematics.
1.2
Deliverables
The development kit is delivered with:
n One AC adapter 100 - 240V ~ 1.0A, 50 - 60 Hz n One modem RS232 cable n One RJ45 Ethernet crossed cable n One A/B-type USB cable n Two power supply cables, one US format, one French format n One CD-ROM containing summary and full datasheets, datasheets with electrical and mechanical characteristics, application notes and getting started documents for all development boards and AT91 microcontrollers. An AT91 software package with C and assembly listings is also provided. This allows the user to begin evaluating the AT91 ARM(R) Thumb(R) 32-bit microcontroller quickly.
1.3
The AT91RM9200 The board consists of an AT91RM9200 together with the following: Development n 2M bytes of parallel Flash memory Board
n Four banks of 2M x 32-bit SDRAM n 128K bytes of EEPROM with two-wire interface access
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Overview
n 8M bytes of serial DataFlash(R) n Five communication ports (USB host and device, Ethernet, serial and IrDA) n Graphic controller with output to a standard VGA monitor n JTAG/ICE, ETM and debug interface n Expansion connector
Figure 1-1. AT91RM9200 Development Board Block Diagram
LCD Panel Slot SmartMedia Slot FingerChip Socket
LCD Panel Slot
Compact Flash Slot
16
Extension Slot VGA Connector Graphic Display Controller
Flash
Clock Controller Buzzer Ethernet PHY Ethernet Port
32
SDRAM
DataFlash
EEPROM LED
EBI USB Host Port UHP
SPI
TWI
TWI
EMAC JTAG
ICE Debug Port
AT91RM9200
USB Device Port UDP NRST USART MCI or SPI USART TWI SSC SSC
ETM Trace Port DBGU RS232 Driver
PIOA PIOB PIOC
Oscillator, PLL and Reset
SDCard Socket
RS232 Driver
Si3044 Line Interface Chipset
Extension Slot Extension Slot Extension Slot
DC Input
Power Supply
Smart Card Socket
IrDA Trasnceiver
User Analog Inputs
ADC
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AT91RM9200 Development Kit User Guide
Section 2 Setting Up the AT91RM9200 Development Board
2.1
Electrostatic Warning
The AT91RM9200 development board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
In order to connect the AT91RM9200 development board, the following elements are required:
n The AT91RM9200 development board itself n Power supply cable capable of supplying 7V to 12V at 1A (not supplied)
2.3
Powering Up the Board
DC power is supplied to the board via the 2.1 mm socket (J1). The polarity of the power supply is not critical. The minimum voltage required is 7V. The board has a voltage regulator providing +3.3V. The regulator allows the input voltage range to be from 7V to 12V.
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Setting Up the AT91RM9200 Development Board
2.4
Connecting the Board
n Using the RS232 cable supplied in the AT91RM9200-DK kit, connect the board to your PC via the Serial Debug Port (J23). n Start the HyperTerminal application: n In the window Connection Description, enter a name for the connection, e.g., "RM9200K_DBGU".
n Click on OK. n In the window Connect To, click on the drop-down list arrow at Connect using:. Select the COM port used.
n Click on OK. n Set the serial parameters of the COM port as follows:
- Bit rate: 115 kbps - Data bit: 8 - Parity: NONE - Stop bit: 1 - Flux control: NONE
n Click on OK.
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AT91RM9200 Development Kit User Guide
Setting Up the AT91RM9200 Development Board
n The AT91RM9200-DK and your PC are connected, as indicated in the lower left-hand corner of the console and by the title bar.
n Press the RESET button on the board. n A message is sent from the board to the HyperTerminal console. Note that this message can vary depending on the version of Zooboot.
2.5
Getting Started with the AT91RM9200
The AT91RM9200 Development Kit is delivered with a CD-ROM containing all necessary information and step-by-step procedures for working with the most common development toolchains. Please refer to this CD-ROM, or to the AT91 web site, http://www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91RM9200.
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Section 3 Board Description
3.1
AT91RM9200 Processor
n Incorporates the ARM920TTM ARM(R) Thumb(R) Processor
- 200 MIPS at 180 MHz - 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer - Memory Management Unit - In-circuit Emulator including Debug Communication Channel - Mid-level Implementation Embedded Trace Macrocell
n Additional Embedded Memories
- 16K Bytes of SRAM and 128K Bytes of ROM
n External Bus Interface (EBI)
- Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash(R), SmartMediaTM and NAND Flash
n System Peripherals:
- Enhanced Clock Generator and Power Management Controller - Two On-chip Oscillators with Two PLLs - Very Slow Clock Operating Mode and Software Power Optimization Capabilities - Four Programmable External Clock Signals - System Timer Including Periodic Interrupt, Watchdog and Second Counter - Real-time Clock with Alarm Interrupt - Debug Unit, Two-wire UART and Support for Debug Communication Channel - Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected - Seven External Interrupt Sources and One Fast Interrupt Source - Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain Capability on Each Line - 20-channel Peripheral Data Controller (DMA)
n Ethernet MAC 10/100 Base-T n USB 2.0 Full Speed (12 M-bits per second) Host Double Port and Device Port
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Board Description
n Multimedia Card Interface (MCI) n Three Synchronous Serial Controllers (SSC) n Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) n Master/Slave Serial Peripheral Interface (SPI) n Two 3-channel, 16-bit Timer/Counters (TC) n Two-wire Interface (TWI) n IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
3.2
Memory
n 2-Mbyte parallel Flash memory n Four banks of 2M x 32-bit SDRAM n 128-Kbyte EEPROM with 2-wire interface n 8-Mbyte serial DataFlash
3.3
Memory Card
n SD Card/MMC
- Supports MultiMedia and SD Card - Analog switches provide support for DataFlash Card
n Smart Media(R) Socket n CompactFlash(R) Socket n Smart Card Interface
3.4
Clock Circuitry and Analog Functions
n 32.768 kHz standard crystal for the AT91RM9200 n 18.432 MHz standard crystal for the AT91RM9200 n 50 MHz CMOS oscillator for the Display Controller n Temperature sensor n Analog-to-digital converter n FingerChip (Socket only)
3.5
Reset Circuitry
n Reset Controller
3.6
Power Supply Circuitry
n 3.3V DC/DC converter n 1.8V DC/DC converter
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Board Description
3.7
Remote Communication
n Fast Ethernet Physical Layer Single Chip Transceiver n IrDA Transceiver n Host Interface via RS-232 DB9 male socket n Line interface n Debug Port via RS-232 DB9 connector n Host and Device USB socket
3.8
User Interface
n Graphic Display Controller n TFT/SNT panel socket n 15-pin standard socket for an external VGA monitor n On-board buzzer and one LED managed via general PIO lines
3.9
Expansion Slots
n Three expansion slots give access to all the microcontroller's signals
3.10
Debug Interface
n 38-pin trace Port socket n 20-pin JTAG interface connector n Serial Debug Unit
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Section 4 Configuration Straps
4.1
Configuration Straps and Jumper Settings
Table 4-1 gives details on configuration straps and jumper settings on the AT91RM9200 development board and their default settings. Table 4-1. Configuration Straps and Jumper Settings
Designation S1 S3 S4 Default Setting Closed Closed Closed Feature The earth plane and the GDN potential are connected. The ETM reset (NSRST) and the System Reset (NRST) are connected. The PD6/DTXD PIO line is connected to the READY/NBUSY output signal of the SPI DataFlash (MN13). The Write Protect feature of the SPI DataFlash (MN13) is disabled. The PA26/TWCK/IRQ1 signal is connected to three remote devices (MN14, MN33, MN34). The PA25/TWD/IRQ2 signal is connected to three remote devices (MN14, MN33, MN34). The PA3/NPCS0/IRQ5 output signal is not connected to the NCS of the serial DataFlash (MN13). The PA5/NPCS2/TXD3 signal is connected to the 10-bit SPI ADC (MN15). The PC15 I/O line is connected to the 10-bit ADC to read the End Of Conversion event (MN15). Not Used: The PS2 Controller is not installed. Not Used: The PS2 Controller is not installed. The PB12/TF2/ETX2 signal is connected to the NRGDT/FSD output signal of the Line Interface (MN23). The PB16/RK2/ERX2 signal is connected to the NOFHK input signal of the Line Interface (MN23). The PB17/RF2/ERXDV signal is connected to the NFSYN input signal of the Line Interface (MN23).
S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
Opened Closed Closed Opened Closed Closed Closed Closed Closed Closed Closed
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Configuration Straps
Table 4-1. Configuration Straps and Jumper Settings
Designation S16 S17 S18 S19 S20 S21 S22 S23 Default Setting Closed Closed Closed Closed Closed Closed Closed Closed Feature The PB13/TK2/ETX3 signal is connected to the SCLK output signal of the Line Interface (MN23). The PB15/RD2/ERX2 signal is connected to the SDO output signal of the Line Interface (MN23). Not Used: The Front End AC97 is not installed. The PA30/DRXD/CTS2 signal is connected to the receive buffer output of the DBGU transceiver (MN26). The AT91RM9200's PC14 PIO line is connected to the NREADY output signal of the Smart Card Interface (MN29). The PA17/TXD0/TIOA0 is connected to the DATA input/output signal of the Smart Card Interface (MN29). The PA22/RXD2/TIOB2 is connected to the RX output signal of the IrDA Transceiver (MN30). Enables all output signals (DCD1, DSR1, RXD1, CTS1, RI1) of the Transceiver (MN28) used for the RS232 Port COM. The PD4/ETXEN input line is connected to the USB device socket (J28) to detect a host connection. The System Reset signal (NRST) is connected to the ICE/JTAG socket (J8, pin 15). The NCS2 output signal is connected to the display controller (MN32). The NCS0 output signal is connected to the parallel Flash memory (MN21). Enables the OE signal from the Atmel FingerChip (MN31). Only the socket is installed. The SMCS/NCS3 output signal is connected to the bidirectional buffer used by the Smart Media Connector (MN20B). The PA15/EMDC/TCLK2 output signal is connected to the MDC input signal of the Ethernet Transceiver (MN22). The PA16/EMDIO/IRQ6 input/output signal is connected to the MDIO input/output signal of the Ethernet Transceiver (MN22). Disables the power-down mode of the Ethernet Transceiver (MN22). Not Used: The Front End AC97 is not installed. Not Used: The Front End AC97 is not installed. Not Used: The Front End AC97 is not installed. Connects the system ground to the Ethernet ground. Not Used: The Front End AC97 is not installed.
S24 S25 S26 S27 S28 S29
Closed Closed Closed Closed Closed Closed
S30 S31
Closed Closed
S32 S33 S34 S35 S36 S37
Closed Closed Closed Closed Closed Closed
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Configuration Straps
Table 4-1. Configuration Straps and Jumper Settings
Designation S38 S39 S40 Default Setting Opened Closed Closed Feature The AT91RM9200 boots up from the parallel Flash Memory. Enables the use of the User LED (DS5). Not Used: The Buzzer is not installed.
Note: Note:
Shaded cells indicate configuration straps/jumpers with open connections. Signal names in bold indicate that the function is shared between several signals.
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AT91RM9200 Development Kit User Guide
Section 5 Schematics
5.1
Schematics
This section contains the following schematics:
n AT91RM9200 Board Layout - Top View n AT91RM9200 Board Layout - Bottom View n Power Supply n AT91RM9200 Chip n Buffers n SDRAM and Flash n Serial Devices n PS2 COM Ports n 3V3 Memory Card n Ethernet n DAA n AC97 Analog Front End n Serial Interfaces n Fingerchip n VGA TFT/CRT Display
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VUE FACE ELEMENTS
4
3
2
1
C228
Y3 F3 F4
R97
L14 L14 L14 L14 L14
L15
C230 C230 C230 C230 C230
R98 R98 R98 R98 R98
L16
MN17
R106
MN3
C121
C233
R103
F5
R102
C12
Q7
R100
R108
CR9
CR24
R107
K
K
K
C251
C250
C269
C270
C271
C272
C212
1
C254
R124
C262
C263
R114
C267 C267 C267 C267 C267
C252
C253 C253 C253 C253 C253
C260
C3 73
MN28
L13
36 36 36 36
L1 37 37 37 37 37 72
C265
C264
C273
C220
MN1
C257
J24
6
R150
C8
1
C7
C4
MN21
2
1
C277
C192
R89
C175
L7
R29
R37
C179
C177
C118
C188 CR12
MN24 MN24 MN24 MN24 MN24
R78
C225
R79
K
S16
Q6
2
Q5
K
R76 CR16
J13
F2
S15
R77 R77 R77 R77 R77
R35
C112
K
LS1 J12
C191
C173
R90
C180
R84
R91
R31
C154
4
CR11 C185
3
C80 C80 C80 C80 C80
1 K
C182 CR13
CR14
C174
CR10
R83
R88
Y4
1
J18
1
MN2
R153
C9
1
1
CR8 R48
J2
C276 C276 C276 C276 C276
C279
S2
C28
6 6 5 5 4 4 3 3 2 2 1 1
J31
49
CR20
K
J11
50
C151
3
2
MN5
25
C145 C144
1
R149
MN34
C275
4
C147
C27
C24
1
2
49
6 6 5 5 4 4 3 3 2 2 1 1
50
C143 C142 MN20 C132
6 6 5 5 4 4 3 3 2 2 1 1
R8
MN8 C90 C83
C149 C148 C133 C134 C135
C20
C62
1
ABCDEFGHJKLMNPRT ABCDEFGHJKLMNPRT
C205
1
C25 J16
C43
C209
1
C41
C42
C103 C100
C200
C278
C51 C84 C89 C88 C85
C141
C95
17
Y5
C49
R92
J21 C86
J4
6 6 5 5 4 4 3 3 2 2 1 1
C36
16 15 14 13 12
C101
C48
11
C196
ABCDEFGHJKLMNPRT ABCDEFGHJKLMNPRT
MN13
10
L9
C53 C94
C140 C139 C136
C96 C87
9 8
MN4
MN11
1
C208
J5
7 6
C40
C210
C55 C73 C69 C68
MN18 C138 C137 C152
5
C193
4 3
C47 C46
ABCDEFGHJKLMNPRT ABCDEFGHJKLMNPRT
2 1
C39 C70
1
C153
A A B B C C D D E E F F G G H H J J K K L L
N N P P R R T T U U
1
1
C109
C30
50
1
R10 R50
C23
J22
J3
Z*
C146
Y2
R154
2
MN9
C190
1
R36
MN27
C217
R33
S13
C178
L8
R55
C158
R155
R14
R13 R13 R13 R13 R13
DS1
K
MN19 C246
DS2
DS3
J8
1
1
C150
D
MONTAGE DU LCD
D
TP3
J30 J27
11
6 4 1 2 1 3
SUR
Z4
SUPPORT
63PC021039
VOIR
DETAIL
MN30
Z7
S1
1
3
4
J28
3
4
R95
B4 B1
J1
1
2
5
6
1
2
J15
5
6
J14
C18
A4 A1
CR4
CR3
MN16
K
1
K
F1
1
L2
32
1 0 1 R
TP4
2 VIS CM 2,5X8 INOX A2
2 RONDELLES ONDUFLEX DIA.2,5
2 ECROUS HM2,5 INOX A2
J33
J29
MN26
CR2
7 8 4 3 1 1 3 3 1 1 1 1 R R R R
CR1
CR7
1
1 2 1 2 1
J23
C1
C13 144 108
6 1
C16 109
C17
R132
C268
1
LCD
4 ENTRETOISES M/F HEXA
R131
C10
MN32
R125
M2,5X10 INOX A2
1 1
MN33
SUPPORT 63PC021039
C
MODULE
CR5
C266
C216
K 1
K
J25
4 ENTRETOISES F/F HEXA
M2,5X25 INOX A2
CR6
R74
C187
CI 63PC02512
Q3
9
R73
C176
8 VIS CM 2,5X10 INOX A2
8 RONDELLES ONDUFLEX DIA.2,5
R72 J20
1
1 1
MN29
MN15
S14
MN23
C224
1
C120
FILS SORTIES CONNECTEURS A FRETTER
1
1
S17
1
Y1
B
R7
2
1
26
2
C38 C71 C67 C66 R51
50 49 Z* J6 50
1
C157
L4
1
R47
1
C102
ABCDEFGHJKLMNPRT ABCDEFGHJKLMNPRT
J19
C72
MN14
1
2
J7 49
C160
TP2
NOTA : COMPOSANTS A MONTER SELON NOMENCLATURE
C159
1
TP1 DS4
MN31
2
K
K
K
J9
19
1
BP1 DS5
K
1
Z*
C82
C29
Z6
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SOUDURES
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D
S22
D
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ADHESIFS
C243 C128 C125 C122 C229 C126 C127 C123
C242
R137
S11
C239
C232
S24
C236
Q2
1
R44
C241
C124
R43
C231
C235
C240
C130
C129
C238
C237
CR19
CR18
CR17
R99 C11 R41 R40
R105
R104
R128
R42
R127
R3
S12
R126
C234
Q9
R110
R4
R109
R39
R138 C131
R38
R139
C211
C14 C15
L12
L11
R136
R120
C213 R143
C274
C214
R135
R119
R121 R145
S19
C215 C258 C255 C256 C259
R122
C248
C249
C247
R130
R129
C222
CARTE
Q1 C2
1
C219
R146 R147
R60
C91
R111
R151
C221
R144
R112
R148
INSERTION
C
S26
C261
C223
S23
R1 R2
J26
CR21
R96
R113
R115
R116
C6 C5
R123
S27
1 5
S20
C181 C227
S9
R28
C117
CR15
R87
C119 C226
R27
R81 R30
R82
R75
+
C111
S21
C115
Q4
R32
R85 S10
R34
R80
C172 C116
Q10
C280
C114 C113
R93 R94
R86
C186 R158
S40
C189
C184
C183
S29
C218
C202
R141
R26
R49 C63 C64
S8
C65
B
C197
1
R140
R9
C21 C34 S18 R23
R5 R6
C74
S4
S5
C31 C19 C22
C204
48
1
C107
C33 C76 C75 C26
CR23 C207 C206
C35 C32 S35
1
C98
MN25 C201
J17 S31
R156
S30
C104
C50 C52 C54 S36 C169
C105 C195 C198 R142 C165 C164
C97
C199
MN12
C61 C59 S34 S33
C99 R62 C56
C171
L5 48
1
C203
R58 R57
C194
C110
R52
C162 C161 MN22
R53
24
C106
C44 C60
C163
L6 S7
C167
C45
C37
C58
C57
C155
C78
C77
C168
NOTA
:
COMPOSANTS
A
MONTER
SELON
NOMENCLATURE
R11
R12
S6
L3
R56
R54
C166
C79 C93 R18 R19 R20 R21 R15 R16 C92
C156
C170
S25
C108 R24
R25 R70 R69 R59 S32
R61
R71
R17
R45
C81
S3
S28
Q8
S39
R157
R152
S38
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2
1
12V TO 14V DC INPUT
D
D
VIN R1 I l i m i t = 0 . 1 V / R . . . about 2.9A R068
M P 1 7 9 _ 2.1mm J1 1 2
C R1
F5
2A
S T P S340 C2 + MN1 5 V+ 1 2 3 SHDN 3 7 + RES/PG GND EN FB/NC C9 100NF 7 T P S 7 7618D C5 100NF C4 2 2 0 uF C7 C8 2 2 0 uF 2 2 0 uF C6 1 F
C
3
1F Q1 I R F 7 4 25 8 7 6 5 8 + C R5 S T P S340 + 1 2 VIN VIN VOUT VOUT C R6 3.3V MN2 3 4 6 5 3V3 1V8 L1 22uH 3.8A
R2
R068
C R2 + C1 25V 4 7 0 uF C3 2 2 0 uF 16V CS EXT REF GND MAX1626 OUT 1 4 6 2 3/5 4 C10 100NF 8
S T P S340
C R3
S T P S340
C R4
S T P S340
C
R3 I l i m i t = 0 . 1 V / R . . . about 2.9A
R068
C11 1F MN3 5 V+ 1 2 3 SHDN 3 7 + 1 C R7 S T P S340 + + 4 5 6 3/5 EXT REF GND MAX1626 OUT CS 2 4 C18 100NF 8 6 7 5V 8 L2 22uH 3.8A C12 2 2 0 uF 16V + Q2 I R F 7 4 25
R4
R068
B
C14 100NF C13 2 2 0 uF C16 C17 2 2 0 uF 2 2 0 uF
C15 1 F
B
TP1
TP2 Z1 Z4 Z7 TP3 16 Z5 16
A
GUARD RING
Z3 TM TM 1 Z6 1 1 TM 1 TM
Z2 16
A
Z8 16 S1
Z9 16 TP4
W e d n e s d a y , M a y 2 1 , 2003
S TUDIEL
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
MMA
2 1 / 0 5/03
ATMEL
NORMALLY C L O S E D
P O W E R S U P PLY
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
V E R I F.
D a t e:
1/1
AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
1 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
P B [ 0 . .29] P C [ 0 . . 15] PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC6 PC5 PC4 PC3 PC2 PC1 PC0 L13 M17 M13 N17 N16 L12 K15 K13 K14 L15 L14 M14 M15
P A [ 0 . .31]
A10 F11 E11 F12 G12 E12 E13 B12 A12 D12 D13 C12 A13 C13 B13 D14 B14 A15 A17 B16 B15 D15 E14 C16 B17 E15 F16 F13 G16 G15 G14 G13
PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
J6 J5 G6 G4 F4 F5 F3 C4 B4 A3 C5 B3 A4 F7 E7 D7 C7 C8 F9 B8 A8 D9 E9 C9 B9 A9 E10 D10 C10 B10
D [ 0 . . 3 1] A [ 0 . . 25]
D
P D [ 0 . . 27] IRQ0/PB29 FIQ/PB28 PCK0/PB27 RTS1/PB26 EF100/DSR1/PB25 CTS1/PB24 DCD1/PB23 SCK1/PB22 RXD1/PB21 TXD1/PB20 RXCK/DTR1/PB19 ECOL/RI1/PB18 ERXDV/RF2/PB17 ERX3/RK2/PB16 ERX2/RD2/PB15 ETXER/TD2/PB14 ETX3/TK2/PB13 ETX2/TF2/PB12 TIOB5/RF1/PB11 TIOA5/RK1/PB10 TIOB4/RD1/PB9 TIOA4/TD1/PB8 TIOB3/TK1/PB7 TIOA3/TF1/PB6 MCDA3/RF0/PB5 MCDA2/RK0/PB4 MCDA1/RD0/PB3 SCK3/TD0/PB2 CTS3/TK0/PB1 RTS3/TF0/PB0 HOLDA/PC15 HOLD/PC14 NCS7/PC13 CFCE2/NCS6/PC12 CFCE1/NCS5/PC11 CFCS/NCS4/PC10 NWAIT/PC6 BFWE/PC5 BFOE/PC4 SMWE/BFBAA/PC3 BFAVD/PC2 SMOE/BFRDY/PC1 BFCK/PC0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27
E17 F15 F14 E16 D17 C17 D16 D6 A6 B6 C6 A5 B5 B2 C3 C2 F1 G2 G5 G1 H2 H4 H3 H1 J3 J1 J4 J2
PD0/ETX0 PD1/ETX1 PD2/ETX2 PD3/ETX3 PD4/ETXEN PD5/ETXER PD6/DTXD PD7/PCK0/TSYNC PD8/PCK1/TCLK PD9/PCK2/TPS0 PD10/PCK3/TPS1 PD11/TPS2 PD12/TPK0 PD13/TPK1 PD14/TPK2 PD15/TD0/TPK3 PD16/TD1/TPK4 PD17/TD2/TPK5 PD18/NPCS1/TPK6 PD19/NPCS2/TPK7 PD20/NPCS3/TPK8 PD21/RTS0/TPK9 PD22/RTS1/TPK10 PD23/RTS2/TPK11 PD24/RTS3/TPK12 PD25/DTR1/TPK13 PD26/TPK14 PD27/TPK15
C
RTS2/DTXD/PA31 CTS2/DRXD/PA30 TCLK5/MCDA0/PA29 TCLK4/MCCDA/PA28 TCLK3/MCCK/PA27 IRQ1/TWCK/PA26 IRQ2/TWD/PA25 PCK1/SCK2/PA24 IRQ3/TXD2/PA23 TIOB2/RXD2/PA22 TIOA2/RTS0/PA21 TIOB1/CTS0/PA20 TIOA1/SCK0/PA19 TIOB0/RXD0/PA18 TIOA0/TXD0/PA17 IRQ6/EMDIO/PA16 TCLK2/EMDC/PA15 TCLK1/ERXER/PA14 TCLK0/ERX1/PA13 MCDB3/ERX0/PA12 MCDB2/ERXDV/PA11 MCDB1/ETX1/PA10 MCDB0/ETX0/PA9 MCCDB/ETXEN/PA8 EXTCK/PCK2/PA7 RXD3/NPCS3/PA6 TXD3/NPCS2/PA5 PCK1/NPCS1/PA4 IRQ5/NPCS0/PA3 IRQ4/SPCK/PA2 PCK0/MOSI/PA1 PCK3/MISO/PA0
D
D DP D DM
K5 K2
DDP DDM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PC16/D16 PC17/D17 PC18/D18 PC19/D19 PC20/D20 PC21/D21 PC22/D22 PC23/D23 PC24/D24 PC25/D25 PC26/D26 PC27/D27 PC28/D28 PC29/D29 PC30/D30 PC31/D31
R9 P10 N11 U9 M11 P11 U10 U11 R11 T11 P12 U12 T12 R12 U13 P13 U14 R13 U15 T14 U16 T15 U17 T16 R15 T17 P14 P15 N13 R16 N15 N14
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
C
H DPA H DMA
K1 K3
HDPA HDMA
H DPB H DMB
L2 L3
HDPB HDMB
3V3 R152 47K PA31 B O O T M O D E SELECT S38
T DI TMS TCK MN4
A1 C1 E5
TDI TMS TCK
C19
T DO NTRST J T A GSEL V D D P LL C20
B1 E2 A2
TDO NTRST JTAGSEL
AT91RM9200
R159 470R
H13 VDDPLLB 1 0 0 NF
100NF
R5
10R
H15
C21
GNDPLLB
1 CR22 3 NRST 2 BAT54 RAS CAS N10 U8 RAS CAS CFIOR_NBS1_NWR1 C FIOW_NBS3_NWR3 SDWE SDA10 SDCKE SDCK T8 N6 P9 U7 S DWE SDA10 S D C KE SDCK NBS1 NBS3
B
R6
1K96
4.7NF
4 7 0 pF
F17
PLLRCB
C22
K17
XOUT
NBS0/A0 NWR2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 PC7/A23 PC8/A24 CFRNW/PC9/A25
N1 M4 M6 M3 N4 N2 L4 P1 N7 N3 M5 P5 P3 P2 N5 T1 U3 T3 R3 U4 R4 N8 P6 T4 R5 P7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
2
B
C23
10PF
R7
0R
C24
10PF
Y1 1 8 . 4 3 2MHz
1
TEMPERATURE S E N S O R
J17
XIN
3V3
C25
V D D O S C C26 J14
VDDOSC
C28 100NF
100NF
100NF
R8
10R
J13
GNDOSC
4
B
VCC
1
3 2 . 7 6 8 kHz
H17
XOUT32
1
TEMP
A
2
C27 1 0 P F
Y2
BFCS/NCS0 SDCS/NCS1 NCS2 SMCS/NCS3 CFOE/NOE/NRD
U6 M9 T6 R7 N9
B F C S _ N C S0 SDCS NCS2 S M C S _ NCS3 CFOE_NOE_NRD MN6 1 GND
C29
3
OUT
GND
5
C30
3 / 1 0 PF
4
G17
XIN32
100NF VCC 4 3V3 BP1 NRST TST1 TST0 E1 R11 D1 E4 1K 2 RESET MR 3 M A X 6 3 9 0XS29D4-T R12 P4 T5 A7 R6 D8 D5 D2 D3 H5 K4 L6 1K R13 1K 3V3 3 4 1 2
MN5 MAX6605
C31
V D D P LL
C32 J15 VDDPLLA 100NF
P8 CFWE/NWE/NWR0 T7 CFIOR/NBS1/NWR1 R8 CFIOW/NBS3/NWR3
C F WE_NWE_NWR0 C F I O R _ N B S 1 _ N WR1 CFIOW_NBS3_NWR3
1 0 0 N F R9 10R C33 5.6NF R 10
J16
GNDPLLA
1K27
L17
PLLRCA
RESET
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP P16 K16 M1 A16 A11 B11
F6
L16
T10
C14
R17
R10
R14
A
M12 P17 M16 J12 H16 C15 A14 C11 D11 B7 E8 E6 D4 E3 F2 G3 L1 L5 M2 R1 U2 R2 M7 U5 T9 N12 T13
H14
S2
U1
T2
1V8
J2
VDDIOP
C34
6 8 0 pF
NRST 3V3 W e d n e s d a y , M a y 2 1 , 2003 100NF 100NF 100NF 100NF C62 10F C43 C47 C53 C57
A
1
C351 0 0 N F
C361 0 0 N F
C371 0 0 N F
C381 0 0 N F
C39
C401 0 0 N F
C411 0 0 N F
C421 0 0 N F
C441 0 0 N F
C451 0 0 N F
C461 0 0 N F
C481 0 0 N F
C491 0 0 N F
C501 0 0 N F
C511 0 0 N F
C521 0 0 N F
C541 0 0 N F
C551 0 0 N F
C561 0 0 N F
C581 0 0 N F
C591 0 0 N F
C601 0 0 N F
C611 0 0 N F
C64 100NF
100NF
C63 10F
21 3 4
2 V D D P LL V DDOSC
C R8 S T P S1L30
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
S TUDIEL
MMA
2 1 / 0 5/03
ATMEL
A T 9 1 R M9200
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
V E R I F.
D a t e:
1/1
AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
2 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
A [ 0 . .25] P D [ 0 . .27] A23 A25 DB17 DB19 DB21 DB23 DB25 DB27 DB29 DB31 NRST NCS3 N W R1 N W R3 PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 3V3 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C65 100NF J3 P C [ 0 . . 15] P B [ 0 . .29] P A [ 0 . .31]
A B [ 0 . .25]
MN7A
C67 C69 C71 C73 1 0 0 N F 1 0 0 N F 1 0 0 NF 1 0 0 N F C66 C68 C70 C72 1 0 0 NF 1 0 0 N F 1 0 0 N F 1 0 0 N F
A25 A24 A23 A22 A21 A20 A19 A18
A2 A1 B2 B1 C2 C1 D2 D1
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
A5 A6 B5 B6 C5 C6 D5 D6
AB25 AB24 AB23 AB22 AB21 AB20 AB19 AB18
3V3
A3 A4
1DIR 1OE
D
D
C3
C4
F3
F4
L3
L4
P3
P4
MN7B C74 1 0 0 NF DB16 DB18 DB20 DB22 DB24 DB26 DB28 DB30 NCS0 NCS2 N W R0 N W R2 NRD PC0 PC2 PC4 PC6 PC8 PC10 PC12 PC14 A24 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7 4 A LVCH32245
3V3
MN7E
VCC
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A17 A16 A15 A14 A13 A12 A11 A10 C 75 100NF 3V3
E2 E1 F2 F1 G2 G1 H2 H1
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 3V3 R140 1K W A IT DB14 DB12 DB10 DB8 DB6 DB4 DB2 DB0
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
E5 E6 F5 F6 G5 G6 H5 H6
AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
H3 H4 J4 DB15 DB13 DB11 DB9 DB7 DB5 DB3 DB1
2DIR 2OE
J5
C 76 100NF 3V3
M N7C
A9 A8 A7 A6 A5 A4 A3 A2
J2 J1 K2 K1 L2 L1 M2 M1
3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8
3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8
J5 J6 K5 K6 L5 L6 M5 M6
AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2
J3 J4
3DIR 3OE
PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
C
A1 A0 N CS0 N WR0 N WR1 NRD 3V3 C77 100NF D B [ 0 . .31] PD5 PD3 PD1 C78 100NF 3V3 NCS0 NCS3 N W R0 N W R1 N W R3 NRD
M N7D AB2 N W R2
C
AB1 AB0
B F C S _ N C S0 S M C S _ N CS3 C F WE_NWE_NWR0 CFIOR_NBS1_NWR1 C FIOW_NBS3_NWR3 CFOE_NOE_NRD
N2 N1 P2 P1 R2 R1 T1 T2
4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8
N5 N6 P5 P6 R5 R6 T6 T5
AB25 AB23 AB21 AB19 AB17 AB15 AB13 AB11 AB9 AB7 AB5 AB3 AB1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 AB24 AB22 AB20 AB18 AB16 AB14 AB12 AB10 AB8 AB6 AB4 AB2 AB0
PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 PB0 PB2 PB4 PB6 PB8
PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 PB1 PB3 PB5 PB7 PB9
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
N CS2
T3 T4
4DIR 4OE
D [ 0 . . 31]
3V3
PB29 PB27 PB25 PB23 PB21 PB19 PB17 PB15 PB13 PB11
MN8A
3V3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
C79 100NF J6
MN9G
14
C80 100NF
D31 D30 D29 D28 D27 D26 D25 D24
A5 A6 B5 B6 C5 C6 D5 D6
MN9A
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
A2 A1 B2 B1 C2 C1 D2 D1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24
VCC 7 4 A L VC04 GND
SDCS
1
2
A3 A4
1DIR 1OE
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
C81 1 0 0 NF
B
B
PD6 PD4 PD2 PD0
PB28 PB26 PB24 PB22 PB20 PB18 PB16 PB14 PB12 PB10
7
7 4 A L VC04
MN8B
3V3 3V3 R14 1K 3V3 MN10 RESET 3 VCC GND M A X 6 3 8 3XR30D3-T 1 C82 100NF 2 NTRST J7
D23 D22 D21 D20 D19 D18 D17 D16
E5 E6 F5 F6 G5 G6 H5 H6
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
E2 E1 F2 F1 G2 G1 H2 H1
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
C84 C86 C88 C90 1 0 0 N F 1 0 0 N F 1 0 0 NF 1 0 0 N F C83 C85 C87 C89 1 0 0 NF 1 0 0 N F 1 0 0 N F 1 0 0 N F
H3 H4
2DIR 2OE
M N8C
E TM T R A C E PORT
3V3 10K 10K 10K 10K 10K
3V3
D15 D14 D13 D12 D11 D10 D9 D8
C3
C4
J5 J6 K5 K6 L5 L6 M5 M6
F3
F4
L3
L4
P3
P4
3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8
3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8
J2 J1 K2 K1 L2 L1 M2 M1
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
3V3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J3 J4 C91 1 0 0 NF J8 3 J9 2
ICE / JTAG INTERFACE
R15 R16 R17 R18 R19 R 20 10K
3DIR 3OE
MN8E
J TAG
A
7 4 A LVCH32245
M N8D
PD9 PD10 PD11 PD7 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 3V3 NTRST TDI TMS TCK NRST S25 T DO
P I P E S T A T[0] PIPESTAT[1] PIPESTAT[2] T R A C E S YNC T R ACEPKT[0] T R ACEPKT[1] T R ACEPKT[2] T R ACEPKT[3] T R ACEPKT[4] T R ACEPKT[5] T R ACEPKT[6] T R ACEPKT[7] V S U P PLY E X T TRIG PD8 T R A C E CLK
T R ACEPKT[8] T R ACEPKT[9] T RACEPKT[10] T RACEPKT[11] T RACEPKT[12] T RACEPKT[13] T RACEPKT[14] T RACEPKT[15] NTRST TDI TMS TCK S3
PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
SYSTEM R ESET
T DO N S RST D B G RQ G ND N RST R21 10K
A
W e d n e s d a y , M a y 2 1 , 2003
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
S TUDIEL
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
D7 D6 D5 D4 D3 D2 D1 D0
N5 N6 P5 P6 R5 R6 T6 T5
4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8
4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
N2 N1 P2 P1 R2 R1 T1 T2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ICE
1
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
MMA
2 1 / 0 5/03
ATMEL
BUFFERS J T A G S EL C92 100NF C93 100NF G1 G2 G3 G4 G5
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
V E R I F.
D a t e:
T3 T4
4DIR 4OE
1/1
AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
3 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
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4
3
2
1
8
7
6
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2
1
EBI SDRAM INTERFACE
A [ 0 . . 25]
D [ 0 . . 3 1]
RAS CAS
D
D
S D WE S D A 10 SDCKE S DCK
NBS1 NBS3 MN11 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 S D A 10 A13 A16 A17 20 21 36 40 SDCKE 37 38 15 39 17 18 16 19 S DCK A1 CAS RAS S DWE N BS2 NBS3 3V3 A14 BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 MN12
S DCS
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 23 24 25 26 29 30 31 32 33 34 22 35 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 20 21 36 40 3V3 37 38 15 39 17 18 16 19 C 94 C95 C96 1 00NF 100NF 100NF C100 C101 C102 C103 100NF 1 00NF 100NF 1 00NF
S D A 10
A13
A16 A17
BA0 BA1
2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
A14
SDCKE
C
S DCK
C
A0
N BS0 NBS1
1 14 27 3 9 43 49
1 14 27 3 9 43 49
CAS RAS
S DWE
M T 4 8 L C 8M16A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 N.C N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 28 41 54 6 12 46 52 28 41 54 6 12 46 52
M T 4 8 L C 8M16A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 N.C N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ
128 Mbits
128 Mbits
C97 C 98 C99 100NF 1 00NF 100NF C104 C105 C106 C107 100NF 1 00NF 100NF 100NF
D B [ 0 . . 31] MN21
A B [ 0 . .25]
B
3V3 A T 4 9 B V 1614A
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 R/B N.C 3V3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15A-1 15 10 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15
B
R150 47K
AB21
NRST N WR0 VCC 46 27 37
S27
3V3 VSS VSS
NCS0 NRD
3V3
12 11 14 13 26 28 47 RESET WE N.C VPP CE OE BYTE
C277 1 00NF
A
A
W e d n e s d a y , M a y 2 1 , 2 003
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2 1 / 0 5 /03
A TMEL
S D R A M & F L ASH
B A E DT ORG I ND M ODIF.
Ech:
JPG JPG JPG D E S S.
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property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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7
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5
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3
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1
3V3 C108 100NF 1 2 N.C N.C N.C N.C RDY/BUSY RESET WP N.C N.C 46 45 N.C N.C 48 47 MN13
P D [ 0 . . 27]
3V3
MN14
R22 VCC WP NC NC
10K
J10 20 19 18 17
1
2
1 2 3 4
A0 A1 NC NC
AT24C1024 SO8
PD6 5 6 R23 100K 7 S5 11 VCC VCC 12 GND GND 36 C110 100NF 37 3V3 3V3 N.C N.C N.C NRST 44 43 42 S4
NORMALLY C L O S E D
3 4
D
D
P C [ 0 . . 15] SCL SDA 12 11
3V3
NC NC NC NC NC
10
GND
SO20
WRITE P R O T E C T NORMALLY O P E N
N.C N.C N.C IO7 IO6 IO5 IO4 3V3 3V3 J 11 1 N PCS0 17 CS SER/PAR SCK/CLK SI SO N.C N.C N.C N.C A T 4 5 D B 642-TC N.C N.C 26 25 N.C N.C 28 27 N.C N.C 30 29 31 S8 SPCK 18 19 20 21 22 23 24 MOSI MISO 2 IO3 IO2 IO1 IO0 R26 100K 13 14 15 16 N.C N.C N.C N.C 35 34 33 32 C109 100NF 8 9 10 41 40 39 38
A T 2 4 C 1 024W
R24 2K7
R25 2K7
PA26
S6
NORMALLY C L O S E D
TWD
NORMALLY O P E N
PA3
C
AT45DB321 - AT45DB1282 AT45DB642 AT45DB2562
PA25
S7
T WCK
A T24C512
P A [ 0 . .31]
5 6 7 8 9 NC NC NC NC
16 15 14 13
C
3V3
R27 100K A0 A1 A2 A3 J12 C111 1 NF 1 1 9 R33 11K R34 240R 2 2 J13 8 V I N 15V FULL RANGE R31 47K R32 1K8 7 R29 11K R30 240R 6 TEMP
R28 100K
MN15
PA0
MISO
1
SDO
PA1
MOSI
2
SDI
PA2
SPCK
3
SCLK
PA5
A DC_CS
S9
16
CS
PC15
ADC_IRQ
S10
4
EOC/INT
NORMALLY C L O S E D
B
13
FS
B
12 C113 112 C C114 1 NF 1 NF 1 NF 15 14 C120 10F C119 100NF R35 7K5 C115 1% 1F R36 7K5 C 1 1 6 1% 1 F R37 7K5 C 1 1 7 1% 1F
PWDN
10
CSTART REFP REFM
TWO USER ENTRY MEASURE 5V FUL RANGE L
3V3
5
VCC
C118 1 0 0 NF
11
GND
T L V 1504
A
A
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MMA
2 1 / 0 5/03
ATMEL
S E R I A L D E VICES
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
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is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
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2
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5
4
3
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D
D
3V3
MN16E VCC 7 4 L C X125 GND 7 C121 100NF
14
R38 1K
3V3
P A [ 0 . .31] 5V 1 R40 1K 2 1 J14 9 10 11 6 4 2 S1 S2 S3 C124 10F C125 100NF 3 R43 10K MN17 4 VSS 4 X_PWR SDATA SCLK 20 E1CLK 21 E1DATA 5V OSCOUT M N 1 6B 7 4 L CX125 6 29 28 OSCIN 18 E0CLK 19 E0DATA F1 0.50A M N 1 6A 7 4 L CX125 2 R41 1K Y3 4MHz R42 10K
R39 47K
P B [ 0 . .29]
PA0
M ISO
3
C122 47pF 5 3 1 C123 47pF
C
C
PA2
S PCK
5
PA4 2 1 32 3 3 VREF VSS2 VDD 2 5 7 8 C R9 BAT54 R44 1K 13 C129 1 0 0 NF C131 10F 11 5V 5V 6
S11
10
26 27 17 31 30
N PCS1
9
M N 1 6C 7 4 L CX125 8
J15 6 4 2 S1 S2 S3 C128 100NF 5 3 1
C126 47pF
PB29
I R Q0
S12
1
RXD 22 TXD E2CLK 23 RTS/SS E2DATA CTS/ATN U R 6 H C P S 2 - SP40 24 PWROFF E3CLK 25 E3DATA CONF2 16 CONF1 RES0 15 CONF0 LED3 14 LED2 13 ASI/SPI LED1 12 LED0 RESET
C127 47pF
NRST 7 4 L CX125 C130 1 0 0 NF
12
B
B
MN16D
NOT INS TALLED
A
A
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P S 2 C O M PORTS
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
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is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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1
D B [ 0 . .31] M N 1 8A
A B [ 0 ..25]
P C [ 0 . . 15] 3V3 J16 VCC VCC GND GND 13 50 1 38
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 A2 A1 B2 B1 C2 C1 D2 D1 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 A5 A6 B5 B6 C5 C6 D5 D6
COMPACT FLASH CONNECTOR
A3 A4 1DIR 1OE
C132 100NF C133 100NF
D
D
C135 C137 C139 C141 1 0 0 N F 1 0 0 NF 1 0 0 N F 1 0 0 N F C134 C136 C138 C140 100NF 100NF 100NF 100NF M N 1 8B
3V3
C3
C4
F3
F4
L3
L4
P3
P4
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E2 E1 F2 F1 G2 G1 H2 H1 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 3V3 2DIR 2OE R45 10K 1 3 2 MN18C M N 1 9A 7 4 L V C 32A 26 R 46 10K 25 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 H3 H4 4 6 5 MN19B 7 4 L V C32A CD2# CD1# E5 E6 F5 F6 G5 G6 H5 H6 AB25 C F R N W PC10 C F C S
31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7 4 A LVCH32245
MN18E
C
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCC
C143 C145 C147 C149 1 0 0 N F 1 0 0 NF 1 0 0 N F 1 0 0 N F C142 C144 C146 C148 100NF 100NF 100NF 100NF J3 J4 3DIR 3OE
AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 J5 J6 K5 K6 L5 L6 M5 M6 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 J2 J1 K2 K1 L2 L1 M2 M1
C
3V3 R47 MN18D AB2 AB1 AB0 AB22 R E G C F WE_NWE_NWR0 C FOE_NOE_NRD C F I O R _ N B S 1 _ N WR1 CFIOW_NBS3_NWR3 T3 T4 4DIR 4OE 3V3 M N 2 0A PC12 PC11 PC5 C FCE2 C FCE1 3V3 R E SET R48 47K 3V3 PB0 P B [ 0 ..29] M N 1 9E C O M P A C T F LASH C A R D D ETECT 14 VCC 7 4 L V C32A GND 1DIR 1OE 3 C R20 BAT54 1 2 7 N5 N6 P5 P6 R5 R6 T6 T5 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8 N2 N1 P2 P1 R2 R1 T1 T2 10K
8 10 11 12 14 15 16 17 18 19 20 44
A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 REG# CSEL# INPACK# BVD2 BVD1 32 7 R141 47K 24 42 41 CE2# CE1# WP WAIT# RESET N 7 E 5 0 - 7 5 16VY-20
B
3V3
C3
C4
F3
F4
L3
L4
P3
P4
39 WE# OE# IOWR# IORD# 43 45 46
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7 4 A LVCH32245
MN20E
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCC
36 9 35 34
B3 B4 D3 D4 E3 E4 G3 G4 K3 K4 M3 M4 N3 N4 R3 R4
VS2# VS1# RDY/BSY
40 33 37
B
PC6 A3 A4 M N 2 0B
A5 A6 B5 B6 C5 C6 D5 D6 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
A2 A1 B2 B1 C2 C1 D2 D1
C150 100NF
M N 1 9C 7 4 L V C32A
MN9E
9
3V3
11
10
8
10
7 4 A L VC04 MN9F H3 H4 2DIR 2OE
MN9B
R153 47K
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E2 E1 F2 F1 G2 G1 H2 H1 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 E5 E6 F5 F6 G5 G6 H5 H6
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
13
12
3
4
S M A RT MEDIA CONNECTOR
C151 100NF J17
S M C S _ N CS3
7 4 A L VC04
7 4 A L VC04
S29 MN20C
MN20D
3V3
N RST
AB22 AB21
A
3
N5 N6 P5 P6 R5 R6 T6 T5 ALE CLE SMWE SMOE SMCE PC2 J2 J1 K2 K1 L2 SMRDY L1 M2 M1 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 3DIR 3OE 3V3 R51
6
4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 PB1 J5 J6 K5 K6 L5 L6 M5 M6 J3 J4
4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
N2 N1 P2 P1 R2 R1 T1 T2
PC3 PC1 PC0 3V3
R50
10K
R154 47K 3V3
AD7 AD6 AD5 AD4
AD0 AD1 AD2 AD3 - WP 1 C152 P B [ 0 . .29] CN015 SMARTMEDIA C A R D D ETECT 100NF 23 24 3V3 C L O S E TO WP C153 10F
R49 47K 1
CR23 BAT54 W e d n e s d a y , M a y 2 1 , 2003 2
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A
22 SMCE 21 SMOE 20 SMRDY 19 18 17 16 15 14 13 12
1 CLE 2 ALE 3 4 SMWE 5 6 7 8 9 10 11
S TUDIEL
3V3
T3 T4
4DIR 4OE
PC2 S m a r t M e dia R DY/BSY
MMA J 18 2
2 1 / 0 5/03
ATMEL
3 V 3 M E M O R Y C ARD
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
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D a t e:
RESERVED
1/1
10K
5 4 3
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Y4
3V3
1 N .C 8 50MHZ D I S P L A Y CONTROLLER
V DD
4
MN9D
5 0 MHz 2 V SS O UT
3
C154 100NF
9
7 4 A L VC04
D
D
MN9C L3 2 C156 100NF VCCA MN22 42 REF_CLK/XT2 15 J19 TX+ C158 3 CT 2 T DT X2 8 100NF 7 1 T D+ 16 J 0 0 2 6 D 21 T X+ 1 XT1 43 R 52 49R9 1% R53 49R9 1% C157 1 0 0 NF 7 4 2 7 92093 1 2 L4 6 V CCA C155 100NF 7 4 2 7 92093 1
P A [ 0 ..31]
5
P C [ 0 . .15]
7 4 A L VC04
PA7
R E F CK
PA10 PA9 PA8 TXR54 7 R D+ C159 6 CT 100NF 8 R DC160 100NF 4 1 nF 9 C163100NF 3V3 5 R X4 9 R 9 1% RXTX_ER/TXD4 RX_ER/RXD4/RPTR VCCA AVDD AVDD AVDD 2 C162100NF 75 1 C161100NF COL/RMII CRS/ADR4 4 9 R 9 1% 4 R56
ETX1 ETX0 E T X EN
17 18 19 20 21 22 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE
PA13 PA12 RX+ 3 3V3 R55 10K
ERX1 ERX0
R X+
3
PA11 16 38 R57 3V3 S31 24 25 32 MDC MDIO MDINTR R58 3V3 41 DVDD DVDD DVDD DVDD BGRES DGND DGND DGND PWRDWN RESET D M 9 161E R155 VCCA 7 4 2 7 92093 1 1 0 0 N F C168 2 L6 2 1 0 0 N F C171 V CCA C169 10F C170 10F 7 4 2 7 92093 1 L5 VCCA VCCA 47K N.C 45 11 FDX/COLLED/OP0 12 SPEEDLED/OP1 13 LINK/ACTLED/OP2 14 CABLESTS/LINKSTS 48 R62 6K8 1% BGRESG 47 R59 10K R60 10K R 61 10K 39 30 23 AGND AGND AGND C164 C165 C166 C167 100NF 100NF 100NF 100NF 5 6 46 2K2 10K 36 35
E CRSDV
26 27 28 29 31 34 37 RXD3/ADR3 RXD2/ADR2 RXD1/ADR1 RXD0/ADR0 RX_EN RX_CLK/SCRAMEN/10BTSER RX_DV/TESTMODE
6
C
C
PA14
ER XER
75
75
75
4 5 7 8
PA15 PA16 PC4
E MDC E MDIO IRQ
S30
OP0 OP1 OP2
DS1 R E C E I V E STATUS Y ELLOW DS2
R63
270R 3V3 R64 D I S P L A Y S PEED STATUS R65 G R E E N = 1 0 0 Mb DS3 A C T LED GREEN R67 270R R66 270R R68 N O T I N S T A LLED
B
15 33 44 S32 10 40 3V3
N O T I N S T A LLED
N O T I N S T A LLED
NRST
B
3V3
OP2 OP1 OP0
R69 R70 R71 N O T I N S T A LLED
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
D ual speed 100/10 HDX R eserved R eserved Manually select 10TX HDX Manually select 10TX FDX Manually select 100TX HDX Manually select 100TX FDX A u t o n e g o ciation enables all capabilities (default)
S36
A
A
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ATMEL
E T H E R N ET
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
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is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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D
D
CR11 C173 B Z V 5 5 - C5V6 1 0 0 N F 1
C174 1 0 0 NF
C R10 BAV99
2
P A [ 0 ..31] 3
NO GROUND PLANE IN DAA SECTION
R74 5K36 1% Q3 B C P 56T1 Q4 MMBTA42
PA24 M C LK
C172 10F
P B [ 0 ..29]
PB12 R G D T C175 100NF + R75 150R MN24 R 77 + 2K2 Q5 MMBTA92 C177 0 . 1 uF 50V R 76 100K C176 1uF 20V
S13
N O T E : V A supply, use i n t e r n a l charge pump
R72 5K36 1%
PB16
OFHK
S14
MN23
PB17 F SYNC PB13 SC LK C178 1 5 0 PF 3KV R79 10R
S15
S16
3V3
R73 5K36 1%
PB15 S DO PB14 S DI
S173V3
N RST CR12 B Z V 5 5 - C43 1 R81 9K31 1% C181 1 .8NF R 82 78R7 1% R83 5K36 1% R 85 5K36 1%
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 QE2 DCT IGND C1B RNG1 RNG2 QB QE R 8 0 120K 2 SI3015 FILT2 FILT RX REXT REXT2 REF VREG2 VREG 16 15 14 13 12 11 10 9
MCLK OFHK FSYNC RGDT/FSD SCLK M0 VD VA SDO GND SDI C1A FC/RGDT M1 RESET AOUT
16 15 14 13 12 11 10 9
R78
10R
C
C179 100NF
S I 3 021
C
C180 1 0NF
S I 3 0 4 4 _AOUT A C 9 7 A N A L O G F R O NT END 3 + CR13 BAV99 1 C R14 B Z V 5 5 - C5V6 C182 0 . 6 8 uF 20V C183 100NF C184 100NF R87 402R 1%
2 R84 5K36 1%
R86 215R 1%
Q6 M M B TA42
C185 5 6 0 PF 600V
C R15 MB4S 56K
POLYSWITCH
L7 7 4 2 7 92041 F2 250V 3 R89 10M 2 C188 1 0 N F 250V + 1 R90 10M 4 CR16 270V C190 1 NF 3KV C187 1 NF 3KV 0 . 1 3A J20
C186 3.9NF
R88
B
6 5 4 3 2 1 RJ12
B
C189 3.9NF C192 1 5 0 PF 3KV R91
C191 5 6 0 PF 600V
56K
L8
7 4 2 7 92041
A
A
W e d n e s d a y , M a y 2 1 , 2003
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ATMEL
DAA
B A EDT ORG I ND MODIF.
Ech:
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2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
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CL
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IND PAGE
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is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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D
C194 100NF 5V C193 10F C195 100NF C200 10F 1 3V3 2 A V D DA C 1 9 6 10F
L9 7 4 2 7 92093
C197 100NF C199 100NF
C198 100NF
D
LINE IN
MN25 C201 470NF AVDD 23 LINE_IN_L LINE_IN_R CD_L CD_GND CD_R MONO_OUT 21 MIC1 VREF_OUT MIC2 R142 VREF VIDEO_L L M 4 549 VIDEO_R 3DP 3DN C278 2 2NF 45 46 47 S39 PB2 ID0# 12 C208 470NF S I 3 0 4 4 _AOUT PHONE EAPD S35 6 10 8 5 BIT_CLK SYNC SDATA_IN SDATA_OUT RESET# XTL_IN 11 S18 XIN 2 13 PC_BEEP ID1# 33 C206 100NF 34 C205 10F 27 A V D DA 10K 28 3V3 22 16 17 C207 100NF
C
J 21 3 . 5 P H O N E J A C K S TEREO DVDD LINE_OUT_L LINE_OUT_R LNLVL_OUT_L LNLVL_OUT_R 37 41 39 3 . 5 P H O N E J A C K S TEREO C204 1F 36 35 DVDD C202 1F 2 J22 4 1 3
25
1
9
LINE OUT
2 4 1 3 24 C203 470NF 18 19 20
C
A C 9 7 INTERFACE
P B [ 0 ..29]
AC97 REV 2.1 CODEC
R157 120R P B [ 0 . .29]
14 AUX_L AUX_R 15
3V3
USER LED
DS5 RED
R156 47K
S33
S34
PB10 PB11 PB9 PB8 NRST
NORMALLY C L O S E D
3V3 R158 2 100K
PB27
B
S40 1 Q 10 I R L M L6302 3
B
PB6
XOUT 3 XTL_OUT AVSS 26 1 XOUT 4 7 DVSS DVSS R92 1M 2 XIN
NC NC NC NC NC NC NC NC NC NC
29 30 31 32 38 40 42 43 44 48
NORMALLY C L O S E D
C209 33PF
C280 100NF
2
LS1 BUZZER
S37 G N D AUDIO
NOT INS TALLED
A
1
Y5 C 2 1 0 3 3 P F 2 4 . 5 7 6MHz
A
W e d n e s d a y , M a y 2 1 , 2003
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MMA
2 1 / 0 5/03
ATMEL
A C 9 7 A N A L O G F R O N T END
B A EDT ORG I ND MODIF.
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AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
10 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
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3V3 V CC C212 100NF 15 2 J 23 C213 1 0 0 NF C215 1 0 0 NF 16
MN26 1 C 1+
P A [ 0 . .31] G ND V+ P A [ 0 . .31] J 24 5 C 2VR XD T XD T 7 13 10 8 11 14 11 PA31 10 T R S19 12 9 R A D M 3 2 0 2ARN PA30 F P S 0 09 DBGU_RXD DBGU_TXD 6 C214 100NF 3 4 C 1C 2+
PA2 PA29 PA0 C211 100NF
P B [ 0 . .29] MCDA1
PB3 PB4 M C I8 MCI7
PB5 MCI5
M CDA3
1 N O1
N C4
15
MISO
SERIAL DEBUG PORT
MCI1
2 C O1
C O4 14
MCI7
D
PA6 MCDA2 C216 100NF
M MC_CS
3 N C1
N O4 13
M CDA0
D
PB7
MMC_TYPE
4 IN
3V3 MCI2 MCI1 MCI9
8 7 6 5 4 3 2 1 9
1 6 2 7 3 8 4 9 5
PA28
M MC_CMD
5 N O2
N C3 11
SPCK
MCI2
6 C O2
C O3 10
MCI5
PA1
MOSI
7 N C2
N O3 9
MMC_C LK
5V 28 C219 100NF G ND 24 1 P B [ 0 . .29] 2 C 2T 1IN T T 2 OUT T T 3IN T R P A [ 0 . .31] 11 T 3 OUT 10 9 T 1 OUT VPB26 14 13 12 21 20 R R 1 OUT R R R 2 OUT R 1IN R 2IN 4 5 R 3IN R 6 R 4IN R R 5 OUT 15 23 S23 0 . 2 0A C232 1 0NF P D [ 0 . . 27] N O R M A L LY CLOSED R EN R96 S HDN R 5IN 7 J 26 PB23 19 18 17 16 R 4 OUT R 3 OUT PB25 PB21 PB24 PB18 R I1 R XD1 CTS1 DSR1 D CD1 C C M 0 2 - 2504 T 2IN PB20 PB19 DT R1 T XD1 R T S1 3 C223 1 0 0 NF C222 100NF C 1C 2+ V+ 27 C221 1 0 0 NF 25 C220 100NF 26
C217 1 0 0 N F 16
V+
VL
12
SD CARD / MMC CARD INTERFACE
MN28 C 1+ MAX3241E V CC 3V3
R I G H T A N G L E M A L E SUBD
R93 4K7
8 G ND
MN27
MAX4702
R 9 4 10K
C218 33PF
J 25
RS232 COM PORT
PA27
C
DCD DSR R XD RTS T XD CTS DTR RI
MN29
1 6 2 7 3 8 4 9 5
C
PA21 S W I T C H 7816 1 2 3 4 17 18
16
5V/3V
PRES
1
10 S22 PA22 PA23 IrDA _RXD IrDA _TXD 3R3 1 8 22 47K 1 2 3 3V3 3V3 C228 10F R95 2 4 6 7 8 RX TX LEDC LEDA SD N.C VCC GND C229 1 0 0 NF 9
15
PC14 I R Q _7816 GND VCC NC RST I/O CLK NC NC
S20
CARD
PWR
2
14
READY
GND
3
C224
10F
P C [ 0 . . 15]
C227 470NF 5 6 7 8
13
C-
VIN
4
3V3
C226 220NF
C225 10F
R I G H T A N G L E M A L E SUBD
12
C+
VCC
5
IrDA T ranceiver
L T C 1 756
SMART C ARD READER
5V
10
C230 10F
C231 100NF
FIX1
B
FIX2
PA17 PA20 PA19
S21 I / O 7816 RST 7816 C L K 7816
11 10 9
DATA RIN CIN
I/O RST CLK
6 7 8
11
F3
5
B
MN30 H S D L - 1 001 S24 PD4 USB_C NX R97 15K
5V 0 . 2 0A C235 1 0NF J27 DUAL USB A A B 12 34 2 R103 D DM D DP R 1 0 6 27R C240 15PF 5 C241 15PF W e d n e s d a y , M a y 2 1 , 2003 6 27R PD5 U S B _ DP_PUP R98 22K 3V3 R99 47K Q7 M M B T2222A R100 1K5 1 CR24 BAT54 N RST 3 C236 33PF 2 3 J28 USB B 1 4 C239 100NF
A
USB HOST INTERFACE
A1 A2 A3 A4 C238 47pF B1 B2 B3 B4
C233 10F
F4 C234 100NF
R101
27R
HDMA HDPA
R102
27R
R104 15K
C237 R105 47pF 15K
A
R107
27R
HDMB HDPB C243 47pF
R108
27R
USB DEVICE INTERFACE
R109 15K
C242 R110 47pF 15K
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
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2 1 / 0 5/03
ATMEL
S E R I A L I N T E RFACES
B A EDT ORG I ND MODIF.
Ech:
JPG JPG JPG D E SS.
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AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
11 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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3V3
D
D
R111 120R
DS4 R ED
3
1 Z15 D I P S O C K ET 2 MN31 AVE AVO TPP FPL 3V3 P D [ 0 . . 27] PD3 PD2 PD1 MN19D 7 4 L V C32A S28 11 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 2 3V3 C246 10F 7 4 2 7 92093 L10 C245 10F 1 D B [ 0 . . 7] 13 N RD 12 R151 47K N C S7 PC13 P C [ 0 . . 15]
C
Q8 I R L M L2402
2 20 3 11
C
ACKN TPE PCLK RST OE DO3 DO2 DO1 DO0 DE3 DE2 DE1 DE0 VCC GND GND F i n g e rChip 16 1 C244 100NF 4 12 13 14 15 10 9 8 7
17 19 18 5 6
B
B
DO NOT SOLDER
A
A
W e d n e s d a y , M a y 2 1 , 2003
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
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MMA
2 1 / 0 5/03
ATMEL
FINGERCHIP
B A EDT ORG I ND MODIF.
Ech:
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AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
12 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
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3
2
1
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J31
C275 10F
L11 7 4 2 7 92093 A V D DV 5V 1
CW
C248 100NF C247 C249 100NF 100NF 2 2 3 1 2 3 4 5 6 1 3V3 C251 10F TWD 6 SDA SCL A0 A2 A3 WP 1 2 3 7 15 VCC VSS 8 C279 100NF NC NC NC NC NC 16 3V3 X 9 4 29-10K 9 RL/VL 14 RW/VW 12 RH/VH 5 10 4 11 13 T WCK MN34
D
C 2 7 6 LUMINANCE 20% ..100% 10F R149 10K 20%
1
A B [ 0 . .25] AB21 56
C250 L12 10F 7 4 2 7 92093 2
D
D B [ 0 . . 31] 5 133 76 118 111 116 114 AVDD AVDD 110
TEST
AVSS AVSS AVDD
DTESEN TESTEN
RESERVED
P C [ 0 . .15]
J29 H SYNC R1 R3 R5 G0 G2 G4
AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DOTCLK VSYNC R0 R2 R4 F D A T18 F D A T20 F D A T22 FDAT23 FDAT22 FDAT21 FDAT20 FDAT19 FDAT18 FDAT17 FDAT16 FDAT15 FDAT14 FDAT13 FDAT12 FDAT11 FDAT10 FDAT9 FDAT8 FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0 G1 G3 G5 B0 B2 B4 107 106 105 104 103 102 101 100 98 97 96 95 94 93 91 90 87 86 85 84 83 82 81 80
J 33
F D A T19 F D A T21 F D A T23 VMP1 VMP3 VMP5 VMP7
C
F D A T23 F D A T22 F D A T21 F D A T20 F D A T19 F D A T18 R0 B0 B1 B2 G0 G1 G2 R1 R2 B3 B4 B5 G3 G4 G5 R3 R4 R5
C
3V3 2 MN32
CR21 S HUNTED C253 10F
S1D13806 DISPLAY CONTROLLER
FPFRAME FPLINE DRDY FPSHIFT 74 75 77 78 VSYNC H SYNC D A T A EN DOTCLK B1 B3 B5 D A T A EN
VMP0 VMP2 VMP4 VMP6 G P I O 12 G P I O 10 GPIO8 GPIO6 GPIO4 GPIO2 GPIO0 C252 10F 3V3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
G P I O 11 GPIO9 GPIO7 GPIO5 GPIO3 GPIO1
PC6
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
R143 2K2
C255 100NF
MN33
C274 100NF
3V3
1
VDDD
IREF
24
3
C254 10F R112 15K
2
R144 47K
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VMP7 VMP6 VMP5 VMP4 VMP3 VMP2 VMP1 VMP0 131 130 129 128 127 126 125 124 VMP7 VMP6 VMP5 VMP4 VMP3 VMP2 VMP1 VMP0
VSSD
TWD T WCK 3V3 S26 47K R160 0R
3 4
CLK/2+ CLK/2-
23 22
3V3
C R17 BAV99 A V D DV 2 3
CR18 BAV99
CR19 BAV99
N RST
SDA SCL
CLK+ CLK-
21 20
R145 R146 R147
3V3
10K 10K 10K
5 6 7
PDEN EXTFB HSYNC
VSSQ
19
C257 C 2 5 6 10F 100NF
N WR1 N WR0 NRD N CS2
2 3
2 3
C258
3 .3NF
8
EXTFIL
VDDQ
18
3V3
39 35 34 33 32 31 30 29 28 WAIT RESET RD/WR WE1 WE0 RD BS M/R CS
R114
C259 1 5 0 pF
9
CLK
17
3V3 R 1 1 3 10R 60 66 64 62 BUSCLK CLKI CLKI2 CLKI3
R148
B
3V3
1
L13
6K8
XFILRET
2
10
CLK/2
16
R 1 1 5 10R
GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
134 135 136 137 57 61 63 65 67 68 69 70 71
G P I O 12 G P I O 11 G P I O 10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 L14 L15 L16
1
1
1
J30 H D - 2 2 R I G H T A N G L E 15PTS
VDDA
C260 10F
FUNC
15
R116
1 0R
R G
1 2 B D S 3 / 3 / 8 .9-4S2
11
B
B D S 3 / 3 / 8.9-4S2 1 2 B D S 3 / 3 / 8.9-4S2 1 2 112 115 117 119 120 113 RED GREEN BLUE HRTC VRTC IREF
12
7 4 2 7 92093 100NF C261
11
VSSA
LOCK/REF
14
B
13 14
12
OSC VSS VSS VSS VSS VSS VSS VSS VSS VSS DVSS DVSS VDDCORE VDDCORE VDDCORE IOVDD IOVDD
I2CADR
13 IOVDD
I C S 1 523
IOVDD
IOVDD
IOVDD
DVDD
5 0 M HZ 27 89 1 37 73 92 38 16 36 59 72 79 88 99 108 121 144 58 143 122 109 123 132 3V3 100NF C262 1 0 0 N F C263 1 0 0 N F 100NF C273 10F C264 C268 C265 1 0 0 N F C266 1 0 0 N F C267 1 0 0 N F C269 1 0 0 N F C270 1 0 0 N F C271 1 0 0 N F C272 1 0 0 N F 17 A V D DV R137 1K5 1% Q9 M M B T2222A R138 1K 1% R139 140R 1%
A
Generic Little Indian
(Default)
3V3 LLED R 1 2 9 LLED R 1 3 0 LLED R 1 3 1 LLED R 1 3 2 LLED R 1 3 3 LLED R 1 3 4 LLED R 1 3 5 LLED R 1 3 6
A
NOT NOT NOT NOT NOT NOT NOT NOT
INSTA INSTA INSTA INSTA INSTA INSTA INSTA INSTA
DVDD
R123 47R
R117 R118 R119 R120 R121 R122 R124 R125 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNF0
330K 330K 330K 330K 330K 330K 330K 330K
138 139 140 141 142 2 3 4
4.6mA
R126 150R 1%
R127 150R 1%
R128 150R 1%
6 1 7 2 8 3 9 4 10 5
15
W e d n e s d a y , M a y 2 1 , 2003
1027 Av du docteur LEFEBVRE 06271 VILLENEUVE LOUBET Tel 04 92 02 45 45 Fax 04 92 02 45 46 C
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MMA
2 1 / 0 5/03
ATMEL
V G A T F T / C R T D I SPLAY
B A EDT ORG I ND MODIF.
Ech:
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2 1 / 0 5/03 3 0 / 0 1/03 0 4 / 0 4/02 D a t e:
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D a t e:
1/1
AT91RM9200-DK
This agreement
CL
TYPE
N U MERO
IND PAGE
FT
13 63SC020514C 13 3
is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
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Atmel Corporation
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e-mail
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
(c) Atmel Corporation 2003. All rights reserved. Atmel(R) and combinations thereof and DataFlash (R) are registered trademarks of Atmel Corporation or its subsidiaries. ARM (R) and Thumb (R) are the registered trademarks of ARM Ltd.; CompactFlash (R) is the registered trademark of the CompactFlash Association; SmartMedia TM is a trademark of the Solid State Floppy Disk Card Forum. Other terms and product names may be the trademarks of others.
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6006A-ATARM-07/03 /0M

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