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| C8051F231 ANALOG PERIPHERALS Two Comparators - Programmable Hysteresis - Configurable to Generate Interrupts or Reset VDD Monitor and Brown-out Detector ON-CHIP JTAG DEBUG - On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System Debug (No Emulator Required!) - Provides Breakpoints, Single Stepping, Watchpoints, Stack Monitor - Inspect/Modify Memory and Registers - Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets - Low Cost, Complete Development Kit SUPPLY VOLTAGE ......................2.7V to 3.6V - Typical Operating Current: 9mA @ 25MHz - Typical Stop Mode Current: <0.1uA Temperature Range: -40C to +85C 32-Pin LQFP Package 8K Flash, 256 RAM, 32-Pin MCU PRELIMINARY 8051-COMPATIBLE C Core - Pipelined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz Clock - Expanded Interrupt Handler MEMORY - 256 Bytes Data RAM - 8k Bytes FLASH; In-System Programmable in 512 byte Sectors DIGITAL PERIPHERALS - 22 Port I/O; All are 5V tolerant TM - Hardware SPI and UART Serial Ports Available Concurrently - Three 16-bit Counter/Timers - Dedicated Watch-Dog Timer - Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes SPI is a trademark of Motorola, Inc. VDD GND Analog/Digital Power Port 0 Latch UART Timer 0 Timer 1 Timer 2 P 0 M U X P 0 D r v P0.0/TX P0.1/RX P0.2//INT0 P0.3//INT1 P0.4/T0 P0.5/T1 P0.6/T2 P0.7/T2EX TCK TMS TDI TDO /RST JTAG Logic Debug HW Reset 8 0 5 1 C o r e 8kbyte FLASH 256 byte RAM Port 1 Latch CP0+ CP0 CP0 P 1 M U X P 1 D r v CP0CP1+ CP1 CP1 P1.0/CP0+ P1.1/CP0P1.2/CP0 P1.3/CP1+ P1.4/CP1P1.5/CP1 P1.6/SYSCLK P1.7 CP1SYSCLK VDD Monitor External Oscillator Circuit Internal Oscillator WDT Port 2 Latch SPI XTAL1 XTAL2 SFR Bus P 2 M U X P 2 D r v P 3 System Clock P2.0/SCK P2.1/MISO P2.2/MOSI P2.3/NSS P2.4 P2.5 Port 3 Latch D r v NC 7.15.2002 C8051F231 8K Flash, 256 RAM, 32-Pin MCU PRELIMINARY SELECTED ELECTRICAL SPECIFICATIONS TA = -40C to +85C, VDD = 2.7V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX GLOBAL CHARACTERISTICS Supply Voltage 2.7 3.6 Supply Current (CPU Clock=25MHz 9 active) Clock=1MHz 0.4 Clock=32kHz; VDD Monitor Disabled 11 10 Supply Current (shutdown) Oscillator not running; VDD Monitor Enabled 0.1 Oscillator not running; VDD Monitor Disabled Clock Frequency Range DC 25 COMPARATORS Supply Current (each comparator) 1.5 Response Time (CP+) - (CP-) = 100mV 4.0 UNITS V mA mA A A A MHz A s PACKAGE INFORMATION D D1 A MIN NOM MAX (mm) (mm) (mm) 1.60 0.15 C8051F226DK DEVELOPMENT KIT A1 0.05 E1 E A2 1.35 1.40 1.45 b 0.30 0.37 0.45 9.00 7.00 0.80 9.00 7.00 - 32 D D1 1 PIN 1 IDENTIFIER A2 e A b A1 e E E1 |
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