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TM
CDP1824/3, CDP1824C/3
High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory
Description
The CDP1824/3 and CDP1824C/3 types are high-reliability CMOS 32-word x 8-bit fully static random-access memories for use in CDP1800-series microprocessor systems. These parts are compatible with the CDP1802 microprocessor and will interface directly without additional components. The CDP1824/3 is fully decoded and does not require a precharge or clocking signal for proper operation. It has common input and output and is operated from a single voltage supply. The MRD signal (output disable control) enables the three-state output drivers, and overrides the MWR signal. A CS input is provided for memory expansion. The CDP1824C/3 is functionally identical to the CDP1824/3. The CDP1824/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1824C/3 has an operating voltage range of 4V to 6.5V.
March 1997
Features
* Access Time - 610ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 5V - 320ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 10V * No Precharge or Clock Required
Ordering Information
5V 10V PACKAGE TEMP. RANGE -55oC to +125oC PKG. NO. D18.3
CDP1824CD3 CDP1824D3 SBDIP
Pinout
CDP1824/3, CDP1824C/3 (SBDIP) TOP VIEW
MA4 MA3 MA2 MA1 MA0 BUS7 BUS6 BUS5 VSS 1 2 3 4 5 6 7 8 9 18 VDD 17 MWR 16 MRD 15 CS 14 BUS0 13 BUS1 12 BUS2 11 BUS3 10 BUS4
Functional Diagram
MA4 MA3 MA2 MA1 MA0 3 4 5 2 1 32 X 8-BIT ARRAY
ADDRESS DECODER
SENSE AMPL
MWR
17 I/O BUFFERS
16 MRD
CS VDD = 18 VSS = 9
15 6 7 8 10 11 12 13 14
BUS BUS BUS BUS BUS BUS BUS BUS 7 6 5 4 3 2 1 0
OPERATIONAL MODES FUNCTION READ WRITE Not Selected Standby Logic 1 = High CS 0 0 1 0 Logic 0 = Low MRD 0 1 X 1 MWR X 0 X 1 DATA PINS STATUS Output: High/Low Dependent on Data Input: Output Disabled Output Disabled: High-Impedance State Output Disabled: High-Impedance State
X = Don't Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved 42
File Number
1717.2
CDP1824/3, CDP1824C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (V DD) (All Voltages Referenced to VSS Terminal) CDP1824/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1824C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V DD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 75 20 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Storage Temperature Range (TSTG) . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
TA = Full Package-Temperature Range. For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1824/3 CDP1824C/3 MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input Voltage Range
MIN 4 V SS
MAX 10.5 VDD
Static Electrical Specifications
CONDITIONS VO (V) VOL V OH V IL VIH IOL IOH IIN IOUT CIN COUT 0.5, 4.5 1, 9 Input High Voltage 0.5, 4.5 1, 9 Output Low Drive (Sink) Current Output High Drive (Source) Current Input Current 0.4 0.5 4.6 9.5 Any Input 0, 5 0, 10 0, 5 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 (Note 2) (Note 2) VIN (V) 0, 5 0, 10 0, 5 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 -55oC, +25oC MIN 4.9 9.9 3.5 7 4 4 MAX 50 500 0.1 0.1 1.5 3 -1 -2 1 1 2 2 10 15 LIMITS +125oC MIN 4.8 4.8 3.5 7 1.5 2.9 MAX 500 1000 0.2 0.2 1.5 -0.75 -1.5 5 5 5 5 10 15 UNITS A A V V V V V V V V mA mA mA mA A A A A pF pF
PARAMETER Quiescent Device Current (Note 1) Output Voltage Low-Level (Note 2) Output Voltage High-Level (Note 2) Input Low Voltage
SYMBOL IDD
Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES:
1. The CDP1824C/3 meets all 5V Static Electrical Characteristics of the CDP1824/3 except Quiescent Device Current for which the limits are IDD = 200A at +25oC/-55oC; IDD = 1000A at +125oC. 2. Guaranteed, but not tested.
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CDP1824/3, CDP1824C/3
Read Cycle Dynamic Electrical Specifications
Input tR, tF 15ns, CL = 50pF LIMITS TEST CONDITIONS VDD (V) 5 10 Access Time From Chip Select tDOA 5 10 Output Active From MRD tAM 5 10 -55oC, +25oC +125oC
PARAMETER Access Time From Address Change
SYMBOL tAA
MIN -
MAX 610 320 610 320 610 320
MIN -
MAX 825 375 825 375 825 375
UNITS ns ns ns ns ns ns
tAM (NOTE 1) MRD tAA MA
CS
tDOA (NOTE 1) DATA OUT HIGH IMPEDANCE
NOTE: 1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output. FIGURE 1. READ CYCLE TIMING DIAGRAM
44
CDP1824/3, CDP1824C/3
Write Cycle Dynamic Electrical Specifications
Input tR, tF 15ns, CL = 50pF LIMITS TEST CONDITIONS VDD (V) 5 10 Data Setup Time tDS 5 10 Data Hold Time tDH 5 10 Chip Select Setup Time tCS 5 10 Address Setup Time tAS 5 10 NOTE: 1. Time required by a device to allow for the indicated function. -55oC, +25oC (NOTE 1) MIN 350 180 400 190 70 35 550 340 550 340 +125oC (NOTE 1) MIN 475 220 560 260 90 45 775 475 775 475
PARAMETER Write Pulse Width
SYMBOL tWRW
MAX -
MAX -
UNITS ns ns ns ns ns ns ns ns ns ns
MA tAS CS
tCS MWR tWRW tDS BUS tDH
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
45
CDP1824/3, CDP1824C/3
Data Retention Specifications
At TA = +25oC LIMITS TEST CONDITIONS VDR (V) 2.5 2.5 2.5 Recovery to Normal Operation Time tRC 2.5 2.5 VDD (V) 5 10 5 10 CDP1824/3 CDP1824C/3
PARAMETER Data Retention Voltage Data Retention Quiescent Current Chip Deselect to Data Retention Time
SYMBOL VDR IDD tCDR
MIN 2.5 600 300 600 300
MAX 10 -
MIN 2.5 600 600 -
MAX 40 -
UNITS V A ns ns ns ns
DATA RETENTION MODE VDD 0.95 VDD VDD tCDR tF (NOTE 1) tF (NOTE 1) tRC 0.95 VDD
VIH CS VIL
VIH VIL
NOTE: tr, tf > 1s. FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
Static Burn-In Circuit
VDD 1 2 3 4 5 6 7 8 9 VSS 18 17 16 15 14 13 12 11 10 VSS VDD
All Resistors 47k (20%)
TYPE CDP1824 CDP1824C
VDD 11V 7V
TEMPERATURE +125oC +125oC
TIME 160 Hrs., Min. 160 Hrs., Min.
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