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| PROCESS Small Signal Transistor NPN - Low Noise Amplifier Transistor Chip CP188 Central TM Semiconductor Corp. PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization EPITAXIAL PLANAR 15 x 15 MILS 9.0 MILS 4.0 x 4.0 MILS 5.5 x 5.5 MILS Al - 30,000A Au - 18,000A GEOMETRY GROSS DIE PER 4 INCH WAFER 53,730 PRINCIPAL DEVICE TYPES CMPT2484 CMPT5088 CMPT5089 CMPT6428 CMPT6429 2N2484 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (1 -August 2002) Central TM PROCESS CP188 Semiconductor Corp. Typical Electrical Characteristics 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (1 -August 2002) |
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