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CS4265 105 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-bit Delta Sigma modulator 105 dB Dynamic Range -95 dB THD+N Up to 192 kHz Sampling Rates Single-ended Analog Architecture Volume Control with Soft Ramp
- 0.5 dB Step Size - Zero Crossing Click-free Transitions
A/D Features
Multi-bit Delta Sigma Modulator 105 dB Dynamic Range -95 dB THD+N Stereo 2:1 Input Multiplexer Programmable Gain Amplifier (PGA)
- +/- 12 dB gain, 0.5 dB Step Size - Zero Crossing, Click-free Transitions
PopguardTM
Technology
Pseudo-differential Stereo Line Inputs Stereo Microphone Inputs
- +32 dB Gain Stage - Low-noise Bias Supply
- Minimizes the effects of output transients.
Filtered Line-level Outputs Selectable Serial Audio Interface Formats
- Left Justified up to 24-bit - I2S up to 24-bit - Right Justified 16, 18, 20 and 24-bit
Up to 192 kHz Sampling Rates Selectable Serial Audio Interface Formats
- Left Justified up to 24-bit - IS up to 24-bit
Selectable 50/15 s De-emphasis
High-pass Filter or DC Offset Calibration
1 .8 V to 5 V
3 .3 V to 5 V
3 .3 V to 5 V
Le ve l T ra nsla tor
S e ria l A u d io In p u t S e ria l A u d io O u tp u t
V o lu m e C o n tro l V o lu m e C o n tro l
In te rp o la tio n F ilte r In te rp o la tio n F ilte r
M u ltib it M o d u la to r M u ltib it M o d u la to r
S w itc h e d C a p a c ito r D A C a n d F ilte r
L e ft D A C O u tp u t M u te C o n tro l M u te C o n tro l R ig h t D A C O u tp u t
P C M S e ria l Inte rfa ce / Loopba ck
S w itc h e d C a p a c ito r D A C a n d F ilte r
R e giste r C onfigura tion
IE C 6 0 9 5 8 -3 T ra n s m itte r In te rn a l V o lta g e R e fe re n c e H ig h P a s s F ilte r L in e a r P h a s e A n ti-A lia s F ilte r M u ltib it O v e rs a m p lin g ADC M u ltib it O v e rs a m p lin g ADC M ic B ia s
T ra n s m itte r O u tp u t M ic ro p h o n e B ia s
I 2 C C o n tro l D a ta
Le ve l T ra nsla tor
PGA MUX
+32 d B
R e se t
M ic In p u t 1&2
+32 d B
H ig h P a s s F ilte r
L in e a r P h a s e A n ti-A lia s F ilte r
PGA
S te re o L in e In p u t
Advance Product Information
Cirrus Logic, Inc. www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved)
NOV `04 DS657A2 1
CS4265
System Features
Synchronous IEC60958-3 Transmitter
- Up to 192 kHz Sampling Rates - 75 Drive Capability
General Description
The CS4265 is a highly integrated stereo audio CODEC. The CS4265 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz. A 2:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. The microphone input path includes a +32 dB gain stage and a low noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain or attenuation of 12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either slave or master mode. The D/A converter is based on a 4th-order multi-bit delta sigma modulator with an ultra-linear low pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. Standard 50/15 s de-emphasis is available for a 44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. Integrated level translators allow easy interfacing between the CS4265 and other devices operating over a wide range of logic levels.
Serial Audio Data Input Multiplexer Internal Digital Loopback Supports Master or Slave Operation Mute Output Control Power Down Mode
- Available for A/D, D/A, CODEC, Mic Preamplifier
+3.3 V to +5 V Analog Power Supply +3.3 V to +5 V digital Power Supply Direct Interface with 1.8 V to 5 V Logic Levels Supports IC Control Port Interface
ORDERING INFORMATION
CS4265-CNZ, Lead Free CDB4265 -10 to 70 C 32-pin QFN Evaluation Board
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TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................... 5 2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 7 SPECIFIED OPERATING CONDITIONS ................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7 DAC ANALOG CHARACTERISTICS ....................................................................................... 8 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE.................. 9 ADC ANALOG CHARACTERISTICS ..................................................................................... 11 ADC ANALOG CHARACTERISTICS ..................................................................................... 13 ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 14 DC ELECTRICAL CHARACTERISTICS ................................................................................ 15 DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 17 SWITCHING CHARACTERISTICS - IC CONTROL PORT................................................... 20 3. TYPICAL CONNECTION DIAGRAM .................................................................................... 21 4. APPLICATIONS .................................................................................................................... 22 4.1 Recommended Power-Up Sequence ............................................................................. 22 4.2 System Clocking ............................................................................................................. 22 4.2.1 Master Clock ...................................................................................................... 22 4.2.2 Master Mode ...................................................................................................... 23 4.2.3 Slave Mode ........................................................................................................ 23 4.3 High Pass Filter and DC Offset Calibration .................................................................... 23 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 24 4.5 Input Connections ........................................................................................................... 24 4.5.1 Pseudo-Differential Input ................................................................................... 24 4.6 Output Connections ........................................................................................................ 25 4.7 Output Transient Control ................................................................................................ 25 4.7.1 Power-up ............................................................................................................ 25 4.7.2 Power-down ....................................................................................................... 25 4.7.3 Serial Interface Clock Changes ......................................................................... 25 4.8 DAC Serial Data Input Multiplexer .................................................................................. 26 4.9 De-Emphasis Filter ......................................................................................................... 26 4.10 Internal Digital Loopback .............................................................................................. 26 4.11 Mute Control ................................................................................................................. 26 4.12 AES3 Transmitter ......................................................................................................... 27 4.12.1 TxOut Driver ..................................................................................................... 27 4.12.2 Mono Mode Operation ..................................................................................... 27 4.13 IC Control Port Description and Timing ....................................................................... 28 4.14 Status Reporting ........................................................................................................... 29 4.15 Reset ........................................................................................................................... 29 4.16 Synchronization of Multiple Devices ............................................................................. 30 4.17 Grounding and Power Supply Decoupling .................................................................... 30 4.18 Package Considerations ............................................................................................... 30 5. REGISTER QUICK REFERENCE ......................................................................................... 31 6. REGISTER DESCRIPTION ................................................................................................... 33 6.1 Chip ID - Register 01h .................................................................................................... 33 6.2 Power Control - Address 02h ......................................................................................... 33 6.3 DAC Control - Address 03h ............................................................................................ 34 6.4 ADC Control - Address 04h ............................................................................................ 34 6.5 MCLK Frequency - Address 05h .................................................................................... 36 6.6 Signal Selection - Address 06h ...................................................................................... 36 6.7 Channel A PGA Control - Address 07h .......................................................................... 36 6.8 Channel B PGA Control - Address 08h .......................................................................... 37 DS657A2 3
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6.9 ADC Input Control - Address 09h ................................................................................... 37 6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 38 6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 38 6.12 DAC Control 2 - Address 0Ch ....................................................................................... 38 6.13 Status - Address 0Dh .................................................................................................... 39 6.14 Status Mask - Address 0Eh .......................................................................................... 40 6.15 Status Mode MSB - Address 0Fh ................................................................................. 40 6.16 Status Mode LSB - Address 10h ................................................................................... 40 6.17 Transmitter Control 1 - Address 11h ............................................................................. 40 6.18 Transmitter Control 2 - Address 12h ............................................................................. 41 7. PARAMETER DEFINITIONS ................................................................................................. 43 8. PACKAGE DIMENSIONS ..................................................................................................... 44 9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 44 Appendix A: DAC Filter Plots ......................................................................................... 45 Appendix B: ADC Filter Plots .............................................................................................. 47 Appendix C: External IEC60958-3 Transmitter Components .............................................. 49 C.1 IEC60958-3 Transmitter External Components ............................................................. 49 C.2 Isolating Transformer Requirements .............................................................................. 49 Appendix D: Channel Status Buffer Management ............................................................... 50 D.1 IEC60958-3 Channel Status (C) Bit Management ......................................................... 50 D.1.1 Accessing the E buffer ....................................................................................... 50 D.1.2 Serial Copy Management System (SCMS) ....................................................... 51 D.1.3 Channel Status Data E Buffer Access ............................................................... 51 D.1.3.1 One Byte mode ................................................................................... 51 D.1.3.2 Two Byte mode ................................................................................... 51
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1. PIN DESCRIPTIONS
SDOUT
26
TXOUT
32
31
30
29
28
27
SDA SCL VLC RESET VA AGND AINA AINB
SDIN1
25
DGND
MCLK
LRCK
SCLK
VD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Top-Down (Through Package) View 32-Pin QFN Package
24 23 22 21 20 19 18 17
SDIN2 TXSDIN VLS MUTEC AOUTB AOUTA AGND VA
Thermal Pad
VQ
MICIN1
MICIN2
FILT+
Pin Name
SDA SCL VLC RESET VA AGND AINA AINB SGND AFILTA AFILTB VQ FILT+ MICIN1 MICIN2
# 1 2 3 4 5 6 7, 8 9
Pin Description
Serial Control Data (Input/Output) - Bidirectional data line for the IC control port. Serial Control Port Clock (Input) - Serial clock for the IC control port. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Analog Input (Input) - The full scale level is specified in the ADC Analog Characteristics specification table. Signal Ground (Input) - Ground reference for the analog line inputs.
10, Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs. 11 12 13
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
14, Microphone Input (Input) - The full scale level is specified in the ADC Analog Characteristics specifica15 tion table.
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MICBIAS
SGND
AFILTA
AFILTB
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MICBIAS VA AGND AOUTA AOUTB MUTEC VLS TXSDIN SDIN2 SDIN1 SDOUT SCLK LRCK MCLK DGND VD TXOUT Thermal Pad
16 17 18
Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section.
19, Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris20 tics specification table. 21 22 23 24 25 26 27 28 29 30 31 32 Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock left/right clock frequency ratio is incorrect, or power-down. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Transmitter Serial Audio Data Input (Input) - Input for two's complement serial audio data. Serial Audio Data Input 2 (Input) - Input for two's complement serial audio data. Serial Audio Data Input 1 (Input) - Input for two's complement serial audio data. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) -Clock source for the delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Transmitter Line Driver Output (Output) - IEC60958-3 driver output. Thermal Pad - Thermal relief pad for optimized heat dissipation.
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2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to
ground.) Parameters Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) DC Power Supplies: Symbol VA VD VLS VLC TA Min 3.1 3.1 1.71 1.71 -10 Nom 5.0 3.3 3.3 3.3 Max 5.25 5.25 5.25 5.25 +70 Units V V V V C
ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V All voltages with respect to ground.) (Note
1) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 2) Logic - Serial Port Logic - Control Port Symbol VA VD VLS VLC Iin VINA VIND-S VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -20 -65 Typ Max +6.0 +6.0 +6.0 +6.0 10 VA+0.3 VLS+0.3 VLC+0.3 +85 +150 Units V V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage
Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up.
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DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load RL = 3 k, CL = 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)
All Speed Modes Parameter Dynamic Performance for VA = 5 V Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit (Note 3) unweighted A-Weighted unweighted A-Weighted (Note 3) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (Note 3) unweighted A-Weighted unweighted A-Weighted (Note 3) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) 96 99 87 90 102 105 93 96 -95 -82 -42 -93 -73 -33 -89 -76 -36 -87 -67 -27 dB dB dB dB dB dB dB dB dB dB Symbol Min Typ Max Unit
16-Bit
Dynamic Performance for VA = 3.3 V Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 93 96 85 88 0.60*VA (Note 4) (Note 5) (Note 5) IOUT RL CL ZOUT 3 99 102 90 93 -92 -79 -39 -90 -70 -30 100 0.1 100 0.65*VA 100 -84 -71 -31 -82 -62 -22 0.25 0.70*VA 10 100 dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp A k pF
16-Bit
Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale Output Voltage DC Current draw from an AOUT pin AC-Load Resistance Load Capacitance Output Impedance Note:
3. One-half LSB of triangular PDF dither added to data. 4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors. 5. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable.
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DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 6,9) Combined Digital and On-chip Analog Filter Response Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Combined Digital and On-chip Analog Filter Response Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Notes: 6. Filter response is guaranteed by design. 7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 8. De-emphasis is available only in Single Speed Mode. 9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. (Note 7) tgd to -0.1 dB corner to -3 dB corner (Note 7) tgd Fs = 44.1 kHz to -0.1 dB corner to -3 dB corner Combined Digital and On-chip Analog Filter Response (Note 7) tgd to -0.05 dB corner to -3 dB corner Symbol Min 0 0 -.01 .5465 50 0 0 -.05 .5770 55 0 0 0 0.7 51 Typ 10/Fs 5/Fs 2.5/Fs Max .4780 .4996 +.08 +.05/-.25 .4650 .4982 +.2 0.397 0.476 +0.00004 Unit Fs Fs dB Fs dB s dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s Single Speed Mode
Double Speed Mode
Quad Speed Mode
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125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
3.3 F AOUTx R L C L V out
AGND
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 1. DAC Output Test Load
Figure 2. Maximum DAC Loading
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ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz.
Line Level Inputs Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Symbol Min Typ Max Unit
99 96 -
105 102 99
-
dB dB dB
93 90 THD+N
99 96 93
-
dB dB dB
(Note 12)
-
-95 -82 -42 -92
-89 -
dB dB dB dB
PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 12) 40 kHz bandwidth -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted
-
-92 -76 -36 -89
-86 -
dB dB dB dB
94 91 -
102 99 96
-
dB dB dB
(Note 12)
90 87 -
96 93 90
-
dB dB dB
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Total Harmonic Distortion + Noise (Note 11) THD+N
(Note 12)
PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Line Level Inputs Symbol
-
-92 -79 -39 -84
-86 -
dB dB dB dB
(Note 12)
Min 0.53*VA 6.12 -
-89 -73 -33 -81 Typ 90 0.56*VA 6.8 5
-83 Max 0.59*VA 7.48 -
dB dB dB dB Unit dB Vpp k %
Parameter Interchannel Isolation Line Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 10) Maximum Interchannel Input Impedance Mismatch
Line Level and Microphone Level Inputs Parameter DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Programmable Gain Characteristics Gain Step Size Absolute Gain Step Error 10. Valid when the line level inputs are selected. Symbol Min Typ 0.1 Max Unit dB % ppm/C dB dB
100
0.5 -
5
0.4
12
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ADC ANALOG CHARACTERISTICS
Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Interchannel Isolation Microphone Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 13) (cont)
Microphone Level Inputs Symbol Min Typ Max Unit
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
-
-68
-
dB
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
0.013*VA -
-68 30 0.014*VA 50
0.015*VA -
dB dB Vpp k
11. Referred to the typical line level full-scale input voltage 12. Valid for Double and Quad Speed Modes only. 13. Valid when the microphone level inputs are selected.
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ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 14, 16) Single Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Quad Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Note: 14. Filter response is guaranteed by design. 15. Response shown is for Fs = 48 kHz. 16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 30 to 41) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20 Hz (Note 15) (Note 15) 1 20 10 10 /Fs
5
Symbol
Min 0 0.5688 70
Typ 12/Fs 9/Fs 5/Fs
Max 0.4896 0.035 0.4896 0.025 0.2604 0.025 0
Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
(-0.1 dB)
tgd
0 0.5604 69
(-0.1 dB)
tgd
0 0.5000 60
(-0.1 dB)
tgd
-
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DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to
ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode) Parameter Power Supply Current (Normal Operation) VA = 5 VA = 3.3 VD, VLS, VLC = 5 VD, VLS, VLC = 3.3 V V V V Symbol IA IA ID ID IA ID PSRR VQ (Note 19) IQ ZQ FILT+ MICBIAS IMB Min Typ 41 37 39 23 0.50 0.54 400 198 4.2 60 0.5 x VA 23 VA 0.8 x VA Max 50 45 47 28 485 241 1 2 Unit mA mA mA mA mA mA mW mW mW dB VDC A k VDC VDC mA
Power Supply Current. (Power-Down Mode) (Note 17). Power Consumption (Normal Operation). (Power-Down Mode). VQ Characteristics Quiescent Voltage DC Current from VQ VQ Output Impedance FILT+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS
VA = 5 V VLS, VLC, VD=5 V
VA, VD, VLS, VLC = 5 V VA, VD, VLS, VLC = 3.3 V VA, VD, VLS, VLC = 5 V (Note 18)
Power Supply Rejection Ratio (1 kHz)
Notes: 17. Power Down Mode is defines as RESET = Low with all clock and data lines held static and no analog input. 18. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. 19. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors.
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DIGITAL INTERFACE CHARACTERISTICS
Parameters (Note 20) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io=2 mA Symbol Serial Port VIH Control Port VIH VIL Serial Port VIL Control Port Serial Port Control Port MUTEC TXOUT Serial Port Control Port MUTEC TXOUT (Note 21) VOH VOH VOH VOH VOL VOL VOL VOL Iin Min 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 VA-1.0 VD-1.0 Typ 3 Max 0.2xVLS 0.2xVLC 0.4 0.4 0.4 0.4 10 1 Units V V V V V V V V V V V V A pF mA
Low-Level Output Voltage at Io=2 mA
Input Leakage Current Input Capacitance Maximum MUTEC Drive Current
Notes: 20. Serial Port signals include: MCLK, SCLK, LRCK, SDIN1, SDIN2, TXSDIN, SDOUT. Control Port signals include: SCL, SDA, RESET. 21. Guaranteed by design.
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic `0' = DGND = 0 V;
Logic `1' = VL, CL = 20 pF) (Note 22) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 45 tslr tsdo tsdis tsdih -10 0 16 20 40 Single Speed Mode Double Speed Mode Quad Speed Mode SCLK Pulse Width High SCLK Pulse Width Low SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Notes: 22. See figures 3 and 4 on page 18. tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdo tsdis tsdih
10 -------------------( 128 )Fs 10 ----------------( 64 )Fs 10 ----------------( 64 )Fs
9 9 9
Typ 50 50 50 50 -
Max 50 100 200 51.200 55 10 32 60 10 32 -
Unit kHz kHz kHz MHz ns % % % ns ns ns ns % ns ns ns ns ns ns ns ns ns
MCLK Specifications MCLK Frequency MCLK Input Pulse Width High/Low MCLK Output Duty Cycle Master Mode LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Slave Mode LRCK Duty Cycle SCLK Period
30 48 -10 0 16 20
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LRCK O utput
t SCLK O utput t SDO UT
slr
sdo
t SDIN
sdis
t
sdih
Figure 3. Master Mode Serial Audio Port Timing
LRCK Input t sclkh t
t SCLK Input t SDOUT
slr
sclkl
t sdo
sclkw
t SDIN
sdis
t
sdih
Figure 4. Slave Mode Serial Audio Port Timing
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LR C K SCLK
Left C A - Left Channel ha nnel
Channel B - Right R igh t C ha nnel
SDATA
M SB -1 -2 -3 -4 -5
+ 5 + 4 + 3 +2 +1 LS B
M SB -1 -2 -3 -4
+ 5 + 4 + 3 + 2 + 1 LS B
Figure 5. Format 0, Left Justified up to 24-Bit Data
LR C K SCLK
Channel ha nnel Left C A - Left
RChannel B nnel igh t C ha - Right
SDATA
MSB -1 -2 -3 -4 -5
+ 5 +4 +3 + 2 +1 LSB
MSB -1 -2 -3 -4
+5 + 4 +3 +2 + 1 LSB
Figure 6. Format 1, IS up to 24-Bit Data
LRCK
Channel A - Left Left Channel
Channel B - Right Right Channel
SCLK
SDATA
LS B
M B-1 -2 -3 -4 -5 -6 S
B +6 +5 +4 +3 +2 +1 LS
M B -1 -2 -3 -4 -5 -6 S
B +6 +5 +4 +3 +2 +1 LS
32 clocks
Figure 7. Format 2, Right Justified 16-Bit Data. Format 3, Right Justified 24-Bit Data.
DS657A2
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CS4265
SWITCHING CHARACTERISTICS - IC CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 24) (Note 24) (Note 23) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns
Notes: 23. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 24. Guaranteed by design.
RST t S to p irs S ta rt R e p e a te d S t a rt t rd t fd S to p
SDA t buf t h d st t h igh t h d st t fc t su sp
SCL t t t su d t a ck t su st t rc
lo w
hdd
Figure 8. Control Port Timing - IC Format
20
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3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V 10 F 0.1 F 0.1 F 0.1 F 10 F
+3.3V to +5V
VD +1.8V to +5V 0.1 F
47 k Note 4
VA
VA MUTEC
3.3 F Mute Drive 470 10 k See Note 2
VLS
AOUTA SDOUT
* *
C C
10 k
Optional Analog Muting
Rext Rext
SDIN1 SDIN2 Digital Audio Processor TXSDIN MCLK SCLK LRCK
AOUTB
3.3 F Note 2 : 470
CS4265
For best response to Fs/2 :
C=
Rext + 470 4Fs(Rext x 470 )
This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. 10 F 100 100 k
Digital Audio Output
TXOUT
AIN1A
10 F
Left Analog Input 1 Signal Ground
* 1800 pF * 1800 pF
SGND
100 k 100
RST MicroController SCL SDA
AIN1B
10 F 10 F
Right Analog Input 1
MICIN1 MICIN2
Microphone Input 1 Microphone Input 2
10 F RL RL
2 k +1.8V to +5V
Note 1
2 k VLC 0.1 F MICBIAS FILT+
Note 3
10 F
Note 1: Resistors are required for IC control port operation Note 3: The value of RL is dictated by the microphone carteridge. Note 4: Sets the LSB of the 7-bit chip address. See the IC Control Port Description and Timing section.
AGND AGND AFILTA AFILTB VQ DGND
0.1 F * * 2.2nF
47 F
2.2nF
0.1 F
10 F
* Capacitors must be C0G or equivalent
Figure 9. Typical Connection Diagram
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CS4265
4. APPLICATIONS 4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings. 2) Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3) The desired register settings can be loaded while the PDN bit remains set. 4) Clear the PDN bit to initiate the power-up sequence.
4.2
System Clocking
The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1 below. Mode Single Speed Double Speed Quad Speed Sampling Frequency 4-50 kHz 50-100 kHz 100-200 kHz
Table 1. Speed Modes
4.2.1
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (see page 35) and the MCLK Freq bits (see page 36) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies.
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LRCK (kHz) 32 44.1 48 64 88.2 96 128 176.4 192 Mode
MCLK (MHz) 64x 8.1920 11.2896 12.2880 96x 12.2880 16.9344 18.4320 128x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 QSM Table 2. Common Clock Frequencies 192x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 256x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 384x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 DSM 512x 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 768x 24.5760 33.8680 36.8640 SSM 1024x 32.7680 45.1584 49.1520 -
4.2.2
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 10.
MC LK F re q B its /256 /1 /1.5 MC LK /2 /3 /4 000 001 010 011 100 /1 10 /4 /2 /128 /64 F M B its 00 01 S C LK 00 01 10 LR C K
Figure 10. Master Mode Clocking
4.2.3
Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, MCLK. The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed mode. Refer to Table 3 for required clock ratios. Single Speed SCLK/LRCK Ratio 32x, 48x, 64x, 128x Double Speed 32x, 48x, 64x Quad Speed 32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3
High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven into the A/D converter. The CS4265 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
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CS4265
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit (see page 35) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS4265 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Characteristics section for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4265.
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer is able to select either a line-level input source, or a mic-level input source and route it to the PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. The PGA stage provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 11 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AINA MUX MICIN1
+32 dB
PGA Channel A PGA Gain Bits Channel B PGA Gain Bits PGA
Out to ADC Channel A
Analog Input Selection Bits
AINB MUX MICIN2
+32 dB
Out to ADC Channel B
Figure 11. Analog Input Architecture
The "Analog Input Selection (Bit 0)" section on page 38 outlines the bit settings necessary to control the input multiplexer and mic gain. "Channel A PGA Control - Address 07h" on page 36 and "Channel B PGA Control - Address 08h" on page 37 outlines the register settings necessary to control the PGA. By default, the line level input is selected by the input multiplexer, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.5.1
Pseudo-Differential Input
The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a pseudodifferential reference signal. This feature allows for common mode noise rejection with single-ended signals. Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-differential input stage. The Typical Connection Diagram shows the recommended pseudo-differential input topology. If pseudo-differential input
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functionality is not required, simply connect the SGND pin to AGND through the parallel combination of a 10 F and a 0.1 F capacitor.
CS4265
A IN A VA
10 F
In to P G A +
SGND
0.1 F
+ In to P G A -
A IN B
N ote: If pseudo-differential input functionality is not required, the connections shown with dashed line should be added.
Figure 12. Pseudo-Differential Input Stage
4.6
Output Connections
The CS4265 DAC's implement a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is shown in the "DAC Filter Plots" section beginning on page 45. The recommended external analog circuitry is shown in the Typical Connection Diagram. The CS4265 DAC is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
4.7
Output Transient Control
The CS4265 uses PopguardTM technology to minimize the effects of output transients during power-up and powerdown. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1
Power-up
When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ which is initially low. After the PDN bit is released (set to `0'), the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2
Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either the PDN should be set or the device should be reset about 250 ms before removing power. During this time, the voltage on VQ and the DAC outputs will gradually discharge to GND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle, power may be re-applied at any time.
4.7.3
Serial Interface Clock Changes
When changing the clock ratio or sample rate it is recommended that zero data (or near zero data) be present on the selected SDIN pin for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it's zero data state. DS657A2 25
CS4265
4.8 DAC Serial Data Input Multiplexer
The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two separate data sources to be input into the DAC without the use of any external multiplexing components. The "DAC SDIN Source (Bit 7)" section on page 36 describes the control port settings necessary to control the multiplexer.
4.9
De-Emphasis Filter
The CS4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 13. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 6.3.3 for de-emphasis control. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single Speed Mode.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 13. De-Emphasis Curve
4.10 Internal Digital Loopback
The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (06h - See page 36). When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265. Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin in the format selected by the ADC_DIF bit in register 04h.
4.11 Mute Control
The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is incorrect, and during power-down. The MUTEC pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
26
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channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an activelow CMOS driver. See Figure 14 below for a suggested active-low mute circuit.
+V E E AC Couple AO UT LP F 47 k -V E E
560
A udio O ut
CS4265
+V A MMU N 2111LT1 MU TE C 2 k
10 k
-V E E
Figure 14. Suggested Active-Low Mute Circuit
4.12 AES3 Transmitter
The CS4265 includes an IEC60958-3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status data. This buffering scheme is described in "Channel Status Buffer Management" on page 50. The IEC60958-3 transmitter encodes and transmits audio and digital data according to the IEC60958-3 (S/PDIF) interface standard. Audio and control data are multiplexed together and bi-phase mark encoded. The resulting bit stream is driven to an output connector either directly or through a transformer. The transmitter is clocked from the clock input pin MCLK. The channel status (C) bits in the transmitted data stream are taken from storage areas within the CS4265. The user can manually access the internal storage of the CS4265 to configure the transmitted channel status data. The section "Channel Status Buffer Management" on page 50 describes the method of manually accessing the storage areas. The CS4265 transmits all `0's in the user (U) data fields.
4.12.1 TxOut Driver
The line driver is a low skew, low impedance, single-ended output capable of driving cables directly. The driver is set to ground during reset (RESET = LOW), when no transmit clock is provided, and optionally under the control of a register bit. The CS4265 also allows immediate muting of the IEC60958-3 transmitter audio data through a control register bit. External components are used to terminate and isolate the external cable from the CS4265. These components are detailed in "External IEC60958-3 Transmitter Components" on page 49.
4.12.2 Mono Mode Operation
An IEC60958-3 stream may be used in more than one way to transmit 192 kHz sample rate data. One method is to double the frame rate of the current format. This results is a stereo signal with a sample rate of 192 kHz. An alternate method is implemented using the two sub-frames in a 96 kHz frame rate IEC60958-3 signal to carry consecutive samples of a mono signal, resulting in a 192 kHz sample rate stream. This allows older equipment, whose IEC60958-3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample
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CS4265
rate information. In this "mono mode", two cables are needed for stereo data transfer. The CS4265 offers mono mode operation. The CS4265 is set placed into and out of mono mode with the MMT control bit. In mono mode, the input port will run at the audio sample rate (Fs), while the IEC60958-3 transmitter frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable. Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains both left and right audio data words. The "mono mode" IEC60958-3 output stream may also be achieved by keeping the CS4265 in normal stereo mode, and placing consecutive audio samples in the left and right positions in an incoming 96 kHz word rate data stream.
4.13 IC Control Port Description and Timing
The control port is used to access the registers, allowing the CS4265 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 k pull-up or pulldown on the SDOUT pin will set AD0, the least significant bit of the chip address. A pull-up to VLS will set AD0 to `1' and a pull-down to DGND will set AD0 to `0'. The state of SDOUT is sensed and AD0 is set upon the release of RESET. The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100111. To communicate with a CS4265, the chip address field, which is the first byte sent to the CS4265, should match 100111 followed by the setting of AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to the CS4265 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
1
1 AD0 0
6
5
4
3
ACK START
ACK
ACK
ACK STOP
Figure 15. Control Port Timing, IC Write
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0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 1 1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1
1
AD0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 16. Control Port Timing, IC Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition. Send 100111x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.14 Status Reporting
The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status register, as listed in the status register descriptions. See "Status - Address 0Dh" on page 39. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
4.15
Reset
When RESET is low, the CS4265 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RESET is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low power state and begin operation. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RESET pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
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CS4265
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
4.16 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS4265's in the system. If only one master clock source is needed, one solution is to place one CS4265 in Master Mode, and slave all of the other CS4265's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4265 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on the same clock edge.
4.17 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4265 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 9 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS4265 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS4265 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4265 digital outputs only to CMOS inputs.
4.18 Package Considerations
The CS4265 is available in the compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS4265 evaluation board demonstrates the optimum thermal pad and via configuration.
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5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. Addr Function 7
PART3 1 02h Power Control 03h DAC Control 1 04h ADC Control 05h MCLK Frequency 06h Signal Selection Freeze 0 0 FM1 0 Reserved 0 SDINSel 0
6
PART2 1 0 0 FM0 0 MCLK Freq2 0
5
PART1 0 0 0 Reserved 0 MCLK Freq1 0
4
PART0 1 Reserved 0 0 ADC_DIF 0 MCLK Freq0 0 Reserved 0 Gain4 0 Gain4 0 PGASoft 1 Vol4 0 Vol4 0 0 EFTC 0 EFTCM 0 EFTC1 0 EFTC0 0
3
REV3 0 PDN_MIC 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Gain3 0 Gain3 0 PGAZero 1 Vol3 0 Vol3 0 Reserved 0 ClkErr 0 ClkErrM 0 ClkErr1 0 ClkErr0 0
2
REV2 0 PDN_ADC 0 MuteDAC 0 MuteADC 0 Reserved 0 Reserved 0 Gain2 0 Gain2 0 Reserved 0 Vol2 0 Vol2 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
1
REV1 0 PDN_DAC 0 DeEmph 0 HPFFreeze 0 Reserved 0 LOOP 0 Gain1 0 Gain1 0 Reserved 0 Vol1 0 Vol1 0 Reserved 0 ADCOvfl 0 ADCOvflM 0 ADCOvfl1 0 ADCOvfl0 0
0
REV0 1 PDN 1 Reserved 0 M/S 0 Reserved 0 Reserved 0 Gain0 0 Gain0 0 Select 1 Vol0 0 Vol0 0 Reserved 0 ADCUndrfl 0 ADCUndrflM 0 ADCUndrfl1 0 ADCUndrfl0 0
01h Chip ID
Reserved Reserved
Reserved Reserved DAC_DIF1 DAC_DIF0
Reserved Reserved 1 0 Gain5 0 Gain5 0
07h PGA Ch B Gain Reserved Reserved Control 0 0 08h PGA Ch A Gain Reserved Reserved Control 0 09h Analog Input Control 0Ah DAC Ch A Volume Control 0Bh DAC Ch B Volume Control 0Ch DAC Control 2 0Dh Status 0Eh Status Mask 0Fh Status Mode MSB 10h Status Mode LSB 0
Reserved Reserved Reserved 0 Vol7 0 Vol7 0 DACSoft 1 0 0 0 Vol6 0 Vol6 0 1 0 0 0 Vol5 0 Vol5 0 0 0 0
DACZero InvertDAC Reserved
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved 0 0 0
Reserved Reserved Reserved 0 0 0
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CS4265
Addr Function 7
Reserved 0 12h Transmitter Control 2 13h - C-Data Buffer 2Ah Tx_DIF1 0 -
6
EFTCI 0 Tx_DIF0 0 -
5
CAM 0 TxOff 0 -
4
Reserved 0 TxMute 0 -
3
Reserved 0 V 0 -
2
Reserved 0 MMT 0 -
1
Reserved 0 MMTCS 0 -
0
Reserved 0 MMTLR 0 -
11h Transmitter Control 1
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6. 6.1 REGISTER DESCRIPTION Chip ID - Register 01h
B6 PART2 B5 PART1 B4 PART0 B3 REV3 B2 REV2 B1 REV1 B0 REV0 B7 PART3
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID which is 1101b (0Dh) and the remaining bits (3 through 0) are for the chip revision.
6.2
Power Control - Address 02h
6 Reserved 5 Reserved 4 Reserved 3 PDN_MIC 2 PDN_ADC 1 PDN_DAC 0 PDN
7 Freeze
6.2.1
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in Table 4 below. Table 4. Freeze-able Bits Name MuteDAC MuteADC Gain[5:0] Gain[5:0] Vol[7:0] Vol[7:0] TxMute Register 03h 04h 07h 08h 0Ah 0Bh 0Eh Bit(s) 2 2 5:0 5:0 7:0 7:0 4
6.2.2
Power Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3
Power Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4
Power Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5
Power Down Device (Bit 0)
Function:
DS657A2
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CS4265
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down.
6.3
7
DAC Control - Address 03h
6 Reserved 5 DAC_DIF1 4 DAC_DIF0 3 Reserved 2 MuteDAC 1 DeEmph 0 Reserved
Reserved
6.3.1
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 5 and Figures 5-7. Table 5. DAC Digital Interface Formats DAC_DIF1 DAC_DIF0 0 0 0 1 1 1 0 1 Description Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Format 0 1 2 3 Figure 5 6 7 7
6.3.2
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the DACSoft and DACZero bits in the DAC Control 2 register.
6.3.3
De-Emphasis Control (Bit 1)
Function:
The standard 50/15 s digital de-emphasis filter response, Figure 17, may be implemented for a sample rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 6 below. NOTE: De-emphasis is available only in Single-Speed Mode. Table 6. De-Emphasis Control DeEmph 0 1 Description Disabled (default) 44.1 kHz de-emphasis
6.4
7
ADC Control - Address 04h
6 FM0 5 Reserved 4 ADC_DIF 3 Reserved 2 MuteADC 1 HPFFreeze 0 M/S FM1
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Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 17. De-Emphasis Curve
6.4.1
Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates. Table 7. Functional Mode Selection FM1 0 0 1 1 FM0 0 1 0 1 Mode Single-Speed Mode: 4 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved
6.4.2
ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the ADC Digital Interface Format bit. The options are detailed in Table 8 and may be seen in Figure 5 and 6. Table 8. ADC Digital Interface Formats ADC_DIF 0 1 Description Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Format 0 1 Figure 5 6
6.4.3
Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels will be muted.
6.4.4
ADC High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "High Pass Filter and DC Offset Calibration" on page 23.
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6.4.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit will select master mode, while clearing this bit will select slave mode.
6.5
7
MCLK Frequency - Address 05h
6 MCLK Freq2 5 MCLK Freq1 4 MCLK Freq0 3 Reserved 2 Reserved 1 Reserved 0 Reserved
Reserved
6.5.1
Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 9 below for the appropriate settings. Table 9. MCLK Frequency MCLK Divider /1 / 1.5 /2 /3 /4 Reserved Reserved MCLK Freq2 0 0 0 0 1 1 1 MCLK Freq1 0 0 1 1 0 0 1 MCLK Freq0 0 1 0 1 0 1 x
6.6
7
Signal Selection - Address 06h
6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 LOOP 0 Reserved
SDINSel
6.6.1
DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 10 below. Table 10. DAC SDIN Source Selection SDINSel Setting 0 1 DAC Data Source SDIN1 SDIN2
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to "Internal Digital Loopback" on page 26.
6.7
Channel A PGA Control - Address 07h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
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6.7.1 Channel A PGA Gain (Bits 5:0)
Function:
See "Channel B PGA Gain (Bits 5:0)" on page 37.
6.8
Channel B PGA Control - Address 08h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
6.8.1
Channel B PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two's complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the 12 dB range are reserved and must not be used. See Table 11 for example settings. Table 11. Example Gain and Attenuation Settings Gain[5:0] 101000 000000 011000 Setting -12 dB 0 dB +12 dB
6.9
ADC Input Control - Address 09h
6 Reserved 5 Reserved 4 PGASoft 3 PGAZero 2 Reserved 1 Reserved 0 Select
7 Reserved
6.9.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 12 on page 38. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 12 on page 38. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 12 on page 38.
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Table 12. PGA Soft Cross or Zero Cross Mode Selection PGASoft 0 0 1 1 PGAZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
6.9.2
Analog Input Selection (Bit 0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 13 below. Table 13. Analog Input Selection Select 0 1 PGA/ADC Input Microphone Level Input Line Level Input
6.10 DAC Channel A Volume Control - Address 0Ah
See 6.11 DAC Channel B Volume Control - Address 0Bh
6.11 DAC Channel B Volume Control - Address 0Bh
7 Vol7 6 Vol6 5 Vol5 4 Vol4 3 Vol3 2 Vol2 1 Vol1 0 Vol0
6.11.1 Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as shown in Table Table 14. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the DAC Control 2 register (see section 6.12.1). Table 14. Digital Volume Control Example Settings Binary Code 00000000 00000001 00101000 00101001 11111110 11111111 Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB
6.12 DAC Control 2 - Address 0Ch
7 DACSoft 6 DACZero 5 InvertDAC 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved
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6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 15 on page 39. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 15 on page 39. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 15 on page 39. Table 15. DAC Soft Cross or Zero Cross Mode Selection DACSoft 0 0 1 1 DACZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC will be inverted.
6.13 Status - Address 0Dh
7 Reserved 6 Reserved 5 Reserved 4 EFTC 3 ClkErr 2 Reserved 1 ADCOvfl 0 ADCUndrfl
For all bits in this register, a `1' means the associated condition has occurred at least once since the register was last read. A `0' means the associated condition has NOT occurred since the last reading of the register. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
6.13.1 E to F C-buffer Transfer
Function:
Indicates the completion of an E to F C-buffer transfer. See "Channel Status Buffer Management" on page 50 for more information.
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6.13.2 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.14 Status Mask - Address 0Eh
7 Reserved 6 Reserved 5 Reserved 4 EFTCM 3 ClkErrM 2 Reserved 1 ADCOvflM 0 ADCUndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register "Status - Address 0Dh" on page 39. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status register. The bit positions align with the corresponding bits in the Status register.
6.15 Status Mode MSB - Address 0Fh 6.16 Status Mode LSB - Address 10h
7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 EFTC1 EFTC0 3 ClkErr1 ClkErr0 2 Reserved Reserved 1 ADCOvfl1 ADCOvfl0 0 ADCUndrfl1 ADCUndrfl0
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to update the Status register in accordance with the status condition. In the Rising edge active mode, the status bit becomes active on the arrival of the condition. In the Falling edge active mode, the status bit becomes active on the removal of the condition. In Level active mode, the status bit is active during the condition. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
6.17 Transmitter Control 1 - Address 11h
7 Reserved 6 EFTCI 5 CAM 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)
Function:
When cleared, C-data E to F buffer transfers are allowed. When set, C-data E to F buffer transfers are inhibited. See "IEC60958-3 Channel Status (C) Bit Management" on page 50.
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6.17.2 C-Data Access Mode (Bit 5)
Function:
When cleared, the C-data buffer will operate in One-byte control port access mode. When set, the Cdata buffer will operate in Two-byte control port access mode. See "IEC60958-3 Channel Status (C) Bit Management" on page 50.
6.18 Transmitter Control 2 - Address 12h
7 Tx_DIF1 6 Tx_DIF0 5 TxOff 4 TxMute 3 V 2 MMT 1 MMTCS 0 MMTLR
6.18.1 Transmitter Digital Interface Format (Bits 7:6)
Function:
The required relationship between LRCK, SCLK and SDIN for the transmitter is defined by the Transmitter Digital Interface Format and the options are detailed in Table 16 and Figures 5-7. Table 16. Transmitter Digital Interface Formats Tx_DIF1 0 0 1 1 Tx_DIF0 0 1 0 1 Description Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Format 0 1 2 3 Figure 5 6 7 7
6.18.2 Transmitter Output Driver Control (Bit 5)
Function:
When this bit is cleared, the transmitter output pin driver will be in the normal operational mode. When set, the transmitter output pin driver will drive to a constant 0 V.
6.18.3 Transmitter Mute Control (Bit 4)
Function:
When this bit is cleared, the transmitter data will be in the normal operational mode. When set, the transmitter will output all zero data.
6.18.4 Transmitted Validity Bit Control (Bit 3)
Function:
This bit sets the transmitted Validity bit level. When this bit is cleared, valid linear PCM audio data is indicated. When this bit is set, invalid or nonlinear PCM audio data is indicated.
6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2)
Function:
When this bit is cleared, the transmitter will operate in stereo mode. When set, the transmitter will operate in mono mode with one input channel's data output in both A and B subframes (see "IEC609583 Channel Status (C) Bit Management" on page 50) and the CS data defined by the MMTCS bit (see section 6.18.6).
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6.18.6 Mono Mode CS Data Source (Bit 1)
Function:
When this bit is cleared, the transmitter will transmit the channel A CS data in the A subframe and the channel B CS data in the B subframe. When this bit is set, the transmitter will transmit the CS data defined for the channel selected by the MMTLR bit in both the A and B subframes.
6.18.7 Mono Mode Channel Selection (Bit 0)
Function:
When this bit is cleared, channel A input data will be transmitted in both channel A and B subframes in mono mode. When this bit is set, channel B input data will be transmitted in both channel A and B subframes in mono mode.
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7. PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
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8. PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
D b e Pin #1 Corner
Pin #1 Corner
E
E2
A1 A Top View Side View
L
D2
Bottom View
DIM A A1 b D D2 E E2 e L
MIN -0.0000 0.0071 0.1280 0.1280 0.0118
INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157
MAX 0.0394 0.0020 0.0110 0.1319 0.1319 0.0197
MIN -0.00 0.18 3.25 3.25 0.30
MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40
NOTE MAX 1.00 0.05 0.28 3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1
JEDEC #: MO-220 Controlling Dimension is Millimeters. Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip.
9. THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance (Note 3) Allowable Junction Temperature Symbol 32-QFN JA JC Min Typ 38 52 Max 125 Units C/Watt C/Watt C
Notes: 3. JA is specified according to JEDEC specifications for multi-layer PCBs.
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APPENDIX A: DAC FILTER PLOTS
Figure 18. DAC Single Speed Stopband Rejection
Figure 19. DAC Single Speed Transition Band
Figure 20. DAC Single Speed Transition Band
Figure 21. DAC Single Speed Passband Ripple
Figure 22. DAC Double Speed Stopband Rejection
Figure 23. DAC Double Speed Transition Band
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Figure 24. DAC Double Speed Transition Band
0
Figure 25. DAC Double Speed Passband Ripple
0
-10
-10
-20
-30
-20
-40 Amplitude (dB)
Amplitude (dB) -30
-50
-60
-40
-70
-50
-80
-60
-90
-100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1
0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75
Figure 26. DAC Quad Speed Stopband Rejection
0
Figure 27. DAC Quad Speed Transition Band
0.2
-5 0.15 -10 -15 -20 -25 -30 -35 -0.1 -40 -0.15 -45 -0.2 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.1
0.05 Amplitude (dB)
Amplitude (dB)
0
-0.05
Figure 28. DAC Quad Speed Transition Band
Figure 29. DAC Quad Speed Passband Ripple
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APPENDIX B: ADC FILTER PLOTS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 30. ADC Single Speed Stopband Rejection
Figure 31. ADC Single Speed Stopband Rejection
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 32. ADC Single Speed Transition Band (Detail)
Figure 33. ADC Single Speed Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 34. ADC Double Speed Stopband Rejection
Figure 35. ADC Double Speed Stopband Rejection
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0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52
Amplitude (dB)
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 36. ADC Double Speed Transition Band (Detail)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Figure 37. ADC Double Speed Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Amplitude (dB)
Frequency (norm alized to Fs)
Amplitude (dB)
Frequency (norm alized to Fs)
Figure 38. ADC Quad Speed Stopband Rejection
Figure 39. ADC Quad Speed Stopband Rejection
0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-4 -5 -6 -7 -8 -9 -10 0.10
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 40. ADC Quad Speed Transition Band (Detail)
Figure 41. ADC Quad Speed Passband Ripple
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APPENDIX C: EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS
This section details the external components required to interface the IEC60958-3 transmitter to cables and fiberoptic components.
C.1
IEC60958-3 Transmitter External Components
The IEC60958-3 specifications call for an unbalanced drive circuit with an output impedance of 75 20% and a output drive level of 0.5 volts peak-to-peak 20% when measured across a 75 load using no cable. The circuit shown in Figure 42 provides the proper output impedance and drive level using standard 1% resistors. If VD is driven from +3.3 V, use resistor values of 243 in place of the 374 resistor and a 107 resistor in place of the 90.9 resistor. The standard connector for a consumer application is an RCA phono socket. The TXOUT pin may be used to drive TTL or CMOS gates as shown in Figure 43. This circuit may be used for optical connectors for digital audio as they typically implement TTL or CMOS compatible inputs. This circuit is also useful when driving multiple digital audio outputs as RS422 line drivers typically implement TTL compatible inputs.
374-R TXP TXO UT
CS4265
90.9
RCA P hon o
Figure 42. Consumer Output Circuit (VD = 5 V)
TXOUT
CS4265
TTL or CMOS Gate
Figure 43. TTL/CMOS Output Circuit
C.2
Isolating Transformer Requirements
Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection.
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APPENDIX D: CHANNEL STATUS BUFFER MANAGEMENT
The CS4265 has a comprehensive channel status (C) data buffering scheme which allows the user to manage the C data through the control port.
D.1
IEC60958-3 Channel Status (C) Bit Management
The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits). The user may read from or write to these RAM buffers through the control port. The CS4265 manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the input, synchronized to the output time base, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in Figure 44. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 13h) is the consumer/professional bit for channel status block A. The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used as the source of C data for the IEC60958-3 transmitter. The F buffer accepts block transfers from the E buffer.
A 8-bits B 8-bits
E
24 w ords
F
Transm it D ata Buffer
To AE S3 Transm itter
C ontrol Port
Figure 44. Channel Status Data Buffer Structure
D.1.1
Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register space of the CS4265, through the control port. The user can modify the data to be transmitted by writing to the E buffer. The user can configure the status register such that EFTC bit is set whenever an E to F transfer completes. With this configuration in place, periodic polling of the status register allows determination of the time periods acceptable for E buffer interaction. Also provided is an "E to F" inhibit bit. The "E to F" buffer transfer is disabled whenever the user sets this bit. This may be used whenever "long" control port interactions are occurring.
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A flowchart for reading and writing to the E buffer is shown in Figure 45. For writing, the sequence starts after an E to F transfer, which is based on the output timebase.
Begin Configure the EFTC status bit as Rising Edge active. Read the Status Register (Reg 0Dh)
Is the EFTC bit set?
No
Yes
Optionally set E to F inhibit Write E data If set, clear E to F inhibit
Figure 45. Flowchart for Writing the E Buffer
D.1.2
Serial Copy Management System (SCMS)
The CS4265 allows read/modify/write access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately.
D.1.3
Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the most significant byte is the A channel data, and the least significant byte is the B channel data (see Figure 44). There are two methods of accessing this memory, known as one byte mode and two byte mode. The desired mode is selected through a control register bit.
D.1.3.1 One Byte mode
In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One byte mode takes advantage of the often identical nature of A and B channel status data. When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is being done, the CS4265 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's auto increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.
D.1.3.2 Two Byte mode
There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS4265 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two
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bytes must now be input to the CS4265's control port. The A channel status data is first, B channel status data second.
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Release A1 A2
Date May 2004 September 2004
Changes Initial Advance Release.
- Updated descriptions of pins 3, 4, 5, and 6 on page 5. - Removed specifications for SPI control port. - Added specification for AD0 selection in the IC Control Port Description and Timing section on page 28. - Updated the typical connection diagram on page 21 to reflect the pin changes and AD0 selection method. - Added thermal pad to pin descriptions on page 6. - Added Package Considerations section on page 30. - Updated the Mic level input impedance specification on page 13.
Table 17. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
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Price & Availability of CS4265-CNZ

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