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CS5378 Low-power Single-channel Decimation Filter
Features
Single-channel Digital Decimation Filter
Multiple On-chip FIR and IIR Coefficient Sets Programmable Coefficients for Custom Filters Synchronous Operation
Description
The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS5378 with a CS3301/02 differential amplifier, a CS5371 modulator, and a CS4373 test DAC, a synchronous high-resolution measurement system can be designed quickly and easily. Digital filter coefficients for the CS5378 FIR and IIR filters are included on-chip for a simple setup, or they can be programmed for custom applications. Selectable digital filter decimation ratios produce output word rates from 4000 SPS to 1 SPS, resulting in measurement bandwidths ranging from 1600 Hz down to 400 mHz when using the on-chip coefficient sets. The CS5378 includes integrated peripherals to simplify system design: a low-jitter PLL for standard clock or manchester inputs, offset and gain corrections, a test DAC bit stream generator, a time break controller, and eight general-purpose I/O pins.
Integrated PLL for Clock Generation
1.024 MHz, 2.048 MHz, or 4.096 MHz Input Standard Clock or Manchester Input
Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 250 SPS 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS
Digital Gain and Offset Corrections Test DAC Bit-stream Generator
Sine Wave or Impulse Output Mode
Time Break Controller, General-purpose I/O Microcontroller or EEPROM Configuration Small-footprint, 28-pin SSOP Package Low Power Consumption
16 mW at 500 SPS OWR
Flexible Power Supplies
I/O Interface and PLL: 3.3 V or 5.0 V Digital Logic Core: 2.5 V, 3.3 V or 5.0 V
I
ORDERING INFORMATION See page 86.
VDDCORE
SS:EECS
VDDPAD
VDDPLL
DRDY
MISO
MOSI
SCK
PLL, Clock Generation Serial Interface Reset, Synchronization
CLK MCLK RESET SYNC MSYNC TIMEB
Time Break Controller Decimation and Filtering Engine
Test Bit Stream Controller
TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0
Modulator Data Interface
GPIO General Purpose I/O
MDATA
MFLAG
GNDPAD
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
GNDCORE
GNDPLL
OCT `05 DS639F1
CS5378
TABLE OF CONTENTS
1. General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1. 1.2. 1.3. 1.4. Digital Filter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Integrated Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 System Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Characteristics and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. System Design with CS5378 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Data Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2. Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3. Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5. Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.2. Reset Self-Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3. Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6. PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1. 6.2. 6.3. 6.4. 7.1. 7.2. 7.3. 7.4. 7.5. 8.1. 8.2. 8.3. 8.4. 8.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PLL Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Master Clock Jitter and Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 MSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Digital Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Modulator Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Test Bit Stream Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 EEPROM Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Example EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8. Configuration By EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Configuration By Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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9.1. 9.2. 9.3. 9.4. 9.5. 10.1. 10.2. 10.3. 10.4. 10.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Microcontroller Configuration Commands . . . . . . . . . . . . . . . . . . . . . . .33 Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .35 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Modulator Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Modulator Flag Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
10. Modulator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11. Digital Filter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.1. Filter Coefficient Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 11.2. Filter Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
12. SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1. 12.2. 12.3. 12.4. 13.1. 13.2. 13.3. 13.4. 13.5. 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. SINC1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 SINC Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 FIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 FIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 On-Chip FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Programmable FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 FIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IIR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IIR3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 On-Chip IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Programmable IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 IIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13. FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14. IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
15. Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.1. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
16. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.2. Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.3. Serial Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
17. Test Bit Stream Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
17.1. 17.2. 17.3. 17.4. 17.5. 17.6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 TBS Impulse Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
DS639F1
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17.7. TBS Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17.8. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
18. Time Break Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
18.1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.2. Time Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.3. Time Break Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
19. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
19.1. 19.2. 19.3. 19.4. 19.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 GPIO Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
20. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
20.1. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 20.2. Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
21. 22. 23. 24. 25.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Environmental, Manufacturing, & Handling Information . . . . . . . . . . 86 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LIST OF FIGURES
Figure 1. CS5378 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. MISO Read Timing in SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Serial Data Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing. . . . . . . . . . . . . . . . . . . . . 16 Figure 8. TBS Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Single-Channel System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Reset Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Synchronization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15. EEPROM Serial Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. 8 Kbyte EEPROM Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17. Serial Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. Microcontroller Serial Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. Modulator Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 21. Digital Filter Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 22. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 23. SINC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 24. SINC Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 25. FIR Filter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 26. FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DS639F1 4
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Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register SPICTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Command Register SPICMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register SPIDAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register SPIDAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Configuration Register CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Configuration Register GPCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Correction Register GAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Correction Register OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Bit Stream Configuration Register TBSCFG. . . . . . . . . . . . . . . . . . . . . Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . User Defined System Register SYSTEM1 . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS5378 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 50 51 52 54 56 58 58 59 60 63 64 67 68 69 70 72 73 74 75 76 77 78 79 80 81 82 83
LIST OF TABLES
Table 1. Microcontroller and EEPROM Configuration Commands . . . . . . . . . . . . . . . . . 9 Table 2. TBS Configurations Using On-Chip Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. SPI and Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. PLL and BOOT Mode Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. PLL Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Maximum EEPROM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. EEPROM Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8. Example EEPROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9. Microcontroller Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11. SINC Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 12. SINC1 and SINC2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 13. SINC3 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. FIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 15. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 16. Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. IIR Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 17. IIR Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 18. TBS Configurations Using On-Chip Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 19. TBS Impulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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CS5378
VDDCORE
SS:EECS
VDDPAD
VDDPLL
DRDY
MISO
MOSI
SCK
PLL, Clock Generation Serial Interface Reset, Synchronization
CLK MCLK RESET SYNC MSYNC TIMEB
Time Break Controller Decimation and Filtering Engine
Test Bit Stream Controller
TBSDATA GPIO7:BOOT GPIO6:PLL2 GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1 GPIO0
Modulator Data Interface
GPIO General Purpose I/O
MDATA
MFLAG
GNDPAD
Figure 1. CS5378 Block Diagram
1. GENERAL DESCRIPTION
The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378. 40, 25, 20, 10, 5, 1 SPS. * Flexible digital filter configuration. (See Figure 2) * * Cascaded SINC, FIR, and IIR filters with selectable output stage. Linear and minimum phase FIR low-pass filter coefficients included. 3 Hz Butterworth IIR high-pass filter coefficients included. FIR and IIR coefficients programmable to create a custom filter response.
1.1 Digital Filter Features
* * Single channel decimation filter for CS5371 modulator. Synchronous operation for simultaneous sampling in multi-sensor systems. * Internal synchronization of digital filter phase to an external SYNC signal.
Output word rates, including low bandwidth rates. Standard output rates: 4000, 2000, 1000, 500, 333, 250 SPS. Low bandwidth rates: 200, 125, 100, 50,
Digital gain correction to normalize sensor gain. Digital offset correction and calibration. Offset correction to remove measurement
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GNDPLL
CS5378
Modulator Input 512 kHz
Sinc Filter 2 - 64000
FIR1 4
FIR2 2
IIR1 1 Order
st
IIR2 2
nd
Order
Gain & DC Offset Corrections
Output to High Speed Serial Interface Output Word Rate from 4000 SPS ~ 1 SPS Figure 2. Digital Filtering Stages
DC offset. Calibration engine for automatic calculation of offset correction factor. *
-
Impulse output mode for transfer function characterization.
Time break controller to record system timing information. Dedicated TB status bit in the output data stream. Programmable output delay to match system group delay.
1.2 Integrated Peripheral Features
* Low jitter PLL to generate local clocks. * 1.024 MHz, 2.048 MHz, 4.096 MHz standard clock or manchester encoded input. *
Synchronous operation for simultaneous sampling in multi-sensor systems. MCLK / MSYNC output signals to synchronize external components. Asynchronous operation to 4 MHz for direct connection to system telemetry. Internal 8-deep data FIFO for flexible output timing. Selectable 24-bit data only or 32-bit status+data output.
8 General Purpose I/O (GPIO) pins for local hardware control.
1.3 System Level Features
* Flexible configuration options. * Configuration 'on-the-fly' via microcontroller or system telemetry. Fixed configuration via stand-alone boot EEPROM. 16 mW at 500 SPS OWR. 100 W standby mode. Separate digital logic core, telemetry I/O,
*
High speed serial data output. -
Low power consumption. -
*
Digital test bit stream signal generator suitable for CS4373 test DAC. Sine wave output mode for testing total harmonic distortion.
*
Flexible power supply configurations. -
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and PLL power supplies. * Telemetry I/O and PLL interfaces operate from 3.3 V or 5 V. Digital logic core operates from 2.5 V, 3.3 V or 5 V. Total footprint 8 mm x 10 mm plus three bypass capacitors. * tion during operation. EEPROM boot sets a fixed operational configuration.
Configuration commands written through the serial interface. (See Table 1) Standardized microcontroller interface using SPI registers. (See Table 3) Commands write digital filter registers and FIR / IIR filter coefficients. Digital filter registers set hardware configuration options.
Small 28-pin SSOP package. -
1.4 Configuration Interface
* Configuration from microcontroller or standalone boot EEPROM. Microcontroller boot permits reconfigura-
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Microcontroller Boot Configuration Commands
Name NOP WRITE DF REGISTER READ DF REGISTER WRITE FIR COEFFICIENTS WRITE IIR COEFFICIENTS CMD 24-bit 000000 000001 000002 000003 000004 DAT1 24-bit REG REG [DATA] NUM FIR1 (FIR COEF) a11 b11 a22 b21 COEF SEL DAT2 24-bit DATA NUM FIR2 (FIR COEF) b10 a21 b20 b22 Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS NOP NOP FILTER START FILTER STOP
000005 000006 000007 000008 000009
Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation Stop Digital Filter Operation
EEPROM Boot Configuration Commands
Name NOP WRITE DF REGISTER WRITE FIR COEFFICIENTS CMD 8-bit 00 01 02 DATA 24-bit REG DATA NUM FIR1 NUM FIR2 (FIR COEF) a11 b10 b11 a21 a22 b20 b21 b22 COEF SEL No Operation Write Digital Filter Register Write Custom FIR Coefficients Description
WRITE IIR COEFFICIENTS
03
Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS NOP NOP FILTER START
04 05 06 07
Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words of this type are to be written.
Table 1. Microcontroller and EEPROM Configuration Commands
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Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
7:4 FIR2
3:0 FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS
Bits 3:0 0000 0001 Bits 7:4 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase FIR2 Coefficients Linear Phase Minimum Phase
Figure 3. FIR and IIR Coefficient Set Selection Word
Test Bit Stream Characteristic Equation: (Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz
Signal Frequency (TBSDATA) 10.00 Hz 10.00 Hz 25.00 Hz 25.00 Hz 31.25 Hz 31.25 Hz 50.00 Hz 50.00 Hz 125.00 Hz 125.00 Hz
Output Rate (TBSCLK) 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz
Output Rate Selection (RATE) 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5
Interpolation Selection (INTP) 0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table 2. TBS Configurations Using On-Chip Data
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SPI Registers
Name SPICTRL SPICMD SPIDAT1 SPIDAT2 Addr. 00 - 02 03 - 05 06 - 08 09 - 0B Type R/W R/W R/W R/W # Bits 8, 8, 8 8, 8, 8 8, 8, 8 8, 8, 8 SPI Control SPI Command SPI Data 1 SPI Data 2 Description
Digital Filter Registers
Name CONFIG RESERVED GPCFG RESERVED FILTCFG GAIN RESERVED OFFSET RESERVED TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST Addr. 00 01-0D 0E 0F-1F 20 21 22-24 25 26-28 29 2A 2B 2C 2D 2E 2F Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W # Bits 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 Reserved GPIO[7:0] Direction, Pull-up Enable, and Data Reserved Digital Filter Configuration Gain Correction Reserved Offset Correction Reserved Time Break Delay Test Bit Stream Configuration Test Bit Stream Gain User Defined System Register 1 User Defined System Register 2 Hardware Version ID Self-Test Result Code Description Hardware Configuration
Table 3. SPI and Digital Filter Registers
PLL[2:0] 111 110 101 100 011 010 001 000
Mode Selection on Reset 32.768 MHz clock input (PLL bypass). 1.024 MHz clock input. 2.048 MHz clock input. 4.096 MHz clock input. 32.768 MHz clock input (PLL bypass). 1.024 MHz manchester input. 2.048 MHz manchester input. 4.096 MHz manchester input.
BOOT 1 0
Mode Selection on Reset EEPROM boot Microcontroller boot
Configuration Note: States of the PLL[2:0] and BOOT pins are latched immediately after reset to select modes. These pins have a weak (~100 k) pull-up resistor enabled by default. An external 10 k pull-down is required to set a low condition.
Table 4. PLL and BOOT Mode Reset Configurations
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2. CHARACTERISTICS AND SPECIFICATIONS
* * * Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C. GND, GND1, GND2 = 0 V, all voltages with respect to 0 V.
SPECIFIED OPERATING CONDITIONS
Parameter Logic Core Power Supply PLL Power Supply I/O Power Supply Ambient Operating Temperature Industrial (-IQ) Symbol VDDCORE VDDPLL VDDPAD TA Min 2.375 3.135 3.135 -40 Nom 2.5 3.3 3.3 Max 5.25 5.25 5.25 85 Unit V V V C
ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies Symbol Logic Core VDDCORE PLL VDDPLL I/O VDDPAD (Note 1) (Note 1) (Note 1) IIN IIN IOUT PDN VIND TA TSTG Min -0.3 -0.3 -0.3 -0.3 -40 -65 Max 6.0 6.0 6.0 10 50 25 500 VDD+0.3 85 150 Units V V V mA mA mA mW V C C
Input Current, Any Pin Except Supplies Input Current, Power Supplies Output Current Power Dissipation Digital Input Voltages Ambient Operating Temperature (Power Applied) Storage Temperature Range
1. Transient currents up to 100 mA will not cause SCR latch-up.
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THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-Layer PCB) Ambient Operating Temperature (Power Applied) Symbol TJ JA TA Min -40 Typ 50 +85 Max 135 Unit C C / W C
DIGITAL CHARACTERISTICS
Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Drive Voltage Low-Level Output Drive Voltage Rise Times, Digital Inputs Fall Times, Digital Inputs Rise Times, Digital Outputs Fall Times, Digital Outputs Input Leakage Current 3-State Leakage Current Digital Input Capacitance Digital Output Pin Capacitance (Note 2) Iout = -40 A Iout = +40 A Symbol VIH VIL VOH VOL tRISE tFALL tRISE tFALL IIN IOZ CIN COUT Min 0.6 * VDD 0.0 VDD - 0.3 0.0 Typ 1 9 9 Max VDD 0.8 VDD 0.3 100 100 100 100 10 10 Unit V V V V ns ns ns ns A A pF pF
Notes: 2. Maximum leakage for pins with pull-up resistors (RESET, SS:EECS, GPIO, MOSI, SCK) is 250 A.
t rise out t fallo ut
t ris e in
t fa llin
0.90 * VDD 2.6 V 0.10 * VDD 0.7 V
0.90 * VDD 4 .6 V 0.10 * 0 .4 V VDD
POWER CONSUMPTION
Parameter Operational Power Consumption 1.024 MHz Digital Filter Clock 2.048 MHz Digital Filter Clock 4.096 MHz Digital Filter Clock 8.192 MHz Digital Filter Clock Standby Power Consumption 32 kHz Digital Filter Clock, Filter Stopped PWRS 100 W PWR1 PWR2 PWR4 PWR8 12 14 16 24 mW mW mW mW Symbol Min Typ Max Unit
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SWITCHING CHARACTERISTICS
Serial Configuration Interface Timing (External Master)
SSI SS:EECS
MOSI
MSB t1
MSB - 1 t2 t3 t4 t5
LSB t6
SCK SCLK
Figure 4. MOSI Write Timing in SPI Slave Mode
SS I SS:EECS t 10 MISO MSB t7 MSB - 1 t8 t9 LSB
SCK SCLK
Figure 5. MISO Read Timing in SPI Slave Mode
Parameter MOSI Write Timing SS:EECS Enable to Valid Latch Clock Data Set-up Time Prior to SCK Rising Data Hold Time After SCK Rising SCK High Time SCK Low Time SCK Falling Prior to SS:EECS Disable MISO Read Timing SCK Falling to New Data Bit SCK High Time SCK Low Time SS:EECS Rising to MISO Hi-Z
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Min 60 60 120 120 120 60 120 120 -
Typ -
Max 200 150
Unit ns ns ns ns ns ns ns ns ns ns
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CS5378
SWITCHING CHARACTERISTICS
Serial Data Interface Timing
DRDY SCK
t3 t4
MISO
t1 t2 t5
Figure 6. Serial Data Read Timing
Parameter DRDY Falling Edge to SCK Rising SCK Falling to New Data Bit SCK High Time SCK Low Time Final SCK Falling to DRDY Rising
Symbol t1 t2 t3 t4 t5
Min 60 120 120 60
Typ -
Max 120 -
Unit ns ns ns ns ns
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SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, and MDATA
SYNC
MCLK
MSYNC tmsd MDATA
tmsh
tmsd Data1 Data2
Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.
fMCLK 2.048 MHz 1.024 MHz
tmsd = TMCLK / 4 tmsh = TMCLK
tmsd = 122 ns tmsh = 488 ns
tmsd = 244 ns tmsh = 976 ns
Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing
Parameter Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter Synchronization after SYNC rising MSYNC Setup Time to MCLK rising MCLK rising to Valid MDATA MSYNC falling to MCLK rising (Note 4) (Note 3)
Symbol CLK DTY tRISE tFALL JTR SYNC tmss tmdv tmsf
Min 32 40 -2 20 20
Typ 32.768 -
Max 33 60 20 20 300 2 75 -
Unit MHz % ns ns ps s ns ns ns
Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled. 4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.
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SWITCHING CHARACTERISTICS
Test Bit Stream (TBS)
TBSDATA
t1 t2
MCLK
Note: Example timing shown for a 256 kHz output rate and no programmable delays.
Figure 8. TBS Output Data Timing
Parameter TBS Data Output Timing TBS Data Bit Rate TBS Data Rising to MCLK Rising Setup Time MCLK Rising to TBS Data Falling Hold Time (Note 5)
Symbol
Min -
Typ 256 -
Max -
Unit kbps ns ns
t1 t2
60 60
5. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay.
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CS5378
CS5371
System Telemetry
Geophone or Hydrophone Sensor
M U X
CS3301 CS3302 AMP
Modulator CS5378 Digital Filter w/ PLL
Controller or Configuration EEPROM
CS4373 Communication Interface Test DAC
Figure 9. Single-Channel System Block Diagram
3. SYSTEM DESIGN WITH CS5378
Figure 9 illustrates a simplified block diagram of the CS5378 in a single channel measurement system. A differential sensor is connected through the CS3301/02 differential amplifiers to the CS5371 modulator, where analog to digital conversion occurs. The modulator's 1-bit output connects to the CS5378 MDATA input, where the oversampled data is decimated and filtered to 24-bit output samples at a programmed output rate. These output samples are buffered into an 8-deep data FIFO and then passed to the system telemetry. System self tests are performed by connecting the CS5378 test bit stream (TBS) generator to the CS4373 test DAC. Analog tests drive differential signals from the CS4373 test DAC into the multiplexed inputs of the CS3301/02 amplifiers or directly to the differential sensor. Digital loopback tests internally connect the TBS digital output directly to the CS5378 modulator input.
3.1 Power Supplies
The system shown in Figure 9 typically operates from a 2.5 V or a 5 V analog power supply and a 3.3 V digital power supply. The CS5378 logic core can be powered from 2.5 V to minimize power consumption, if required.
3.2 Reset Control
System reset is required only for the CS5378 device, and is a standard active low signal that can be generated by a power supply monitor or microcontroller. Other system devices default to a powerdown state when the CS5378 is reset.
3.3 PLL and Clock Generation
A PLL is included on the CS5378 to generate an internal 32.768 MHz master clock from a 1.024 MHz, 2.048 MHz, or 4.096 MHz standard clock or manchester encoded input. Clock inputs for other system devices are driven by clock outputs from the CS5378.
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3.4 Synchronization
Digital filter phase and analog sample timing of the modulator connected to the CS5378 are synchronized by a rising edge on the SYNC pin. If a synchronization signal is received identically by all CS5378 devices in a measurement network, synchronous sampling across the network is guaranteed.
3.7 Data Collection
Data is collected from the CS5378 through the serial data interface. When data is available, serial transactions are automatically initiated to transfer 24-bit data or 32-bit status+data from the output FIFO to the system telemetry. The output FIFO has eight data locations to permit latency in data collection.
3.5 System Configuration
Through the serial configuration interface, filter coefficients and digital filter register settings can either be programmed by a microcontroller or automatically loaded from an external EEPROM after reset. System configuration is only required for the CS5378 device, as other devices are configured via the CS5378 General Purpose I/O pins. Two registers in the digital filter, SYSTEM1 and SYSTEM2 (0x2C, 0x2D), are provided for user defined system information. These are general purpose registers that will hold any 24-bit data values written to them.
3.8 Integrated peripherals Test Bit Stream (TBS)
A digital signal generator built into the CS5378 produces a 1-bit sine wave or impulse function. This digital test bit stream is connected to the CS4373 test DAC to create high quality analog test signals or internally looped back to the CS5378 MDATA input to test the digital filter and data collection circuitry.
Time Break
Timing information is recorded during data collection by strobing the TIMEB pin. A dedicated flag in the sample status bits, TB, is set high to indicate during which measurement the timing event occurred.
3.6 Digital Filter Operation
After analog to digital conversion occurs in the modulator, the oversampled 1-bit data is read into the CS5378 through the MDATA pin. The digital filter then processes data through the enabled filter stages, decimating it to 24-bit words at a programmed output word rate. The final 24-bit samples are concatenated with 8-bit status words and placed into an output FIFO.
General Purpose I/O (GPIO)
Eight general purpose pins are available on the CS5378 for system control. Each pin can be set as input or output, high or low, with an internal pullup enabled or disabled. The CS3301/02, CS5371 and CS4373 devices in Figure 9 are configured by simple pin settings controlled through the CS5378 GPIO pins.
DS639F1
19
CS5378
1 2 3 4 5 6 7 8
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDPAD GNDPAD
GNDCORE VDDCORE
9 10 11 12 13 14
GNDPLL VDDPLL
Figure 10. Power Supply Block Diagram
4. POWER SUPPLIES
The CS5378 has three sets of power supply inputs. One set supplies power to the I/O pins of the device (VDDPAD), another supplies power to the logic core (VDDCORE) and the third supplies power to the PLL (VDDPLL). The I/O pin power supplies determine the maximum input and output voltages when interfacing to peripherals, the logic core power supply largely determines the power consumption of the CS5378 and the PLL power supply powers the internal PLL circuitry.
VDDCORE, GNDCORE - Pins 21, 22
Sets the operational voltage of the CS5378 logic core. VDDCORE can be driven with voltages from 2.5 V to 5 V. A 2.5 V supply will minimize total power consumption.
4.2 Bypass Capacitors
Each power supply pin should be bypassed with parallel 1 F and 0.01 F caps, or by a single 0.1 F cap, placed as close as possible to the CS5378. Bypass capacitors should be ceramic (X7R, C0G), tantalum, or other good quality dielectric type.
4.1 Pin Descriptions VDDPAD, GNDPAD - Pins 9, 10
Sets the interface voltage to a microcontroller, system telemetry, modulator, and test DAC. VDDPAD can be driven with voltages from 3.3 V to 5 V.
4.3 Power Consumption
Power consumption of the CS5378 depends primarily on the power supply voltage of the logic core (VDDCORE) and the programmed digital filter clock rate. Digital filter clock rates are selected based on the required output word rate as explained in "Digital Filter Initialization" on page 38.
VDDPLL, GNDPLL - Pins 15, 16
Sets the operational voltage of the internal CS5378 PLL circuitry. Can be driven with voltages from 3.3 V to 5 V.
DS639F1
20
CS5378
RESET
Self-Tests
BOOT Pin 1
0
SELFTEST Register
EEPROM Boot
Controller Boot
Figure 11. Reset Control Block Diagram
5. RESET CONTROL
The CS5378 reset signal is active low. When released, a series of self-tests are performed and the device either actively boots from an external EEPROM or enters an idle state waiting for microcontroller configuration. combined into the SELFTEST register (0x2F), with 0x0AAAAA indicating all passed. Self-tests require 60 ms to complete.
5.3 Boot Configurations
The logic state of the BOOT pin after reset determines if the CS5378 actively reads configuration information from EEPROM or enters an idle state waiting for a microcontroller to write configuration commands.
5.1 Pin Descriptions RESET - Pin 18
Reset input, active low.
GPIO7:BOOT - Pin 28
Boot mode select, latched immediately following reset. Weak (~100 k) internal pull-up defaults high, external 10 k pull-down required to set low.
BOOT 1 0 Reset Mode EEPROM boot Microcontroller boot
EEPROM Boot
When the BOOT pin is high after reset, the CS5378 actively reads data from an external serial EEPROM and then begins operation in the specified configuration. Configuration commands and data are encoded in the EEPROM as specified in the `Configuration By EEPROM' section of this data sheet, starting on page 25.
5.2 Reset Self-Tests
After RESET is released but before booting, a series of digital filter self-tests are run. Results are
Self-Test Type Program ROM Data ROM Program RAM Data RAM Execution Unit DS639F1 Pass Code 0x00000A 0x0000A0 0x000A00 0x00A000 0x0A0000 Fail Code 0x00000F 0x0000F0 0x000F00 0x00F000 0x0F0000
Microcontroller Boot
When the BOOT pin is low after reset, the CS5378 enters an idle state waiting for a microcontroller to write configuration commands and initialize filter operation. Configuration commands and data are written as specified in the `Configuration By Microcontroller' section of this data sheet, starting on page 30.
21
CS5378
CLK PLL PLL[2:0]
32.768 MHz
Clock Divider and MCLK Generator
Internal Clocks MCLK Output
DSPCFG Register Figure 12. Clock Generation Block Diagram
6. PLL AND CLOCK GENERATION
The CS5378 requires a 32.768 MHz master clock, which can be supplied directly or from an internal phase locked loop. This master clock is used to generate an internal digital filter clock and an external modulator clock. The internal PLL will lock to standard clock or manchester encoded input signals. The input type and input frequency are selected by the reset state of the PLL mode select pins. A weak internal pull-up resistor (~100 k) will hold the PLL mode select pins high by default. To force the pin low on reset, an external 10 k pulldown resistor should be connected. Once the pin state is latched following reset, the GPIO[4:6] pins funtion without affecting PLL operation.
6.3 Synchronous Clocking
To guarantee synchronous measurements throughout a sensor network, a system clock should be distributed to arrive at all nodes in phase. The distributed system clock can either be the full 32.768 MHz master clock, or the CS5378 PLL can create a synchronous 32.768 MHz clock from a slower clock. To ensure the generated clock remains synchronous with the network, the CS5378 PLL uses a phase/frequency detector architecture.
PLL[2:0]
111 110 101 100 011 010 001 000
6.1 Pin Descriptions CLK - Pin 17
Clock or PLL input, standard clock or manchester.
GPIO[4:6]:PLL[0:2] - Pins 5, 6, 7
PLL mode select, latched immediately after reset. Weak (~100 k) internal pull-ups default high, external 10 k pull-downs required to set low.
PLL Mode
32.768 MHz clock input (PLL bypass). 1.024 MHz clock input. 2.048 MHz clock input. 4.096 MHz clock input. 32.768 MHz clock input (PLL bypass). 1.024 MHz manchester input. 2.048 MHz manchester input. 4.096 MHz manchester input.
6.2 PLL Mode Select
The CS5378 PLL operational mode and frequency are selected immediately after reset based on the state of the PLL[0:2] pins. On the rising edge of the reset signal, the digital high or low state of the PLL[0:2] pins is latched and used to program the clock input type and frequency.
Table 5. PLL Mode Selections
DS639F1
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CS5378
6.4 Master Clock Jitter and Skew
Care must be taken to minimize jitter and skew on the distributed system clock as both parameters affect measurement performance. Jitter on the input clock causes jitter in the generated modulator clock, resulting in sample timing errors and increased noise. Skew between input clocks from node to node creates a sample timing offset, resulting in systematic measurement errors in a reconstructed signal.
DS639F1
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CS5378
0 SYNC 1 MSYNC Generator
Digital Filter
0 1 Test Bit Stream
MSEN
MSYNC Output
TSYNC
Figure 13. Synchronization Block Diagram
7. SYNCHRONIZATION
The CS5378 has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator analog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5378 devices, synchronous sampling across a network can be guaranteed. phase. Filter convolutions restart, and the next output word is available one full sample period later. Repetitive synchronization is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization will occur at the start of a convolution cycle when the digital filter state machine is already reset.
7.1 Pin Description SYNC - Pin 19
Synchronization input, rising edge triggered.
7.4
Modulator Synchronization
7.2 MSYNC Generation
The SYNC signal rising edge is used to generate a retimed synchronization signal, MSYNC. The MSYNC signal reinitializes internal digital filter phase and is driven onto the MSYNC output pin to phase align modulator analog sampling. The MSEN bit in the digital filter CONFIG register (0x00) enables MSYNC generation. See "Modulator Interface" on page 36 for more information about MSYNC.
The external MSYNC signal phase aligns modulator analog sampling when connected to the CS5371 MSYNC input. This ensures synchronous analog sampling relative to MCLK. Repetitive synchronization of the modulators is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization always occurs at the start of analog sampling.
7.5 Test Bit Stream Synchronization
When the test bit stream generator is enabled, an MSYNC signal can reset the internal data pointer. This restarts the test bit stream from the first data point to establish a known output signal phase. The TSYNC bit in the digital filter TBSCFG register (0x2A) enables synchronization of the test bit stream by MSYNC. When TSYNC is disabled, the test bit stream phase is not affected by MSYNC.
24
7.3 Digital Filter Synchronization
The internal MSYNC signal resets the digital filter state machine to establish a known digital filter
DS639F1
CS5378
VD 3 8 7 WP VCC HOLD
SS:EECS SCK
27 24 25 26
1 6 2 5
CS SCK
CS5378
MISO MOSI
AT25640
SO SI 4 GND
Figure 14. EEPROM Configuration Block Diagram
8. CONFIGURATION BY EEPROM
After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is high, the CS5378 initiates serial transactions to read configuration information from an external EEPROM. to read configuration commands and data. 8-bit SPI opcodes and 16-bit addresses are combined to read back 8-bit configuration commands and 24-bit configuration data. System design should include a connection to the configuration EEPROM for in-circuit reprogramming. The CS5378 serial pins tri-state when inactive to support external connections to the serial bus.
8.1 Pin Descriptions
Pins required for EEPROM boot are listed here, other serial pins are inactive.
SCK - Pin 24
Serial clock output, nominally 1.024 MHz.
8.3 EEPROM Organization
The boot EEPROM holds the 8-bit commands and 24-bit data required to initialize the CS5378 into an operational state. Configuration information starts at memory location 0x10, with addresses 0x00 to 0x0F free for use as manufacturing header information. The first serial transaction reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. Command and data reads continue until the `Filter Start' command is recognized.
MISO - Pin 25
Serial data input pin. Valid on rising edge of SCK, transition on falling edge.
MOSI - Pin 26
Serial data output pin. Valid on rising edge of SCK, transition on falling edge.
SS:EECS - Pin 27
EEPROM chip select output, active low.
8.2 EEPROM Hardware Interface
When booting from EEPROM the CS5378 actively performs serial transactions, as shown in Figure 15,
DS639F1
25
CS5378
Instruction Read 0x03
Opcode
Address ADDR[15:0]
Definition Read data beginning at the address given in ADDR.
Serial Read from EEPROM
READ CMD MOSI 0x03 2 BYTE ADDR ADDR ADDR
MISO
DATA1 DATA2 DATA3 1 BYTE / 3 BYTE DATA
SS:EECS
Cycle
1
2
3
4
5
6
7
8
SCK
MOSI
MSB
6
5
4
3
2
1
LSB
MISO
MSB
6
5
4
3
2
1
LSB
X
SS:EECS
Figure 15. EEPROM Serial Read Transactions
DS639F1
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CS5378
Write DF Register - 0x01
0000h 0010h Mfg Header 8-bit Command N x 24-bit Data 8-bit Command N x 24-bit Data 1FFFh ... EEPROM Manufacturing Information EEPROM Command and Data Values This EEPROM command writes a data value to the specified digital filter register. Digital filter registers control hardware peripherals and filtering functions. See "Digital Filter Registers" on page 71 for the bit definitions of the digital filter registers.
Sample Command:
Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240. 01 00 00 00 06 04 31 01 00 00 20 00 02 40
Figure 16. 8 Kbyte EEPROM Memory Organization
Write FIR Coefficients - 0x02
The maximum number of bytes that will be written for a single configuration is less than 2 KByte (16 Kbit), including command overhead: This EEPROM command writes custom coefficients for the FIR1 and FIR2 filters. The first two data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are the concatenated FIR1 and FIR2 coefficients. A maximum of 255 coefficients can be written for each FIR filter, though the available digital filter computation cycles will limit their practical size. See "FIR Filter" on page 44 for more information about FIR filter coefficients.
Memory Requirement
Bytes
Digital Filter Registers (12) FIR Coefficients (255+255) IIR Coefficients (3+5) `Filter Start' Command Total Bytes
84 1537 25 1 1647
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
Table 6. Maximum EEPROM Configuration
02 00 00 02 00 00 02 00 02 2E 00 07 71 FF FF B9 FF FE 8D
Supported serial configuration EEPROMs are SPI mode 0 (0,0) compatible, 16-bit addresses, 8bit data, larger than 2 KByte (16 KBit). ATMEL AT25640, AT25128, or similar serial EEPROMs are recommended.
Write IIR Coefficients - 0x03
This EEPROM command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight data words containing coefficient values always immediately follow the command byte. The IIR coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See "IIR Filter" on page 52 for more information about IIR filter coefficients.
8.4 EEPROM Configuration Commands
A summary of available EEPROM commands is shown in Table 7.
DS639F1
27
CS5378
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, and IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. 03 84 BC 9D 7D A1 B1 82 5E 4F 83 69 4F 3C AD 5F 3E 51 04 83 5D F8 3E 51 04
Sample Command:
Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200. 04 00 22 00
Filter Start - 0x07
This EEPROM command initializes and starts the digital filter. Measurement data becomes available one full sample period after this command is issued. No data words are required for this EEPROM command.
Write ROM Coefficients - 0x04
This EEPROM command selects the on-chip coefficients for the FIR1, FIR2, IIR 1st order, and IIR 2nd order filters for use by the digital filter. One data word is required to select which internal coefficient sets to use. See "Filter Coefficient Selection" on page 38 for information about selecting on-chip FIR and IIR coefficient sets.
Sample Command:
07
Name NOP WRITE DF REGISTER WRITE FIR COEFFICIENTS
CMD 8-bit 00 01 02
DATA 24-bit REG DATA NUM FIR1 NUM FIR2 (FIR COEF) a11 b10 b11 a21 a22 b20 b21 b22 COEF SEL No Operation
Description
Write Digital Filter Register Write Custom FIR Coefficients
WRITE IIR COEFFICIENTS
03
Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS NOP NOP FILTER START
04 05 06 07
Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation
(DATA) indicates multiple words of this type are to be written.
Table 7. EEPROM Boot Configuration Commands
DS639F1
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CS5378
8.5 Example EEPROM Configuration
Table 8 shows an example EEPROM file for a minimal CS5378 configuration.
Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Data 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 22 00 01 00 00 00 06 04 31 01 00 00 20 00
Description Mfg header
Addr 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
Data 02 40 01 00 00 2A 07 40 40 01 00 00 2B 04 B0 00 07
Description
Write TBSCFG Register
Write TBSGAIN Register
Write ROM Coefficients
31
Filter Start
Write CONFIG Register
Write FILTCFG Register
Table 8. Example EEPROM File
DS639F1
29
CS5378
Digital Filter Command Interpreter
SPI Registers
Serial Pin Logic
SS:EECS SCK MOSI MISO
Figure 17. Serial Interface Block Diagram
9. CONFIGURATION BY MICROCONTROLLER
After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is low, the CS5378 receives configuration commands from a microcontroller.
9.2 Microcontroller Hardware Interface
When booting from a microcontroller the CS5378 receives configuration commands and configuration data through serial transactions, as shown in Figure 18. 8-bit SPI opcodes and 8-bit addresses are combined to read and write 24-bit configuration commands and data. Microcontroller serial transactions require toggling the SS:EECS pin as the CS5378 chip select and writing a serial clock to the SCK input. Serial data is input to the CS5378 on the MOSI pin, and output on the MISO pin.
9.1 Pin Descriptions
Pins required for microcontroller boot are listed here, other serial pins are inactive.
SS:EECS - Pin 27
Slave select input pin, active low. Serial chip select input from a microcontroller.
MOSI - Pin 26
Serial data input pin. Valid on rising edge of SCK, transition on falling edge.
9.3 Microcontroller Serial Transactions
Microcontroller configuration commands are written to the digital filter through SPI registers. A 24bit command and two 24-bit data words can be written to the SPI registers in any single serial transaction. Some commands require additional data words through additional serial transactions to complete. 9.3.1 SPI opcodes A microcontroller communicates with the CS5378 serial port using standard 8-bit SPI opcodes and an 8-bit address. The standard SPI `Read' and `Write' opcodes are listed in Figure 18.
MISO - Pin 25
Serial data output pin. Valid on rising edge of SCK, transition on falling edge. Open drain output requiring a 10 k pull-up resistor.
SCK - Pin 24
Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz.
DS639F1
30
CS5378
Instruction Write Read
Opcode 0x02 0x03
Address ADDR[7:0] ADDR[7:0]
Definition Write SPI registers beginning at the address in ADDR. Read SPI registers beginning at the address in ADDR.
Microcontroller Write to SPI Registers
SS:EECS
MISO
0x02
ADDR
Data1
Data2
DataN
MOSI
Microcontroller Read from SPI Registers
SS:EECS
MISO
0x03
ADDR
MOSI
Data1
Data2
DataN
Cycle
1
2
3
4
5
6
7
8
SCK
MOSI
MSB
6
5
4
3
2
1
LSB
MISO
MSB
6
5
4
3
2
1
LSB
X
SS:EECS
Figure 18. Microcontroller Serial Transactions DS639F1 31
CS5378
9.3.2 SPI registers The SPI registers are shown in Figure 19 and are 24-bit registers mapped into an 8-bit register space as high, mid, and low bytes. See "SPI Registers" on page 66 for the bit definitions of the SPI registers. 9.3.3 Serial transactions A serial transaction to the SPI registers starts with an SPI opcode, followed by an address, and then some number of data bytes written or read starting at that address. Typical serial write transactions require sending groups of 5, 8, or 11 total bytes to the SPICMD or SPIDAT1 registers: 5-byte write to SPICMD 02 03 12 34 56 5-byte write to SPIDAT1 02 06 12 34 56 8-byte write to SPICMD, SPIDAT1 02 03 12 34 56 AB CD EF 8-byte write to SPIDAT1, SPIDAT2 02 06 12 34 56 AB CD EF 11-byte write to SPICMD, SPIDAT1, SPIDAT2 02 03 12 34 56 AB CD EF 65 43 21 Typical serial read transactions require groups of 3 or 5 bytes, split between writing into MOSI and reading from MISO. 3-byte read of mid-byte of SPICTRL 9.3.5 Polling E2DREQ One transaction type that can always be performed no matter the delay from the previous configuration command is reading E2DREQ in the mid-byte of the SPICTRL register. A 3-byte read transaction. MOSI: 03 01 00 MISO: xx xx 01 <- E2DREQ bit high MISO: xx xx 00 <- E2DREQ bit low The E2DREQ bit reads high while a serial transaction is being processed. When low, the digital filter is ready to receive a new serial transaction. MOSI: 03 01 00 MISO: xx xx 12 5-byte read of SPIDAT1 MOSI: 03 06 00 00 00 MISO: xx xx 12 34 56 9.3.4 Multiple serial transactions Some configuration commands require multiple serial transactions to complete. There must be a small delay between transactions for the CS5378 to process the incoming data. Two methods can be used to ensure the CS5378 is ready to receive the next configuration command. 1) Delay a fixed 1 ms period to guarantee enough time for the command to be completed. 2) Verify the status of the E2DREQ bit by reading the SPICTRL register. When low, the CS5378 is ready for the next command.
Name SPICTRL SPICMD SPIDAT1 SPIDAT2
Addr. 00 - 02 03 - 05 06 - 08 09 - 0B
Type R/W R/W R/W R/W
# Bits 8, 8, 8 8, 8, 8 8, 8, 8 8, 8, 8 SPI Control SPI Command SPI Data 1 SPI Data 2
Description
Figure 19. SPI Registers DS639F1 32
CS5378
9.4 Microcontroller Configuration Commands
A summary of available microcontroller configuration commands is listed in Table 9.
Read DF Register - 0x02
This command reads a specified digital filter register. The register value is requested in the first serial transaction, with the register value copied to SPIDAT1 and read in a subsequent serial transaction.
Write DF Register - 0x01
This configuration command writes a specified digital filter register. Digital filter registers control hardware peripherals and filtering functions. See "Digital Filter Registers" on page 71 for the bit definitions of the digital filter registers.
Sample Command:
Read digital filter registers 0x00 and 0x20. 02 03 00 00 02 00 00 00 Delay 1 ms or poll E2DREQ MOSI: 03 06 00 00 00 MISO: xx xx 06 04 31 02 03 00 00 02 00 00 20 Delay 1 ms or poll E2DREQ MOSI: 03 06 00 00 00 MISO: xx xx 00 02 40
Sample Command:
Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240. 02 03 00 00 01 00 00 00 06 04 31 Delay 1 ms or poll E2DREQ 02 03 00 00 01 00 00 20 00 02 40 Delay 1 ms or poll E2DREQ
Name NOP WRITE DF REGISTER READ DF REGISTER WRITE FIR COEFFICIENTS WRITE IIR COEFFICIENTS
CMD 24-bit 000000 000001 000002 000003 000004
DAT1 24-bit REG REG [DATA] NUM FIR1 (FIR COEF) a11 b11 a22 b21 COEF SEL -
DAT2 24-bit DATA NUM FIR2 (FIR COEF) b10 a21 b20 b22 -
Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS NOP NOP FILTER START FILTER STOP
000005 000006 000007 000008 000009
Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation Stop Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words of this type are to be written.
Table 9. Microcontroller Boot Configuration Commands
DS639F1
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CS5378
Write FIR Coefficients - 0x03
This command writes custom coefficients for the FIR1 and FIR2 filters. The first two data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are the concatenated FIR1 and FIR2 coefficients. A maximum of 255 coefficients can be written for each FIR filter, though the available digital filter computation cycles will limit their practical size. See "FIR Filter" on page 44 for more information about FIR filter coefficients. 02 06 3C AD 5F 3E 51 04 Delay 1 ms or poll E2DREQ 02 06 83 5D F8 3E 51 04 Delay 1 ms or poll E2DREQ
Write ROM Coefficients - 0x05
This configuration command selects the on-chip coefficients for FIR1, FIR2, IIR 1st order, and IIR 2nd order filters for use by the digital filter. One data word is required to select which internal coefficient sets to use. See "Filter Coefficient Selection" on page 38 for information about selecting on-chip FIR and IIR coefficient sets.
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D. 02 03 00 00 03 00 00 02 00 00 02 Delay 1 ms or poll E2DREQ 02 06 00 02 2E 00 07 71 Delay 1 ms or poll E2DREQ 02 06 FF FF B9 FF FE 8D Delay 1 ms or poll E2DREQ
Sample Command:
Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200. 02 03 00 00 05 00 22 00 Delay 1 ms or poll E2DREQ
Filter Start - 0x08
This command initializes and starts the digital filter. Measurement data becomes available one full sample period after this command is issued. No data words are required for this command.
Write IIR Coefficients - 0x04
This command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight coefficient values immediately follow this command. The IIR coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See "IIR Filter" on page 52 for more information about IIR filter coefficients.
Sample Command:
02 03 00 00 08 Delay 1 ms or poll E2DREQ
Filter Stop - 0x09
This command disables the digital filter. Measurement data output stops immediately after this command is issued. No data words are required for this command.
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, and IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. 02 03 00 00 04 84 BC 9D 7D A1 B1 Delay 1 ms or poll E2DREQ 02 06 82 5E 4F 83 69 4F Delay 1 ms or poll E2DREQ
DS639F1
Sample Command:
02 03 00 00 09 Delay 1 ms or poll E2DREQ
34
CS5378
9.5 Example Microcontroller Configuration
Table 10 shows an example microcontroller transactions for a minimal CS5378 configuration.
Transaction 01 02 03 04 05 06 07 08 09 10 11
SPI Data 02 03 00 00 05 00 22 00 Delay 1ms or poll E2DREQ 02 03 00 00 01 00 00 00 06 04 31 Delay 1ms or poll E2DREQ 02 03 00 00 01 00 00 20 00 02 40 Delay 1ms or poll E2DREQ 02 03 00 00 01 00 00 2A 07 40 40 Delay 1ms or poll E2DREQ 02 03 00 00 01 00 00 2B 04 B0 00 Delay 1ms or poll E2DREQ 02 03 00 00 08
Description Write ROM coefficients Write CONFIG Register Write FILTCFG Register Write TBSCFG Register Write TBSGAIN Register Filter Start
Table 10. Example Microcontroller Configuration
DS639F1
35
CS5378
MCLK MSYNC MDATA MFLAG
MCLK / MSYNC Generate MDI Input 512 kHz
CLK SYNC
SINC Filter
FIR Filters
IIR Filter
DC Offset & Gain Correction
Output to High Speed Serial Interface Output Rate 4000 SPS ~ 1 SPS
Figure 20. Modulator Data Interface
10. MODULATOR INTERFACE
The CS5378 performs digital filtering for a type modulator. Signals from the modulators are connected through the modulator data interface (MDI).
10.2 Modulator Clock Generation
The MCLK output is a low-jitter, low-skew modulator clock generated from the 32.768 MHz master clock. MCLK typically operates at 2.048 MHz unless analog low-power modes require a 1.024 MHz modulator clock. The MCLK rate is selected and the MCLK output is enabled by bits in the digital filter CONFIG register (0x00). By default MCLK is disabled and driven low.
10.1 Pin Descriptions MCLK - Pin 11
Modulator clock output. Nominally 2.048 MHz or 1.024 MHz.
MSYNC - Pin 12
Modulator synchronization signal output. Generated from the SYNC input.
10.3 Modulator Synchronization
The MSYNC output signal follows an input to the SYNC pin. MSYNC phase aligns the modulator sampling instant to guarantee synchronous analog sampling across a measurement network. MSYNC is enabled by a bit in the CONFIG register (0x00). By default SYNC inputs do not cause an MSYNC output.
MDATA - Pin 13
Modulator data input, nominally 512 kbit/s.
MFLAG - Pin 14
Modulator flag input. Driven high when the modulator is unstable due to an analog over-range condition.
DS639F1
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CS5378
10.4 Modulator Data Input
The MDATA input expects 1-bit data at a 512 kHz or 256 kHz rate. The input rate is selected by a bit in the CONFIG register (0x00). By default, MDATA is expected at 512 kHz. The MDATA input one's density is designed for full scale positive at 86% and full scale negative at 14%, with absolute maximum over-range capability to 93% and 7%. These raw inputs are decimated and filtered by the digital filter to create 24bit samples at the output rate.
10.5 Modulator Flag Input
A high MFLAG input signal indicates the modulator has become unstable due to an analog overrange input signal. Once the over-range signal is reduced, the modulator recovers stability and the MFLAG signal is cleared. The MFLAG input is mapped to a status bit in the serial data output stream, and is associated with each sample when written. See "Serial Data Interface" on page 58 for more information on the MFLAG error bit in the serial data status byte.
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Modulator Input 512 kHz
SINC Filter 2 - 64000
FIR1 4
FIR2 2
IIR1 1st Order
IIR2 2nd Order
DC Offset & Gain Correction
Output to High Speed Serial Data Interface Output Rate 4000 SPS ~ 1 SPS
Figure 21. Digital Filter Stages
11. DIGITAL FILTER INITIALIZATION
The CS5378 digital filter consists of three multistage sections: a three stage SINC filter, a two stage FIR filter, and a two stage IIR filter. To initialize the digital filter, FIR and IIR coefficient sets are selected using configuration commands, and the FILTCFG register (0x20) is written to select the output filter stage, the output word rate, and the number of enabled channels. The digital filter clock rate is then selected by writing the CONFIG register (0x00). word, and the available coefficient sets for each selection. Characteristics of the on-chip digital filter coefficients are discussed in the `SINC Filter', `FIR Filter', and `IIR Filter' sections of this data sheet.
11.2 Filter Configuration Options
Digital filter parameters are selected by bits in the FILTCFG register (0x20), and the digital filter clock rate is selected by bits in the CONFIG register (0x00). 11.2.1 Output Filter Stage The digital filter can output data following any stage in the filter chain. The output filter stage is selected by the FSEL bits in the FILTCFG register. Taking data from the SINC or FIR1 filter stages reduces the overall decimation of the filter chain and increases the output rate, as discussed in the next section. Taking data from FIR2, IIR1, IIR2, or IIR3 results in data at the selected rate.
11.1 Filter Coefficient Selection
Selection of SINC filter coefficients is not required as they are selected automatically based on the programmed output word rate. Digital filter FIR and IIR coefficients are selected using the `Write FIR Coefficients' and `Write IIR Coefficients', or the `Write ROM Coefficients' configuration commands. When writing the FIR and IIR coefficients from ROM, a data word selects an on-chip coefficient set for each filter stage. Figure 22 shows the format of the coefficient selection
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Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
7:4 FIR2
3:0 FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 3 Hz @ 2000 SPS 3 Hz @ 1000 SPS 3 Hz @ 500 SPS 3 Hz @ 333 SPS 3 Hz @ 250 SPS
Bits 3:0 0000 0001 Bits 7:4 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase FIR2 Coefficients Linear Phase Minimum Phase
Figure 22. FIR and IIR Coefficient Set Selection Word
11.2.2 Output Word Rate The CS5378 digital filter supports output word rates (OWRs) between 4000 SPS and 1 SPS. The output word rate is selected by the DEC bits in the FILTCFG register. When taking data directly from the SINC filter, the decimation of the FIR1 and FIR2 stages is bypassed and the actual output word rate is multiplied by a factor of eight compared with the register selection. When taking data directly from FIR1, the decimation of the FIR2 stage is bypassed and the actual output word rate is multiplied by a factor of two. Data taken from the FIR2, IIR1, IIR2, or IIR3 filtering stages is output at the selected rate. 11.2.3 Digital Filter Clock The digital filter clock rate is programmable between 8.192 MHz and 32 kHz by bits in the CONFIG register.
Computation Cycles
The minimum digital filter clock rate for a configuration depends on the computation cycles required to complete digital filter convolutions at the selected output word rate. All configurations work for a maximum digital filter clock, but lower clock rates consume less power.
Standby Mode
The CS5378 can be placed in a low-power standby mode by sending the `Filter Stop' configuration command and programming the digital filter clock to 32 kHz. In this mode the digital filter idles, consuming minimal power until re-enabled by later configuration commands.
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1-bit - Input
5th order sinc1 8
4th order sinc2 stage1 2
4th order sinc2 stage2 2
5th order sinc2 stage3 2
6th order sinc2 stage4 2
4th order sinc3 stage1 5
4th order sinc3 stage2 5
4th order sinc3 stage3 5
5th order sinc3 stage4 5
5th order sinc3 stage5 2
6th order sinc3 stage6 3
6th order sinc3 stage7 2
24-bit Output
Figure 23. SINC Filter Block Diagram
12. SINC FILTER
The SINC filter primary purpose is to attenuate outof-band noise components from the modulators. While doing so, they decimate 1-bit data into lower frequency 24-bit data suitable for the FIR and IIR filters. The SINC filter has three cascaded sections, SINC1, SINC2, and SINC3, which are each made up of the smaller stages shown in Figure 23. The selected output word rate in the FILTCFG register automatically determines the coefficients and decimation ratios selected for the SINC filters.
12.2 SINC2 Filter
The second section is SINC2, a multi-stage, variable order, variable decimation SINC filter. Depending on the selected output word rate in the FILTCFG register, different cascaded SINC2 stages are enabled, as shown in Table 11.
12.3 SINC3 Filter
The last section is SINC3, a flexible multi-stage variable order, variable decimation SINC filter. Depending on the selected output word rate in the FILTCFG register, different SINC3 stages are enabled, as shown in Table 11.
12.1 SINC1 Filter
The first section is SINC1, a single stage 5th order fixed decimate by 8 SINC filter. This SINC filter decimates the incoming 1-bit bit stream from the modulators down to a 64 kHz rate.
12.4 SINC Filter Synchronization
The SINC filter is synchronized to the external system by the MSYNC signal, which is generated from the SYNC input. The MSYNC signal sets a reference time (time 0) for all filter operations, and the SINC filter is restarted to phase align with this reference time.
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SINC1 - Single stage, fixed decimate by 8 5th order decimate by 8, 36 coefficients SINC2 - Multi-stage, variable decimation Stage Stage Stage Stage 1: 2: 3: 4: 4th 4th 5th 6th order order order order decimate decimate decimate decimate by by by by 2, 2, 2, 2, 5 5 6 7 coefficients coefficients coefficients coefficients
SINC3 - Multi-stage, variable decimation Stage Stage Stage Stage Stage Stage Stage 1: 2: 3: 4: 5: 6: 7: 4th 4th 4th 5th 5th 6th 6th order order order order order order order decimate decimate decimate decimate decimate decimate decimate by by by by by by by 5, 5, 5, 5, 2, 3, 2, 17 17 17 21 6 13 7 coefficients coefficients coefficients coefficients coefficients coefficients coefficients
Figure 24. SINC Filter Stages
SINC filters
FIR2 Output Word Rate 4000 2000 1000 500 333 250 200 125 100 50 40 25 20 10 5 1 DEC Bit Setting SINC1 Decimation 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 SINC2 Decimation 2 4 8 16 8 16 4 16 4 8 4 16 4 8 16 16 SINC2 Stages SINC3 Decimation 3 2 10 4 20 20 50 20 100 100 100 500 SINC3 Stages
0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
4 3,4 2,3,4 1,2,3,4 2,3,4 1,2,3,4 3,4 1,2,3,4 3,4 2,3,4 3,4 1,2,3,4 3,4 2,3,4 1,2,3,4 1,2,3,4
6 7 4,7 5,7 3,5,7 3,5,7 3,4,7 3,5,7 2,3,5,7 2,3,5,7 2,3,5,7 1,2,3,5,7
Table 11. SINC Filter Configurations
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Filter Type SINC1 5th order decimate by 8 36 coefficients
System Function
Filter Coefficients h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 = = = = = = = = = = = = = = = = = = 1 5 15 35 70 126 210 330 490 690 926 1190 1470 1750 2010 2226 2380 2460 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 = = = = = = = = = = = = = = = = = = 2460 2380 2226 2010 1750 1470 1190 926 690 490 330 210 126 70 35 15 5 1
1 - z -8 H ( z) = 1 - z -1
5
Filter Type SINC2 (Stage 1) SINC2 (Stage 2) 4th order decimate by 2 5 coefficients
System Function
Filter Coefficients h0 h1 h2 h3 h4 h0 h1 h2 h3 h4 h5 h0 h1 h2 h3 h4 h5 h6 = = = = = = = = = = = = = = = = = = 1 4 6 4 1 1 5 10 10 5 1 1 6 15 20 15 6 1
1 - z -2 H ( z) = 1 - z -1
4
SINC2 (Stage 3) 5th order decimate by 2 6 coefficients
1 - z -2 H ( z) = 1 - z -1
5
SINC2 (Stage 4) 6th order decimate by 2 7 coefficients
1 - z -2 H ( z) = 1 - z -1
6
Table 12. SINC1 and SINC2 Filter Coefficients
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Filter Type SINC3 (Stage 1) SINC3 (Stage 2) SINC3 (Stage 3) 4th order decimate by 5 17 coefficients
System Function
Filter Coefficients h0 h1 h2 h3 h4 h5 h6 h7 h8 = = = = = = = = = 1 4 10 20 35 52 68 80 85 h9 h10 h11 h12 h13 h14 h15 h16 = = = = = = = = 80 68 52 35 20 10 4 1
1 - z -5 H ( z) = 1 - z -1
4
SINC3 (Stage 4) 5th order decimate by 5 21 coefficients
1 - z -5 H ( z) = 1 - z -1
5
h0 = 1 h1 = 5 h2 = 15 h3 = 35 h4 = 70 h5 = 121 h6 = 185 h7 = 255 h8 = 320 h9 = 365 h10 = 381 h0 h1 h2 h3 h4 h5 h0 h1 h2 h3 h4 h5 h6 h0 h1 h2 h3 h4 h5 h6 = = = = = = = = = = = = = = = = = = = = 1 5 10 10 5 1 1 6 21 50 90 126 141 1 6 15 20 15 6 1
h11 = h12 = h13 = h14 = h15 = h16 = h17 = h18 = h19 = h20 =
365 320 255 185 121 70 35 15 5 1
SINC3 (Stage 5) 5th order decimate by 2 6 coefficients
1 - z -2 H ( z) = 1 - z -1
5
SINC3 (Stage 6) 6th order decimate by 3 13 coefficients
1 - z -3 H ( z) = 1 - z -1
6
h7 h8 h9 h10 h11 h12
= = = = = =
126 90 50 21 6 1
SINC3 (Stage 7) 6th order decimate by 2 7 coefficients
1 - z -2 H ( z) = 1 - z -1
6
Table 13. SINC3 Filter Coefficients
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FIR1 Filter - decimate by 4
FIR2 Filter - decimate by 2
Figure 25. FIR Filter Block Diagram
13. FIR FILTER
The finite impulse response (FIR) filter block consists of two cascaded stages, FIR1 and FIR2. It compensates for SINC filter droop and creates a low-pass corner to block aliased components of the input signal. On-chip linear phase or minimum phase coefficients can be selected using a configuration command, or the coefficients can be programmed for a custom filter response.
13.2 FIR2 Filter
The FIR2 filter stage has a decimate by two architecture. It creates a low-pass brick wall filter to block aliased components of the input signal. The on-chip linear and minimum phase coefficient sets are 126-tap, with a maximum 255 programmable coefficients. All coefficients are normalized to 24-bit two's complement full scale, 0x7FFFFF. The characteristic equation for FIR2 is a convolution of the input values, X(n), and the filter coefficients, h(k), to produce an output value, Y. Y = [h(k)*X(n-k)] + [h(k+1)*X(n-(k+1))] + ...
13.1 FIR1 Filter
The FIR1 filter stage has a decimate by four architecture. It compensates for SINC filter droop and flattens the magnitude response of the pass band. The on-chip linear and minimum phase coefficient sets are 48-tap, with a maximum 255 programmable coefficients. All coefficients are normalized to 24-bit two's complement full scale, 0x7FFFFF. The characteristic equation for FIR1 is a convolution of the input values, X(n), and the filter coefficients, h(k), to produce an output value, Y. Y = [h(k)*X(n-k)] + [h(k+1)*X(n-(k+1))] + ...
13.3 On-Chip FIR Coefficients
Two sets of on-chip coefficients, linear phase and minimum phase, are available for FIR1 and FIR2. Performance of the on-chip coefficient sets is very good, with excellent ripple and stop band characteristics as described in Figure 26 and Table 14. Which on-chip coefficient set to use is selected by a data word following the `Write ROM Coefficients' configuration command. See "Filter Coefficient Selection" on page 38 for information about selecting on-chip coefficient sets.
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13.4 Programmable FIR Coefficients
A maximum of 255 + 255 coefficients can be programmed into FIR1 and FIR2 to create a custom filter response. The total number of coefficients for the FIR filter is fundamentally limited by the available computation cycles in the digital filter, which itself is determined by the digital filter clock rate. Custom filter sets should normalize the maximum coefficient value to 24-bit two's complement full scale, 0x7FFFFF, and scale all other coefficients accordingly. To maintain maximum internal dynamic range, the CS5378 FIR filter performs double precision calculations with an automatic gain correction to scale the final output. Custom FIR coefficients are uploaded using the `Write FIR Coefficients' configuration command. See "EEPROM Configuration Commands" on page 27 or "Microcontroller Configuration Commands" on page 33 for information about writing custom FIR coefficients.
13.5 FIR Filter Synchronization
The FIR1 and FIR2 filters are synchronized to the external system by the MSYNC signal, which is generated from the SYNC input. The MSYNC signal sets a reference time (time 0) for all filter operations, and the FIR filters are restarted to phase align with this reference time.
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FIR1 - Single stage, fixed decimate by 4 Coefficient set 0: linear phase decimate by 4, 48 coefficients Coefficient set 1: minimum phase decimate by 4, 48 coefficients SINC droop compensation filter FIR2 - Single stage, fixed decimate by 2 Coefficient set 0: linear phase decimate by 2, 126 coefficients Coefficient set 1: minimum phase decimate by 2, 126 coefficients Brick wall low-pass filter, flat to 40% fs
Combined SINC + FIR digital filter specifications Passband ripple less than +/- 0.01 dB below 40% fs Transition band -3 dB frequency at 42.89% fs Stopband attenuation greater than 130 dB above 50% fs
Figure 26. FIR Filter Stages
SINC + FIR filters
FIR2 Output Word Rate 4000 2000 1000 500 333 250 200 125 100 50 40 25 20 10 5 1 SINC Decimation 16 32 64 128 192 256 320 512 640 1280 1600 2560 3200 6400 12800 64000 FIR1 Decimation 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 FIR2 Decimation 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Total Decimation 128 256 512 1024 1536 2048 2560 4096 5120 10240 12800 20480 25600 51200 102400 512000 Passband Ripple ( dB) 0.0042 0.0045 0.0040 0.0041 0.0080 0.0064 0.0043 0.0046 0.0040 0.0040 0.0040 0.0040 0.0036 0.0036 0.0036 0.0029 Stopband Attenuation (dB) 130.38 130.38 130.42 130.42 130.45 130.43 130.44 130.42 130.43 130.43 130.44 132.98 130.43 130.43 130.43 134.31
Table 14. FIR Filter Characteristics
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Individual filter stage group delay (no IIR)
Decimation Ratios 8 Stage 4 Stages 3,4 Stages 2,3,4 Stages 1,2,3,4 SINC3 Stage 7 Stage 6 Stages 5,7 Stages 4,7 Stages 3,5,7 Stages 3,4,7 Stages 2,3,5,7 Stages 1,2,3,5,7 FIR1 Coefficient Set 0 Coefficient Set 1 FIR2 Coefficient Set 0 Coefficient Set 1 2 2 126 126 62.5 See Figure 4 4 48 48 23.5 See Figure 2 3 2,2 5,2 5,2,2 5,5,2 5,5,2,2 5,5,5,2,2 7 13 6,7 21,7 17,6,7 17,21,7 17,17,6,7 17,17,17,6,7 3.0 6.0 8.5 25.0 50.5 133.0 260.5 1310.5 2 2,2 2,2,2 2,2,2,2 Number of Coefficients 36 7 6,7 5,6,7 5,5,6,7 Group Delay (Input Rate) 17.5 3.0 8.5 19.0 40.0
SINC1 SINC2
Cumulative linear phase group delay (no IIR)
FIR2 Output Word Rate 4000 2000 1000 500 333 250 200 125 100 50 40 25 20 10 5 1 SINC Output Group Delay (SINC Filter Input Rate) 41.5 85.5 169.5 337.5 553.5 721.5 885.5 1425.5 1701.5 3401.5 4341.5 6801.5 8421.5 16841.5 33681.5 168081.5 FIR1 Output Group Delay (SINC Filter Input Rate) 417.5 837.5 1673.5 3345.5 5065.5 6737.5 8405.5 13457.5 16741.5 33481.5 41941.5 66961.5 83621.5 167241.5 334481.5 1672081.5 FIR2 Output Group Delay (SINC Filter Input Rate) 4417.5 8837.5 17673.5 35345.5 53065.5 70737.5 88405.5 141457.5 176741.5 353481.5 441941.5 706961.5 883621.5 1767241.5 3534481.5 17672081.5 FIR2 Output Group Delay (FIR2 Output Word Rate) 34.5117 34.5215 34.5186 34.5171 34.5479 34.5398 34.5334 34.5355 34.5198 34.5197 34.5267 34.5196 34.5165 34.5164 34.5164 34.5158
Table 15. SINC + FIR Group Delay
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Minimum phase group delay
FIR1 Minimum Phase Group Delay (Normalized frequency)
FIR2 Minimum Phase Group Delay (Normalized frequency)
Table 16. Minimum Phase Group Delay
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Filter Type FIR1 (Coefficient set 0) Low pass, SINC compensation Linear phase decimate by 4 48 coefficients Filter Coefficients (normalized 24-bit) h0 = 558 h24 h1 = 1905 h25 h26 h2 = 3834 h3 = 5118 h27 h28 h4 = 365 h5 = -14518 h29 h6 = -39787 h30 h31 h7 = -67365 h8 = -69909 h32 h33 h9 = -19450 h10 = 97434 h34 h11 = 258881 h35 h36 h12 = 375562 h13 = 332367 h37 h38 h14 = 39864 h15 = -496361 h39 h16 = -1084130 h40 h41 h17 = -1392827 h18 = -1053303 h42 h43 h19 = 189436 h20 = 2266428 h44 h21 = 4768946 h45 h46 h22 = 7042723 h23 = 8388607 h47 h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 = = = = = = = = = = = = = = = = = = = = = = = = 3337 22258 88284 266742 655747 1371455 2502684 4031988 5783129 7396359 8388607 8325707 6988887 4531706 1507479 -1319126 -3207750 -3736028 -2980701 -1421498 237307 1373654 1711919 1322371 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 h39 h40 h41 h42 h43 h44 h45 h46 h47
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
8388607 7042723 4768946 2266428 189436 -1053303 -1392827 -1084130 -496361 39864 332367 375562 258881 97434 -19450 -69909 -67365 -39787 -14518 365 5118 3834 1905 558 555919 -165441 -581479 -617500 -388985 -99112 114761 186557 141374 58582 -12664 -42821 -35055 -16792 367 7929 5926 2892 23 -1164 -538 -238 18 113
FIR1 (Coefficient set 1) Low pass, SINC compensation Minimum phase decimate by 4 48 coefficients
Figure 27. FIR1 Coefficients
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Filter Type FIR2 (Coefficient set 0) Low pass, passband to 40% fs Linear phase decimate by 2 126 coefficients Filter Coefficients (normalized 24-bit)
h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 h39 h40 h41 h42 h43 h44 h45 h46 h47 h48 h49 h50 h51 h52 h53 h54 h55 h56 h57 h58 h59 h60 h61 h62 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -71 -371 -870 -986 34 1786 2291 291 -2036 -943 2985 3784 -1458 -5808 -1007 7756 5935 -7135 -11691 3531 17500 4388 -20661 -15960 18930 29808 -9795 -42573 -7745 49994 33021 -47092 -62651 29702 90744 4436 -109189 -54172 109009 114154 -81993 -174452 22850 221211 68863 -238025 -187141 208018 318763 -116005 -443272 -49958 533334 298975 -553873 -642475 454990 1113788 -137179 -1854336 -766230 3875315 8388607 h63 h64 h65 h66 h67 h68 h69 h70 h71 h72 h73 h74 h75 h76 h77 h78 h79 h80 h81 h82 h83 h84 h85 h86 h87 h88 h89 h90 h91 h92 h93 h94 h95 h96 h97 h98 h99 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 = 8388607 = 3875315 = -766230 = -1854336 = -137179 = 1113788 = 454990 = -642475 = -553873 = 298975 = 533334 = -49958 = -443272 = -116005 = 318763 = 208018 = -187141 = -238025 = 68863 = 221211 = 22850 = -174452 = -81993 = 114154 = 109009 = -54172 = -109189 = 4436 = 90744 = 29702 = -62651 = -47092 = 33021 = 49994 = -7745 = -42573 = -9795 = 29808 = 18930 = -15960 = -20661 = 4388 = 17500 = 3531 = -11691 = -7135 = 5935 = 7756 = -1007 = -5808 = -1458 = 3784 = 2985 = -943 = -2036 = 291 = 2291 = 1786 = 34 = -986 = -870 = -371 = -71
Figure 28. FIR2 Linear Phase Coefficients
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Filter Type FIR2 (Coefficient set 1) Low pass, passband to 40% fs Minimum phase decimate by 2 126 coefficients Filter Coefficients (normalized 24-bit)
h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 h39 h40 h41 h42 h43 h44 h45 h46 h47 h48 h49 h50 h51 h52 h53 h54 h55 h56 h57 h58 h59 h60 h61 h62 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 4019 43275 235427 848528 2240207 4525758 7077833 8388607 6885673 2483461 -2538963 -4800543 -2761696 1426109 3624338 1820814 -1695825 -2885148 -605252 2135021 1974197 -630111 -2168177 -750147 1516192 1550127 -508445 -1686937 -437822 1308705 1069556 -657282 -1301014 -30654 1173754 579643 -803111 -895851 328399 962522 124678 -820948 -466657 545674 652827 -220448 -680495 -80886 578844 306445 -395302 -431004 181900 454403 15856 -395525 -166123 284099 253485 -152407 -277888 28526 250843 h63 h64 h65 h66 h67 h68 h69 h70 h71 h72 h73 h74 h75 h76 h77 h78 h79 h80 h81 h82 h83 h84 h85 h86 h87 h88 h89 h90 h91 h92 h93 h94 h95 h96 h97 h98 h99 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 = 67863 = -190800 = -128546 = 114197 = 147750 = -46352 = -143269 = -13290 = 114721 = 51933 = -75952 = -68746 = 38171 = 68492 = -7856 = -57526 = -12540 = 41717 = 23334 = -25516 = -26409 = 11717 = 24246 = -1620 = -19248 = -4610 = 13356 = 7526 = -7887 = -8016 = 3559 = 7023 = -598 = -5350 = -1097 = 3579 = 1806 = -2058 = -1859 = 936 = 1558 = -224 = -1129 = -152 = 718 = 290 = -395 = -290 = 178 = 227 = -53 = -151 = -5 = 86 = 23 = -42 = -22 = 17 = 14 = -5 = -7 =1 =3
Figure 29. FIR2 Minimum Phase Coefficients
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1st Order IIR1 b10 Z-1 -a11 b11
2nd Order IIR2 b20 Z-1 -a21 Z-1 b21
3rd Order IIR3 implemented by running both IIR1 and IIR2 stages
-a22
b22
Figure 30. IIR Filter Block Diagram
14. IIR FILTER
The infinite impulse response (IIR) filter block consists of two cascaded stages, IIR1 and IIR2. It creates a high-pass corner to block very low-frequency and DC components of the input signal. On-chip IIR1 and IIR2 coefficients can be selected using a configuration command, or the coefficients can be programmed for a custom filter response. The characteristic equations for the 1st order IIR include an input value, X, an output value, Y, and two intermediate values, W1 and W2, separated by a delay element (z-1). W2 = W1 W1 = X + (-a11 * W2) Y = (W1 * b10) + (W2 * b11)
14.1 IIR Architecture
The architecture of the IIR filter is automatically determined when the output filter stage is selected in the FILTCFG register. Selecting the 1st order IIR1 filter bypasses the 2nd order stage, while selecting the 2nd order IIR2 filter bypasses the 1st order stage. Selection of the 3rd order IIR3 filter enables both the 1st and 2nd order stages.
14.3 IIR2 Filter
The 2nd order IIR filter stage is a direct form filter with five coefficients: a21, a22, b20, b21, and b22. Coefficients of a 2nd order IIR are inherently normalized to two, and should be scaled to 24-bit two's complement full scale, 0x7FFFFF. Normalization effectively divides the 2nd order coefficients in half relative to the input, and requires modification of the characteristic equations. The characteristic equations for the 2nd order IIR include an input value, X, an output value, Y, and three intermediate values, W3, W4, and W5, each separated by a delay element (z-1). The following
14.2 IIR1 Filter
The 1st order IIR filter stage is a direct form filter with three coefficients: a11, b10, and b11. Coefficients of a 1st order IIR are inherently normalized to one, and should be scaled to 24-bit two's complement full scale, 0x7FFFFF.
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characteristic equations model the operation of the 2nd order IIR filter with unnormalized coefficients. W5 = W4 W4 = W3 W3 = X + (-a21 * W4) + (-a22 * W5) Y = (W3 * b20) + (W4 * b21) + (W5 * b22) Internally, the CS5378 uses normalized coefficients to perform the 2nd order IIR filter calculation, which changes the algorithm slightly. The following characteristic equations model the operation of the 2nd order IIR filter when using normalized coefficients. W5 = W4 W4 = W3 W3 = 2 * [(X / 2) + (-a21 * W4) + (-a22 * W5)] Y = 2 * [(W3 * b20) + (W4 * b21) + (W5 * b22)] Which on-chip coefficient set to use is selected by a data word following the `Write ROM Coefficients' configuration command. See "Filter Coefficient Selection" on page 38 for information about selecting on-chip coefficient sets.
14.6 Programmable IIR Coefficients
A maximum of 3 + 5 coefficients can be programmed into IIR1 and IIR2 to create a custom filter response. Custom filter sets should normalize the coefficients to 24-bit two's complement full scale, 0x7FFFFF. To maintain maximum internal dynamic range, the CS5378 IIR filter performs double precision calculations with an automatic gain correction to scale the final output. Custom IIR coefficients are uploaded using the `Write IIR Coefficients' configuration command. See "EEPROM Configuration Commands" on page 27 or "Microcontroller Configuration Commands" on page 33 for information about writing custom IIR coefficients.
14.4 IIR3 Filter
The 3rd order IIR filter is implemented by running both the 1st order and 2nd order IIR filter stages. It can be modeled by cascading the characteristic equations of the 1st order and 2nd order IIR stages.
14.7 IIR Filter Synchronization
The IIR filter is not synchronized to the external system directly, only indirectly through the synchronization of the SINC and FIR filters. Because IIR filters have `infinite' memory, a discontinuity in the input data stream from a synchronization event can require significant time to settle out. The exact settling time depends on the size of the discontinuity and the filter coefficient characteristics.
14.5 On-Chip IIR Coefficients
Five sets of on-chip coefficients are available for IIR1 and IIR2, each providing a 3 Hz high-pass Butterworth response at different output word rates. Characteristics of the on-chip coefficient sets are described in Figure 31 and Table 16.
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IIR1 - Single stage, no decimation 1st order no decimation, 3 coefficients Coefficient Coefficient Coefficient Coefficient Coefficient set set set set set 0: 1: 2: 3: 4: high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% fs fs fs fs fs (3 (3 (3 (3 (3 Hz Hz Hz Hz Hz at at at at at 2000 SPS) 1000 SPS) 500 SPS) 333 SPS) 250 SPS)
IIR2 - Single stage, no decimation 2nd order no decimation, 5 coefficients Coefficient Coefficient Coefficient Coefficient Coefficient set set set set set 0: 1: 2: 3: 4: high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% fs fs fs fs fs (3 (3 (3 (3 (3 Hz Hz Hz Hz Hz at at at at at 2000 SPS) 1000 SPS) 500 SPS) 333 SPS) 250 SPS)
IIR3 - Two stage, no decimation 3rd order no decimation, 8 coefficients (Combined IIR1 and IIR2 filter responses) Coefficient Coefficient Coefficient Coefficient Coefficient set set set set set 0,0: 1,1: 2,2: 3,3: 4,4: high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.20% 0.41% 0.82% 1.22% 1.63% fs fs fs fs fs (4 (4 (4 (4 (4 Hz Hz Hz Hz Hz at at at at at 2000 SPS) 1000 SPS) 500 SPS) 333 SPS) 250 SPS)
Figure 31. IIR Filter Stages
IIR filters
IIR1 Coeff Selection 0 1 2 3 4 IIR1 Corner Frequency 0.15% fs 0.30% fs 0.60% fs 0.90% fs 1.20% fs IIR2 Coeff Selection 0 1 2 3 4 IIR2 Corner Frequency 0.15% fs 0.30% fs 0.60% fs 0.90% fs 1.20% fs IIR3 Coeff Selection 0,0 1,1 2,2 3,3 4,4 IIR3 Corner Frequency 0.2041% fs 0.4074% fs 0.8152% fs 1.2222% fs 1.6293% fs
Table 16. IIR Filter Characteristics
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Filter Type IIR1 (Coefficient set 0) 1st order, high pass Corner at 0.15% fs 3 coefficients IIR1 (Coefficient set 1) 1st order, high pass Corner at 0.30% fs 3 coefficients IIR1 (Coefficient set 2) 1st order, high pass Corner at 0.60% fs 3 coefficients IIR1 (Coefficient set 3) 1st order, high pass Corner at 0.90% fs 3 coefficients IIR1 (Coefficient set 4) 1st order, high pass Corner at 1.20% fs 3 coefficients Filter Type IIR2 (Coefficient set 0) 2nd order, high pass Corner at 0.15% fs 5 coefficients System Function Filter Coefficients (normalized 24-bit) a11 = -8309916 b10 = 8349262 b11 = -8349262
b + b z -1 H ( z ) = 10 11 -1 1+ a z 11 b + b z -1 H ( z ) = 10 11 -1 1+ a z 11 b + b z -1 H ( z ) = 10 11 -1 1+ a z 11 b + b z -1 H ( z ) = 10 11 -1 1+ a z 11 b10 + b11 z -1 H ( z) = 1 + a z -1 11
System Function
a11 = -8231957 b10 = 8310282 b11 = -8310282
a11 = -8078179 b10 = 8233393 b11 = -8233393
a11 = -7927166 b10 = 8157887 b11 = -8157887
a11 = -7778820 b10 = 8083714 b11 = -8083714
b20 + b21 z -1 + b22 z -1 H ( z) = 1 + a z -1 + a z -1 21 22 b + b21 z -1 + b22 z -1 H ( z ) = 20 1 + a z -1 + a z -1 21 22 b + b21 z -1 + b22 z -1 H ( z ) = 20 1 + a z -1 + a z -1 21 22 b + b21 z -1 + b22 z -1 H ( z ) = 20 1 + a z -1 + a z -1 21 22 b + b21 z -1 + b22 z -1 H ( z ) = 20 1 + a z -1 + a z -1 21 22
Filter Coefficients (normalized 24-bit) a21 = -8332704 a22 = 4138771 b20 = 4166445 b21 = -8332890 b22 = 4166445 a21 a22 b20 b21 b22 a21 a22 b20 b21 b22 a21 a22 b20 b21 b22 a21 a22 b20 b21 b22 = = = = = = = = = = = = = = = = = = = = -8276806 4083972 4138770 -8277540 4138770 -8165041 3976543 4083972 -8167944 4083972 -8053350 3871939 4029898 -8059796 4029898 -7941764 3770088 3976539 -7953078 3976539
IIR2 (Coefficient set 1) 2nd order, high pass Corner at 0.30% fs 5 coefficients
IIR2 (Coefficient set 2) 2nd order, high pass Corner at 0.60% fs 5 coefficients
IIR2 (Coefficient set 3) 2nd Order, high pass Corner at 0.90% fs 5 coefficients
IIR2 (Coefficient set 4) 2nd order, high pass Corner at 1.20% fs 5 coefficients
Table 17. IIR Filter Coefficients DS639F1 55
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MDI Input 512 kHz
SINC Filter
FIR Filters
IIR Filter
Gain Correction
Offset Correction
Output to High Speed Serial Data Port (SD Port) Output Rate 4000 SPS ~ 1 SPS
Offset Calibration
Figure 32. Gain and Offset Correction
15. GAIN AND OFFSET CORRECTION
The CS5378 digital filter can apply gain and offset corrections to the measurement data. Also, an offset calibration algorithm can automatically calculate the offset correction value. A gain correction value is written to the GAIN registers (0x21), while an offset correction value is written to the OFFSET register (0x25). Gain and offset corrections are enabled by the USEGR and USEOR bits in the FILTCFG register (0x20). When enabled, the offset calibration algorithm will automatically calculate an offset correction value and write it into the OFFSET register. Offset calibration is enabled by writing the EXP and ORCAL bits in FILTCFG. A gain correction value is 24-bit two's complement with unity gain defined as full scale, 0x7FFFFF. Gain correction always scales to a fractional value, and can never gain the digital filter data greater than one. Output Value = Data * (GAIN / 0x7FFFFF) Unity Gain: GAIN = 0x7FFFFF 50% Gain: GAIN = 0x3FFFFF Zero Gain: GAIN = 0x000000 Once the GAIN register is written, the USEGR bit in the FILTCFG register enables gain correction.
15.2 Offset Correction
Offset correction in the CS5378 cancels the DC bias of a measurement channel by subtracting the value in the OFFSET register (0x25) from the digital filter output data word. An offset correction value is 24-bit two's complement with a maximum positive value of 0x7FFFFF,
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15.1 Gain Correction
Gain correction in the CS5378 normalizes sensor gain in multi-sensor networks. It requires an externally calculated correction value to be written into the GAIN register (0x21).
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and a maximum negative value of 0x800000. If applying an offset correction causes the final result to exceed a 24-bit two's complement maximum, the output data will saturate to that maximum value. Output Data = Input Data - Offset Correction Max Positive Output Value = 0x7FFFFF Max Negative Output Value = 0x800000 Once the OFFSET register is written, the USEOR bit in the FILTCFG register enables offset correction. FILTCFG register, with larger exponent values producing a smoother averaging function that requires a longer settling time, and smaller values producing a noisier averaging function that requires a shorter settling time. Typical exponential values range from 0x05 to 0x0F, depending on the available settling time. The characteristic equations of the offset calibration algorithm include an input value, X, an output value, Y, a summation value, YSUM, a sample index, n, and an exponential value, EXP. Y(n) = X(n) - [YSUM(n-1) >> EXP] YSUM(n) = Y(n) + YSUM(n-1) Offset Correction = YSUM >> EXP Once the EXP bits are written, the ORCAL bit in the FILTCFG register is set to enable offset calibration. When enabled, an updated offset correction value is automatically written to the OFFSET register. When the offset calibration algorithm is fully settled, the ORCAL bit should be cleared to maintain the final value in the OFFSET register.
15.3 Offset Calibration
An offset calibration algorithm in the CS5378 can automatically calculate an offset correction value. When using the offset calibration algorithm, background noise data should be used as the input signal for calculating the offset of the measurement channel. The offset calibration algorithm is an exponential averaging function that places increased weight on more recent digital filter data. The exponential weighting factor is set by the EXP bits in the
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System Telemetry
Data Ready Clock Out Data In
CS5378
DRDY SCK MISO
Figure 33. Serial Data Interface Block Diagram
16. SERIAL DATA INTERFACE
Once digital filtering is complete, each 24-bit output sample is combined with an 8-bit status byte. These data words are written to an 8-deep FIFO buffer and then transmitted to the communications channel through a high speed serial data interface.
MISO - Pin 25
Serial data output.
16.2 Serial Data Format
Serial data transactions transfer either 24-bit data words or 32-bit status+data words, depending on the STAT bit in the CONFIG register. When transmitting status information, each 8-bit status byte has an MFLAG bit, a time break bit, and a FIFO overflow bit encoded as shown in Figure 34.
16.1 Pin Descriptions DRDY - Pin 23
Data ready output signal, active low. Open drain output requiring an external pull-up resistor.
SCK - Pin 24
Serial clock input.
MFLAG Bit - MFLAG
The MFLAG bit is set in the status byte when an signal is received on the MFLAG pin. When re-
31 Status
23 Data
0
MFLAG 31
-30
-29
-28
-27
TB 26
-25
W 24
0 - Modulator Ok 1 - Modulator Error
0 - No Time Break 1 - Time Break
0 - FIFO Ok 1 - FIFO Overflow
Figure 34. 32-bit Serial Data Format
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ceived, the MFLAG bit is set in the next output word. See "Modulator Interface" on page 36 for more information about MFLAG. The W bit is sticky, meaning it persists indefinitely once set. Clearing the W bit requires sending the `Filter Stop' and `Filter Start' configuration commands to reinitialize the data FIFO.
Time Break Bit - TB
The time break bit marks a timing reference based on a rising edge into the TIMEB pin. After a programmed delay, the TB bit in the status byte is set for one output sample. The TIMEBRK digital filter register (0x29) programs the sample delay for the TB bit output. See "Time Break Controller" on page 63 for more information about time break.
Conversion Data Word
The lower 24-bits of the serial data word is the conversion sample for the specified channel. Conversion data is 24-bit two's complement format.
16.3 Serial Data Transactions
The CS5378 automatically initiates serial data transactions whenever data becomes available in the output FIFO by driving the DRDY pin low. Once a serial data transaction is initiated, serial clocks received into SCK cause data to be output to MISO, as shown in Figure 35. When all available data is read from the serial data FIFO, DRDY is released.
FIFO Overflow Bit - W
The FIFO overflow bit indicates an error condition in the serial data FIFO, and is set if new digital filter data overwrites a FIFO location containing data which has not yet been sent.
DRDY
SCK
MISO
MSB
LSB
Figure 35. SD Port Transaction
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Digital Filter Data Bus 24-bit TBSGAIN Register 24-bit Digital Modulator 1-bit TBSDATA
Figure 36. Test Bit Stream Generator Block Diagram
17. TEST BIT STREAM GENERATOR
The CS5378 test bit stream (TBS) generator creates sine wave or impulse bit stream data to drive an external test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter.
17.3 TBS Configuration
Configuration options for the TBS generator are set through the TBSCFG register (0x2A). Gain scaling of the TBS generator output is set by the TBSGAIN register (0x2B).
17.1 Pin Descriptions TBSDATA - Pin 8
Test bit stream 1-bit data output.
Interpolation Factor - INTP[7:0]
Selects how many times the interpolator uses a data point when generating the output bit stream. Interpolation is zero based and represents one greater than the programmed register value.
MCLK - Pin 11
Test bit stream clock output.
Operational Mode - TMODE
Selects between sine wave or impulse output mode.
17.2 TBS Architecture
The test bit stream generator consists of a data interpolator and a digital modulator. It receives periodic 24-bit data from the digital filter to create a 1-bit data output on the TBSDATA pin. The TBS input data from the digital filter is scaled by the TBSGAIN register (0x2B). Maximum stable amplitude is 0x04FFFF, with 0x04B000 approximately full scale for the CS4373 test DAC. The full scale 1-bit output from the TBS generator is defined as 25% minimum and 75% maximum one's density.
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Output Rate - RATE[2:0]
Selects the TBSDATA output rate.
Synchronization - TSYNC
Enables synchronization of the TBS output phase to the MSYNC signal.
Loopback - LOOP
Enables digital loopback from the TBS output to the MDATA inputs.
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Test Bit Stream Characteristic Equation:
(Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate
Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz
Signal Frequency (TBSDATA)
Output Rate (TBSCLK)
Output Rate Selection (RATE)
Interpolation Selection (INTP)
10.00 Hz 10.00 Hz 25.00 Hz 25.00 Hz 31.25 Hz 31.25 Hz 50.00 Hz 50.00 Hz 125.00 Hz 125.00 Hz
256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz 256 kHz 512 kHz
0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5 0x4 0x5
0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table 18. TBS Configurations Using On-chip Data
Run - RUN
Enables the test bit stream generator.
17.5 TBS Sine Wave Output
When the TMODE bit in the TBSCFG register is low, the TBS generator operates in sine wave mode. In this mode, sine wave data from digital filter memory is used to create a sine wave test signal that can drive a test DAC. Sine wave frequency and output data rate are calculated as shown by the characteristic equation of Table 18. The sine wave maximum one's density output from the TBS generator is set by the TBSGAIN register. TBSGAIN can be programmed up to a maximum of 0x04FFFF, with the TBS generator unstable for higher amplitudes. For the CS4373 test DAC, a gain value of 0x04B000 produces an approximately full scale sine wave output (5 Vpp differential).
Data Delay - DDLY[5:0]
Programs full period delays for TBSDATA, up to a maximum of 63 bits.
Gain - TBSGAIN[23:0]
Scales the amplitude of the sine wave output and generated impulse. Maximum 0x04FFFF, nominal 0x04B000.
17.4 TBS Data Source
An on-chip 24-bit 1024 point digital sine wave is stored on the CS5378 which will produce the test signal frequencies listed in Table 18. Additional discrete test frequencies and output rates can be programmed by varying the interpolation factor and output rate.
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Test Bit Stream Impulse Characteristics:
Interpolation Selection (INTP) Output Rate Selection (RATE) Pulse Width from CS4373 Gain Scale Factor (TBSGAIN) Pulse Height from CS4373
0xFF 0xFF 0xFF 0x7F 0x7F 0x7F
0x5 0x4 0x3 0x5 0x4 0x3
500 s 1 ms 2 ms 250 s 500 s 1 ms
0x04B000 0x04B000 0x04B000 0x04B000 0x04B000 0x04B000
~ 860 mV ~ 820 mV ~ 820 mV ~ 820 mV ~ 820 mV ~ 820 mV
Table 19. TBS Impulse Characteristics
17.6 TBS Impulse Output
If the TMODE bit in TBSCFG is set high, the TBS generator operates in impulse mode. In this mode, the value in TBSGAIN sets the amplitude of the generated impulse. Impulse amplitude and period are shown in Table 19. To create a maximum impulse from the TBS generator, the TBSGAIN register should be set to 0x04FFFF, and the INTP bits in TBSCFG should also be set to 0xFF. The RATE bits should always be set to produce data at the correct rate for the intended test DAC. A rising edge on the TIMEB pin triggers the impulse output. When impulse mode is enabled but no TIMEB input is received, the TBS generator uses a negated TBSGAIN register as a repetitive input value. When a rising edge is recognized on the TIMEB pin, a single positive TBSGAIN value is written to the TBS generator to create the impulse.
filter, and data collection interface. Digital loopback testing expects 512 kHz data into the MDATA input. A mismatch of the TBS generator full scale output and the MDATA full scale input results in an amplitude mismatch when testing in loopback mode. The TBS generator outputs a 75% maximum one's density, while the MDATA inputs expect an 86% maximum one's density from a modulator, resulting in a measured full scale error of approximately -3.6 dB.
17.8 TBS Synchronization
When the TSYNC bit is set in the TBSCFG register, the MSYNC signal resets the sine wave data pointer and phase aligns the TBS signal output. Once the digital filter is settled, all CS5378 devices receiving the SYNC signal will have identical TBS signal phase. See "Synchronization" on page 24 for more information about the SYNC and MSYNC signals. If TSYNC is clear, MSYNC has no effect on the TBS data pointer and no change in the TBS output phase will occur during synchronization.
17.7 TBS Loopback Testing
Included as part of the CS5378 test bit stream generator is a feedback path to the digital filter MDATA input. This loopback mode provides a fully digital signal path to test the TBS generator, digital
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TIMEB
TIMEBRK Delay Counter
TB Flag in Serial Data Status Byte
Figure 37. Time Break Block Diagram
18. TIME BREAK CONTROLLER
A time break signal is used to mark timing events that occur during measurement. An external signal sets a flag in the status byte of an output sample to mark when the external event occurred. A rising edge input to the TIMEB pin causes the TB timing reference flag to be set in the serial data status byte. When set, the TB flag appears for only one output sample in the status byte. The TB flag output can be delayed by programming a sample delay value into the TIMEBRK digital filter register.
18.3 Time Break Delay
The TIMEBRK register (0x29) sets a sample delay between a received rising edge on the TIMEB pin and writing the TB flag into the serial data status byte. The programmable sample counter can compensate for group delay through the digital filters. When the proper group delay value is programmed into the TIMEBRK register, the TB flag will be set in the status byte of the measurement sample taken when the timing reference signal was received.
18.3.1 Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5378 measurement channel is to use the time break signal as both a timing reference input and an analog step input.
18.1 Pin Description TIMEB - Pin 20
Time break input pin, rising edge triggered.
18.2 Time Break Operation
An externally generated timing reference signal applied to the TIMEB pin initiates an internal sample counter. After a number of output samples have passed, programmed in the TIMEBRK digital filter register (0x29), the TB flag is set in the status byte of the serial data output word. The TB flag is automatically cleared for subsequent data words, and appears for only one output sample.
When a rising edge is received on the TIMEB pin with no delay programmed into the TIMEBRK register, the TB flag is set in the next serial data status byte. The same rising edge can act as a step input to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. By comparing the timing of the TB status flag output and the rising edge in the measurement data, the measurement channel group delay can be determined.
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GP_PULL
Pull Up Logic
R
GP_DATA
GPIO
GP_DIR
Figure 38. GPIO Block Diagram
19. GENERAL PURPOSE I/O
The General Purpose I/O (GPIO) block provides 8 general purpose pins to interface with external hardware. GP_PULL bits enable/disable the internal pull-up resistor, and GP_DATA bits set the output data value. After reset, GPIO pins default as inputs with pull-up resistors enabled.
19.1 Pin Descriptions GPIO[3:0] - Pins 4 - 1
Standard GPIO pins.
19.4 GPIO Input Mode
When reading a value from the GP_DATA bits, the returned data reports the current state of the pins. If a pin is externally driven high it reads a logical 1, if externally driven low it reads a logical 0. When a GPIO pin is used as an input, the pull-up resistor should be disabled to save power if it isn't required.
GPIO[6:4]:PLL[2:0] - Pins 7 - 5
Standard GPIO pins also used to select the PLL mode after reset. Internal pull-ups default high, 10 k external pull-downs required to set low.
GPIO7:BOOT - Pin 28
Standard GPIO pin also used to select boot mode after reset. Internal pull-up defaults high, 10 k external pull-down required to set low.
19.5 GPIO Output Mode
When a GPIO pin is programmed as an output with a data value of 0, the pin is driven low and the internal pull-up resistor is automatically disabled. When programmed as an output with a data value of 1, the pin is driven high and the pull-up resistor is inconsequential. Any GPIO pin can be used as an open-drain output by setting the data value to 0, enabling the pull-up, and using the GP_DIR direction bits to control the pin value. This open-drain output configuration uses the internal pull-up resistor to hold the pin high when GP_DIR is set as an input, and drives the pin low when GP_DIR is set as an output.
19.2 GPIO Architecture
Each GPIO pin can be configured as input or output, high or low, with a weak (~100 k) internal pull-up resistor enabled or disabled. Figure 38 shows the structure of a bi-directional GPIO pin.
19.3 GPIO Registers
GPIO pin settings are programmed in the GPCFG register. GP_DIR bits set the input/output mode,
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19.5.1 GPIO Reads in Output Mode When reading GPIO pins the GP_DATA register value always reports the current state of the pins, so a value written in output mode does not necessarily read back the same value. If a pin in output mode is written as a logical 1, the CS5378 attempts to drive the pin high. If an external device forces the pin
low, the read value reflects the pin state and returns a logical 0. Similarly, if an output pin is written as a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. In both cases the CS5378 is in contention with the external device resulting in increased power consumption.
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20. REGISTER SUMMARY 20.1 SPI Registers
The CS5378 SPI registers interface the serial port to the digital filter.
Name Addr. Type # Bits Description
SPICTRLH SPICTRLM SPICTRLL SPICMDH SPICMDM SPICMDL SPIDAT1H SPIDAT1M SPIDAT1L SPIDAT2H SPIDAT2M SPIDAT2L
00 01 02 03 04 05 06 07 08 09 0A 0B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8 8 8 8 8 8 8 8 8 8 8 8
SPI Control Register, High Byte SPI Control Register, Middle Byte SPI Control Register, Low Byte SPI Command, High Byte SPI Command, Middle Byte SPI Command, Low Byte SPI Data 1, High Byte SPI Data 1, Middle Byte SPI Data 1, Low Byte SPI Data 2, High Byte SPI Data 2, Middle Byte SPI Data 2, Low Byte
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20.1.1 SPICTRL : 0x00, 0x01, 0x02
Figure 39. SPI Control Register SPICTRL
(MSB) 23 -R/W 0 22 -R/W1 0 21 -R/W 0 20 -R/W 0 19 -R/W 1 18 -R/W 0 17 -R/W 1 16 -R/W 1
SPI Address: 0x00 0x01 0x02
-15 SMODF R 0 14 -R/W 0 13 -R 0 12 EMOP R 0 11 SWEF R 0 10 -R/W 0 9 -R/W 1 8 E2DREQ R/W 0
R W R/W
Not defined; read as 0 Readable Writable Readable and Writable
7 -R/W 0
6 -R/W 0
5 -R/W 1
4 -R/W 0
3 -R/W 0
2 -R/W 0
1 -R/W 0
(LSB) 0 -R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 -reserved 15 SMODF SPI mode fault flag reserved External master to SPI operation in progress flag SPI write collision error flag reserved 7:0 -reserved
14:13 -12 EMOP
11
SWEF
10:9 8
--
E2DREQ External master to digital filter request flag
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20.1.2 SPICMD : 0x03, 0x04, 0x05
Figure 40. SPI Command Register SPICMD
(MSB) 23 SCMD23 R/W 0 22 SCMD22 R/W 0 21 SCMD21 R/W 0 20 SCMD20 R/W 0 19 SCMD19 R/W 0 18 SCMD18 R/W 0 17 SCMD17 R/W 0 16 SCMD16 R/W 0
SPI Address: 0x03 0x04 0x05
-15 SCMD15 R/W 0 14 SCMD14 R/W 0 13 SCMD13 R/W 0 12 SCMD12 R/W 0 11 SCMD11 R/W 0 10 SCMD10 R/W 0 9 SCMD9 R/W 0 8 SCMD8 R/W 0
R W R/W
Not defined; read as 0 Readable Writable Readable and Writable
7 SCMD7 R/W 0
6 SCMD6 R/W 0
5 SCMD5 R/W 0
4 SCMD4 R/W 0
3 SCMD3 R/W 0
2 SCMD2 R/W 0
1 SCMD1 R/W 0
(LSB) 0 SCMD0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 SCMD[23:16] SPI Command High 15:8 Byte SCMD[15:8] SPI Command Mid- 15:8 dle Byte SCMD[7:0] SPI Command Low Byte
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20.1.3 SPIDAT1 : 0x06, 0x07, 0x08
Figure 41. SPI Data Register SPIDAT1
(MSB) 23 SDAT23 R/W 0 22 SDAT22 R/W 0 21 SDAT21 R/W 0 20 SDAT20 R/W 0 19 SDAT19 R/W 0 18 SDAT18 R/W 0 17 SDAT17 R/W 0 16 SDAT16 R/W 0
SPI Address: 0x06 0x07 0x08
-15 SDAT15 R/W 0 14 SDAT14 R/W 0 13 SDAT13 R/W 0 12 SDAT12 R/W 0 11 SDAT11 R/W 0 10 SDAT10 R/W 0 9 SDAT9 R/W 0 8 SDAT8 R/W 0
R W R/W
Not defined; read as 0 Readable Writable Readable and Writable
7 SDAT7 R/W 0
6 SDAT6 R/W 0
5 SDAT5 R/W 0
4 SDAT4 R/W 0
3 SDAT3 R/W 0
2 SDAT2 R/W 0
1 SDAT1 R/W 0
(LSB) 0 SDAT0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 SDAT[23:16] SPI Data High Byte 15:8 SDAT[15:8] SPI Data Middle Byte 15:8 SDAT[7:0] SPI Data Low Byte
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20.1.4 SPIDAT2 : 0x09, 0x0A, 0x0B
Figure 42. SPI Data Register SPIDAT2
(MSB) 23 SDAT23 R/W 0 22 SDAT22 R/W 0 21 SDAT21 R/W 0 20 SDAT20 R/W 0 19 SDAT19 R/W 0 18 SDAT18 R/W 0 17 SDAT17 R/W 0 16 SDAT16 R/W 0
SPI Address: 0x09 0x0A 0x0B
-15 SDAT15 R/W 0 14 SDAT14 R/W 0 13 SDAT13 R/W 0 12 SDAT12 R/W 0 11 SDAT11 R/W 0 10 SDAT10 R/W 0 9 SDAT9 R/W 0 8 SDAT8 R/W 0
R W R/W
Not defined; read as 0 Readable Writable Readable and Writable
7 SDAT7 R/W 0
6 SDAT6 R/W 0
5 SDAT5 R/W 0
4 SDAT4 R/W 0
3 SDAT3 R/W 0
2 SDAT2 R/W 0
1 SDAT1 R/W 0
(LSB) 0 SDAT0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 SDAT[23:16] SPI Data High Byte 15:8 SDAT[15:8] SPI Data Middle Byte 15:8 SDAT[7:0] SPI Data Low Byte
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CS5378
20.2 Digital Filter Registers
The CS5378 digital filter registers control hardware peripherals and filtering functions.
Name Addr. Type # Bits Description
CONFIG RESERVED GPCFG RESERVED FILTCFG GAIN RESERVED OFFSET RESERVED TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST
00 01-0D 0E 0F-1F 20 21 22-24 25 26-28 29 2A 2B 2C 2D 2E 2F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
Hardware Configuration Reserved GPIO[7:0] Direction, Pull-Up Enable, and Data Reserved Digital Filter Configuration Gain Correction Reserved Offset Correction Reserved Time Break Delay Test Bit Stream Configuration Test Bit Stream Gain User Defined System Register 1 User Defined System Register 2 Hardware Version ID Self-Test Result Code
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CS5378
20.2.1 CONFIG : 0x00
Figure 43. Hardware Configuration Register CONFIG
(MSB)23 -R/W 0 22 -R/W 0 21 -R/W 0 20 -R/W 0 19 -R/W 0 18 DFS2 R/W 1 17 DFS1 R/W 0 16 DFS0 R/W 1
DF Address: 0x00
-R W R/W
15 -R/W 0
14 -R/W 0
13 -R/W 0
12 -R/W 0
11 -R/W 0
10 MCKFS2 R/W 1
9 MCKFS1 R/W 0
8 MCKFS0 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 STAT R/W 0
6 -R/W 0
5 MCKEN2 R/W 0
4 MCKEN R/W 0
3 MDIFS R/W 0
2 -R/W 0
1 BOOT R 0
(LSB)0 MSEN R/W 1
Bits in bottom rows are reset condition
Bit definitions:
23:19 -reserved 15:11 -reserved 7:6 STAT Serial Data Status Byte 1: Disabled (24-bit output) 0: Enabled (32-bit output) MCLK/2 output enable 1: Enabled 0: Disabled MCLK output enable 1: Enabled 0: Disabled MDATA input frequency select 1: 256 kHz 0: 512 kHz reserved Boot source indicator 1: Booted from EEPROM 0: Booted from Micro MSYNC enable 1: MSYNC generated 0: MSYNC remains low
18:16 DFS [2:0]
Digital filter frequency select 111: Reserved 110: 8.192 MHz 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: 256 kHz 000: 32 kHz
10:8
MCKFS [2:0]
MCLK frequency select 5 111: reserved 110: reserved 101: 4.096 MHz 100: 2.048 MHz 4 011: 1.024 MHz 010: 512 kHz 001: reserved 000: reserved 3
MCKEN2
MCKEN
MDIFS
2 1
-BOOT
0
MSEN
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CS5378
20.2.2 GPCFG : 0x0E
Figure 44. GPIO Configuration Register GPCFG
(MSB) 23
GP_DIR7
22
GP_DIR6
21
GP_DIR5
20
GP_DIR4
19
GP_DIR3
18
GP_DIR2
17
GP_DIR1
16
GP_DIR0
DF Address: 0x0E
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
-R W R/W
15
GP_PULL7
14
GP_PULL6
13
GP_PULL5
12
GP_PULL4
11
GP_PULL3
10
GP_PULL2
9
GP_PULL1
8
GP_PULL0
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
Not defined; read as 0 Readable Writable Readable and Writable
7
GP_DATA7
6
GP_DATA6
5
GP_DATA5
4
GP_DATA4
3
GP_DATA3
2
GP_DATA2
1
GP_DATA1
(LSB) 0
GP_DATA0
Bits in bottom rows are reset condition
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
Bit definitions:
23:16 GP_DIR [7:0] GPIO pin direction 1: Output 0: Input 15:8 GP_PULL GPIO pullup resistor [7:0] 1: Enabled 0: Disabled 7:0 GP_DATA GPIO data value [7:0] 1: VDD 0: GND
Notes: GPIO[7] also used as BOOT mode select after reset GPIO[6:4] also used as PLL mode select after reset.
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20.2.3 FILTCFG : 0x20
Figure 45. Filter Configuration Register FILTCFG
(MSB) 23 -R/W 0 22 -R/W 0 21 -R/W 0 20 EXP4 R/W 0 19 EXP3 R/W 0 18 EXP2 R/W 0 17 EXP1 R/W 0 16 EXP0 R/W 0
DF Address: 0x20
-R W R/W
15 -R/W 0
14 ORCAL R/W 0
13 USEOR R/W 0
12 USEGR R/W 0
11 -R/W 0
10 FSEL2 R/W 0
9 FSEL1 R/W 0
8 FSEL0 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 DEC3 R/W 0
6 DEC2 R/W 0
5 DEC1 R/W 0
4 DEC0 R/W 0
3 -R/W 0
2 -R/W 0
1 -R/W 0
(LSB) 0 -R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:21 -reserved 15 14 -ORCAL reserved Run OFFSET calibration 1: Enable 0: Disable 7:4 DEC[3:0] Decimation selection (Output word rate) 0111: 0110: 0101: 0100: 0011: 0010: 0001: 0000: 1111: 1110: 1101: 1100: 1011: 1010: 1001: 1000: 3:0 -4000 SPS 2000 SPS 1000 SPS 500 SPS 333 SPS 250 SPS 200 SPS 125 SPS 100 SPS 50 SPS 40 SPS 25 SPS 20 SPS 10 SPS 5 SPS 1 SPS
20:16 EXP[4:0] OFFSET calibration exponent
13
USEOR
Use OFFSET correction 1: Enable 0: Disable
12
USEGR
Use GAIN correction 1: Enable 0: Disable
11 10:8
--
reserved
reserved
FSEL[2:0] Output filter stage select 111: reserved 110: reserved 101: IIR 3rd Order 100: IIR 2nd Order 011: IIR 1st Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output
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CS5378
20.2.4 GAIN : 0x21
Figure 46. Gain Correction Register GAIN
(MSB) 23 GAIN23 R/W 0 22 GAIN22 R/W 0 21 GAIN21 R/W 0 20 GAIN20 R/W 0 19 GAIN19 R/W 0 18 GAIN18 R/W 0 17 GAIN17 R/W 0 16 GAIN16 R/W 0
DF Address: 0x21
-R W R/W
15 GAIN15 R/W 0
14 GAIN14 R/W 0
13 GAIN13 R/W 0
12 GAIN12 R/W 0
11 GAIN11 R/W 0
10 GAIN10 R/W 0
9 GAIN9 R/W 0
8 GAIN8 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 GAIN7 R/W 0
6 GAIN6 R/W 0
5 GAIN5 R/W 0
4 GAIN4 R/W 0
3 GAIN3 R/W 0
2 GAIN2 R/W 0
1 GAIN1 R/W 0
(LSB) 0 GAIN0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 GAIN[23:16] Gain Correction Upper Byte 15:8 GAIN[15:8] Gain Correction Middle Byte 15:8 GAIN[7:0] Gain Correction Lower Byte
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CS5378
20.2.5 OFFSET : 0x25
Figure 47. Offset Correction Register OFFSET
(MSB) 23 OFST23 R/W 0 22 OFST22 R/W 0 21 OFST21 R/W 0 20 OFST20 R/W 0 19 OFST19 R/W 0 18 OFST18 R/W 0 17 OFST17 R/W 0 16 OFST16 R/W 0
DF Address: 0x25
-R W R/W
15 OFST15 R/W 0
14 OFST14 R/W 0
13 OFST13 R/W 0
12 OFST12 R/W 0
11 OFST11 R/W 0
10 OFST10 R/W 0
9 OFST9 R/W 0
8 OFST8 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 OFST7 R/W 0
6 OFST6 R/W 0
5 OFST5 R/W 0
4 OFST4 R/W 0
3 OFST3 R/W 0
2 OFST2 R/W 0
1 OFST1 R/W 0
(LSB) 0 OFST0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 OFST[23:16] Offset Correction Upper Byte 15:8 OFST[15:8] Offset Correction Middle Byte 15:8 OFST[7:0] Offset Correction Lower Byte
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CS5378
20.2.6 TIMEBRK : 0x29
Figure 48. Time Break Counter Register TIMEBRK
(MSB) 23 TBRK23 R/W 0 22 TBRK22 R/W 0 21 TBRK21 R/W 0 20 TBRK20 R/W 0 19 TBRK19 R/W 0 18 TBRK18 R/W 0 17 TBRK17 R/W 0 16 TBRK16 R/W 0
DF Address: 0x29
-R W R/W
15 TBRK15 R/W 0
14 TBRK14 R/W 0
13 TBRK13 R/W 0
12 TBRK12 R/W 0
11 TBRK11 R/W 0
10 TBRK10 R/W 0
9 TBRK9 R/W 0
8 TBRK8 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 TBRK7 R/W 0
6 TBRK6 R/W 0
5 TBRK5 R/W 0
4 TBRK4 R/W 0
3 TBRK3 R/W 0
2 TBRK2 R/W 0
1 TBRK1 R/W 0
(LSB) 0 TBRK0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 TBRK[23:16] Time Break Counter 15:8 Upper Byte TBRK[15:8] Time Break Counter 15:8 Middle Byte TBRK[7:0] Time Break Counter Lower Byte
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CS5378
20.2.7 TBSCFG : 0x2A
Figure 49. Test Bit Stream Configuration Register TBSCFG
(MSB) 23 INTP7 R/W 0 22 INTP6 R/W 0 21 INTP5 R/W 0 20 INTP4 R/W 0 19 INTP3 R/W 0 18 INTP2 R/W 0 17 INTP1 R/W 0 16 INTP0 R/W 0
DF Address: 0x2A
-R W R/W
15 TMODE R/W 0
14 RATE2 R/W 0
13 RATE1 R/W 0
12 RATE0 R/W 0
11 TSYNC R/W 0
10 -R/W 0
9 -R/W 0
8 -R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 LOOP R/W 0
6 RUN R/W 0
5 DDLY5 R/W 0
4 DDLY4 R/W 0
3 DDLY3 R/W 0
2 DDLY2 R/W 0
1 DDLY1 R/W 0
(LSB) 0 DDLY0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 INTP[7:0] Interpolation factor 0xFF: 256 0xFE: 255 ... 0x01: 2 0x00: 1 (use once) 15 TMODE Operational mode 1: Impulse mode 0: Sine Mode 7 LOOP Loopback TBSDATA output to MDATA inputs 1: Enabled 0: Disabled Run Test Bit Stream 1: Enabled 0: Disabled
14:12 RATE[2:0]
TBSDATA and TBSCLK output rate. 111: 2.048 MHz 110: 1.024 MHz 101: 512 kHz 100: 256 kHz 011: 128 kHz 010: 64 kHz 001: 32 kHz 000: 4 kHz Synchronization 1: Sync enabled 0: No sync
6
RUN
11
TSYNC
5:0
DDLY[5:0]
TBSDATA output delay 0x3F: 63 bits 0x3E: 62 bits ... 0x01: 1 bit 0x00: 0 bits ( no delay)
10:8
--
reserved
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20.2.8 TBSGAIN : 0x2B
Figure 50. Test Bit Stream Gain Register TBSGAIN
(MSB) 23 TGAIN23 R/W 0 22 TGAIN22 R/W 0 21 TGAIN21 R/W 0 20 TGAIN20 R/W 0 19 TGAIN19 R/W 0 18 TGAIN18 R/W 0 17 TGAIN17 R/W 0 16 TGAIN16 R/W 0
DF Address: 0x2B
-R W R/W
15 TGAIN15 R/W 0
14 TGAIN14 R/W 0
13 TGAIN13 R/W 0
12 TGAIN12 R/W 0
11 TGAIN11 R/W 0
10 TGAIN10 R/W 0
9 TGAIN9 R/W 0
8 TGAIN8 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 TGAIN7 R/W 0
6 TGAIN6 R/W 0
5 TGAIN5 R/W 0
4 TGAIN4 R/W 0
3 TGAIN3 R/W 0
2 TGAIN2 R/W 0
1 TGAIN1 R/W 0
(LSB) 0 TGAIN0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 TGAIN[23:16] Test Bit Stream Gain 15:8 Upper Byte TGAIN[15:8] Test Bit Stream Gain Middle Byte 15:8 TGAIN[7:0] Test Bit Stream Gain Lower Byte
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CS5378
20.2.9 SYSTEM1, SYSTEM2 : 0x2C, 0x2D
Figure 51. User Defined System Register SYSTEM1
(MSB) 23 SYS23 R/W 0 22 SYS22 R/W 0 21 SYS21 R/W 0 20 SYS20 R/W 0 19 SYS19 R/W 0 18 SYS18 R/W 0 17 SYS17 R/W 0 16 SYS16 R/W 0
DF Address: 0x2C
-R W R/W
15 SYS15 R/W 0
14 SYS14 R/W 0
13 SYS13 R/W 0
12 SYS12 R/W 0
11 SYS11 R/W 0
10 SYS10 R/W 0
9 SYS9 R/W 0
8 SYS8 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 SYS7 R/W 0
6 SYS6 R/W 0
5 SYS5 R/W 0
4 SYS4 R/W 0
3 SYS3 R/W 0
2 SYS2 R/W 0
1 SYS1 R/W 0
(LSB) 0 SYS0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:16 SYS[23:16] System Register Upper Byte 15:8 SYS[15:8] System Register Middle Byte 15:8 SYS[7:0] System Register Lower Byte
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CS5378
20.2.10 VERSION : 0x2E
Figure 52. Hardware Version ID Register VERSION
(MSB) 23 TYPE7 R/W 0 22 TYPE6 R/W 1 21 TYPE5 R/W 1 20 TYPE4 R/W 1 19 TYPE3 R/W 1 18 TYPE2 R/W 0 17 TYPE1 R/W 0 16 TYPE0 R/W 0
DF Address: 0x2E
-R W R/W
15 HW7 R/W 0
14 HW6 R/W 0
13 HW5 R/W 0
12 HW4 R/W 0
11 HW3 R/W 0
10 HW2 R/W 0
9 HW1 R/W 0
8 HW0 R/W 1
Not defined; read as 0 Readable Writable Readable and Writable
7 ROM7 R/W 0
6 ROM6 R/W 0
5 ROM5 R/W 0
4 ROM4 R/W 0
3 ROM3 R/W 0
2 ROM2 R/W 0
1 ROM1 R/W 0
(LSB) 0 ROM0 R/W 1
Bits in bottom rows are reset condition
Bit definitions:
23:16 TYPE [7:0] Chip Type 78 - CS5378 15:8 HW [7:0] Hardware Revision 01 - CS5378 Rev A 7:4 ROM [7:0] ROM Version 01 - Ver 1.0
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CS5378
20.2.11 SELFTEST : 0x2F
Figure 53. Self Test Result Register SELFTEST
(MSB) 23 -R/W 0 22 -R/W 0 21 -R/W 0 20 -R/W 0 19 EU3 R/W 1 18 EU2 R/W 0 17 EU1 R/W 1 16 EU0 R/W 0
DF Address: 0x2F
-R W R/W
15 DRAM3 R/W 1
14 DRAM2 R/W 0
13 DRAM1 R/W 1
12 DRAM0 R/W 0
11 PRAM3 R/W 1
10 PRAM2 R/W 0
9 PRAM1 R/W 1
8 PRAM0 R/W 0
Not defined; read as 0 Readable Writable Readable and Writable
7 DROM3 R/W 1
6 DROM2 R/W 0
5 DROM1 R/W 1
4 DROM0 R/W 0
3 PROM3 R/W 1
2 PROM2 R/W 0
1 PROM1 R/W 1
(LSB) 0 PROM0 R/W 0
Bits in bottom rows are reset condition
Bit definitions:
23:20 -reserved 15:12 DRAM [3:0] Data RAM Test `A': Pass `F': Fail Program RAM Test `A': Pass `F': Fail 7:4 DROM [3:0] Data ROM Test `A': Pass `F': Fail Program ROM Test `A': Pass `F': Fail
19:16 EU [3:0]
Execution Unit Test `A': Pass `F': Fail
11:8
PRAM [3:0]
3:0
PROM [3:0]
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CS5378
21. PIN DESCRIPTION
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4:PLL0 GPIO5:PLL1 GPIO6:PLL2 TBSDATA VDDPAD GNDPAD MCLK MSYNC MDATA MFLAG
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GPIO7:BOOT SS:EECS MOSI MISO SCK DRDY GNDCORE VDDCORE TIMEB SYNC RESET CLK GNDPLL VDDPLL
Figure 54. CS5378 Pin Assignments
Pin Name
GPIO[0:3] GPIO[4:6]:PLL[0:2]
Pin Number
1, 2, 3, 4 5, 6, 7
Pin Type
General Purpose Input / Output Input / Output Input / Output
Pin Description
General Purpose I/O. General Purpose I/O with PLL mode select. GPIO pins have weak (~100 k) internal pullups. PLL mode selection latched immediately after reset. PLL[2:0] 111 110 101 100 011 010 001 000 Reset Mode 32.768 MHz clock input (PLL bypass). 1.024 MHz clock input. 2.048 MHz clock input. 4.096 MHz clock input. 32.768 MHz clock input (PLL bypass). 1.024 MHz manchester input. 2.048 MHz manchester input. 4.096 MHz manchester input.
GPIO7:BOOT
28
Input / Output
General Purpose I/O with boot mode select. GPIO pins have weak (~100 k) internal pullups. Boot mode selection latched immediately after reset. BOOT 1 0 Reset Mode EEPROM boot Microcontroller boot
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CS5378
Pin Name
TBSDATA MCLK MSYNC MDATA MFLAG CLK RESET SYNC TIMEB DRDY SCK MISO MOSI SS:EECS VDDPAD, GNDPAD VDDPLL, GNDPLL VDDCORE, GNDCORE
Pin Number
8 11 12 13 14 17 18 19 20 23 24 25 26 27 9, 10 15, 16 21, 22
Pin Type
Test Bit Stream Output Modulator Interface Output Output Input Input Telemetry Interface Input Input Input Input Serial Interface Output Input / Output Input / Output Input / Output Input Supply Supply Supply Power Supplies
Pin Description
Test bit stream data output. Modulator clock output. Modulator sync output. Modulator data input. Modulator flag input. Clock input. Reset, active low. Sync input. Time break input. Data ready, active low. Serial clock. Serial data, master in / slave out. Serial data, master out / slave in. Slave select with EEPROM chip select, active low. Pin power supply. PLL power supply. Logic core power supply.
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CS5378
22.PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E b2 SIDE VIEW
123
L
e
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4
MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4
NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150 Controlling Dimension is Millimeters
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CS5378
23.ORDERING INFORMATION
Model Temperature Package
CS5378-IS CS5378-ISZ Lead Free
-40 to +85 C
28-pin SSOP
24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C 260 C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days
CS5378-IS CS5378-ISZ Lead Free
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
25.REVISION HISTORY
Revision Date Changes
PP1 F1
FEB 2004 OCT 2005
Initial "Preliminary Product" release. Added lead-free device ordering information. Added MSL data.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.
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