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Approved Product
CY25568
Spread Spectrum Clock Generator
FEATURES
* * * * * * * 4 to 32 MHz Input Frequency Range 4 to 128 MHz Output Frequency Range Accepts Clock, Crystal and Resonator Inputs 1x, 2x and 4x Frequency Multiplication Non-modulated Reference Frequency Output Center and Down Spread Modulation Low Power Dissipation 3.3V = 52 mW-typ @ 6MHz 3.3V = 60 mW-typ @ 12MHz 3.3V = 72 mW-typ @ 24MHz Power Down Mode Low Cycle-to Cycle Jitter 8MHz = 195 ps-typ 16MHz = 175 ps-typ 32MHz = 100 ps-typ Available in 16-pin (150 mil.) SOIC package
APPLICATIONS
* * * * * * * * * * Printers and MFPs LCD Panels and Monitors Digital Copiers PDAs Automotive CD-ROM, VCD and DVD Networking, LAN/WAN Scanners Modems Embedded Digital Systems
*
*
BENEFITS * * * Peak EMI reduction by 8 to 16dB Fast Time to Market Cost Reduction
*
GENERAL DESCRIPTION
The Cypress CY25568 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today's high-speed digital electronic systems. The CY25568 uses a Cypress proprietary Phase-Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the digital clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The CY25568 input frequency range is 4 to 32 MHz and accepts clock, crystal and ceramic resonator inputs. The output clocks can be programmed to produce 1x, 2x and 4x multiplication of the input frequency with Spread Spectrum. A separate non-modulated reference clock is also provided. The use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and allows the user to generate up to 128 MHz Spread Spectrum Clock (SSC) by using only first order crystals. This will reduce the cost while improving the system clock accuracy, performance and complexity Center Spread or Down Spread frequency modulation can be selected by the user based on 4 discrete values of Spread % for each Spread Mode with the option of a Non-Spread mode for system test and verification purposes. The CY25568 is available in a 16 pin SOIC (150-mil.) package with a commercial operating temperature range of 0 to 70C. Contact Cypress for availability of -25 to +85C Industrial Temperature Range Operation. Refer to CY25811/12/14 products for 8-pin SOIC package versions of the CY25568.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *B
12/21/02 Page 1 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
BLOCK DIAGRAM
300K
7
REFOUT
XIN
1
8pF
REFERENCE DIVIDER
PD and CP
LF
XOUT
16
8pF
MODULATION CONTROL
VDD VDD VSS VSS
13
VCO COUNTER
VCO
6 12
SSCLK1 SSCLK2 SSCLK3
3 2
INPUT DECODER LOGIC
11 4 5 15 14 10
DIVIDER and MUX
9 8
FRSEL
S1 SO D1 DO PD#
Figure 1. Block Diagram
ORDERING INFORMATION
Operating Temperature Range
0 to 70C
Part No.
CY25568SC
Package
16 Pin SOIC
Table 1. Ordering Information
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 2 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
PIN CONFIGURATION
XIN/CLKIN VSS VSS S1 S0 SSCLK1 REFOUT SSCK3
1 2 3 4 5 6 7 8
16 15 14
XOUT D1 D0 VDD VDD FRSEL PD# SSCLK2
CY25568
13 12 11 10 9
Figure 2. 16 Pin SOIC Pin Assignment
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Xin/CLK VSS VSS S1 S0 SSCLK1 REFOUT SSCLK3 SSCLK2 PD# FRSEL VDD VDD D0 D1 XOUT
Description
Clock, crystal or ceramic resonator input pin. Power Supply Ground. Power Supply Ground. Digital Spread % control pin. 3-Level input (H-M-L). Default=M. Digital Spread % control pin. 3-Level input (H-M-L). Default=M. Output Clock. Refer to Table-6 for frequency programmability. Reference Clock Output. The same frequency as Xin/CLK input. Output Clock. Refer to Table-6 for frequency programmability. Output Clock. Refer to Table-6 for frequency programmability. Power Down Control. Internally Pulled to VDD, Default=High. Input Frequency Range Selection digital control input. 3-Level input (H-M-L). Default=M. Positive Power Supply. Positive Power Supply. 3-Level (H-M-L) Digital output clock scaling control. Refer to Table-6. Default=M. 3-Level (H-M-L) Digital output clock scaling control. Refer to Table-6. Default=M. Crystal or ceramic resonator output pin. Table 2. Pin Description
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 3 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
ABSOLUTE MAXIMUM RATINGS1:
Supply Voltage (VDD): +5.5V Operating Temperature: 0 to 70C Input Voltage Relative to VDD: VDD+0.3V Storage Temperature: -65 to +150C Input Voltage Relative to VSS: VSS-0.3V Note: Operation at any Absolute Maximum Rating is not implied. DC ELECTRICAL CHARACTERISTICS: Test Conditions: VDD=3.3V, T=25, unless otherwise noted.
Symbol VDD VINH VINM VINL VINH1 VINL1 VOH1 VOH2 VOL1 VOL2 Cin1 Cin2 IDD1 IDD2 IDD3 Parameter Power Supply Range Input High Voltage Input Middle Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current Min. 2.90 0.85VDD 0.40VDD 0.0 2.0 2.4 2.0 6.0 3.5 Typ. 3.3 VDD 0.50VDD 0.0 7.5 4.5 13.0 28.0 300 Max. 3.60 VDD 0.60VDD 0.15VDD 0.8 0.4 1.2 9.0 6.0 16.0 32.0 400 Unit V V V V V V V V V V pF pF mA mA $ Conditions S0,S1,D0,D1 and FRSEL Inputs S0,S1,D0,D1 and FRSEL Inputs S0,S1,D0,D1 and FRSEL Inputs PD# Input Only PD# Input Only IOH = 4 ma, all Output Clocks IOH = 6 ma, all Output Clocks IOL = 4 ma, all Output Clocks IOL = 10 ma, all Output Clocks Xin (Pin 1) and Xout (Pin 16) All Digital Inputs Fin=4MHz, no load (refer to Figure 4C) Fin=32MHz, no load (refer to Figure 4C) PD#=GND
Table 3 TIMING ELECTRICAL CHARACTERISTICS: Test Conditions: VDD=3.3V, T=25C, CL=15pF. Rise/Fall time @ 0.4 and 2.4V, duty cycle at 1.5 V
Symbol ICLKFR trise1 tfall1 trise2 tfall2 trise3 tfall3 CDCin Parameter Input Frequency Range Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Input Clock Duty Cycle Min. 4 2.4 2.4 1.2 1.2 2.4 2.4 20 3.2 3.2 1.6 1.6 3.2 3.2 50 Typ. Max. 32 4.0 4.0 2.0 2.0 4.0 4.0 80 Unit Conditions MHz Clock, Crystal or Ceramic Resonator Input ns ns ns ns ns ns % SSCLK1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL=1 or 0 SSCLK1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL=1 or 0 SSCLK2, and 3, only when 4x scaling is selected and FRSEL=M SSCLK2, and 3, only when 4x scaling is selected and FRSEL=M REFOUT only REFOUT only XIN/CLK (Pin 1)
1
Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 4 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
CDCout CCJ1 CCJ2 CCJ3 Output Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter 45 50 195 170 100 55 260 225 150 % ps ps ps SSCLK1,2 and 3 Fin=8 MHz (refer to Figure 4A) Fin=16 MHz (refer to Figure 4A) Fin=32 MHz (refer to Figure 4A)
Table 4
INPUT FREQUENCY RANGE AND SELECTION
The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table 5. FRSEL 0 1 M INPUT FREQUENCY RANGE 4.0 to 8.0 MHz 8.0 to 16.0 MHz 16.0 to 32.0 MHz Table 5 - Input Frequency Selection OUTPUT CLOCKS The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of applications. Each clock output is described below in detail. REFOUT REFOUT is a 3.3-volt CMOS level non-modulated copy of the clock at XIN/CLKIN. SSCLK1, 2 and 3 SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each clock can drive separate nets with a capacitive load of up to 20 pF. The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table 6.
D0 0 0 0 M M M 1 1 1
D1 0 M 1 0 M 1 0 M 1
REFOUT REF REF REF REF REF REF REF REF REF
SSCLK1 REF 1x REF REF REF REF REF 1x 1x
SSCLK2 1x 2x 2x 1x REF 2x 4x 2x 2x
SSCLK3 1x 2x 2x 2x REF 4x 4x 4x 4x
REF is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. Table 6 - Output Clocks Function Selection
Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07111 Rev. *A 06/21/01 Page 5 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
SPREAD % SELECTION
The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread % are selected by using 3-Level S0 and S1 digital inputs and are given in Table 7.
XIN (MHz)
FRSEL
S1=0 S0=0
CENTER (%)
S1=0 S0=M
CENTER (%)
S1=0 S0=1
CENTER (%)
S1=M S0=0
CENTER (%)
S1=1 S0=1
DOWN (%)
S1=1 S0=0
DOWN (%)
S1=M S0=1
DOWN (%)
S1=1 S0=M
DOWN (%)
S1=M S0=M
NO SPREAD
4-5 5-6 6-7 7-8 8-10 10-12 12-14 14-16 16-20 20-24 24-28 28-32
0 0 0 0 1 1 1 1 M M M M
+/-1.4 +/-1.3 +/-1.2 +/-1.1 +/-1.4 +/-1.3 +/-1.2 +/-1.1 +/-1.4 +/-1.3 +/-1.2 +/-1.1
+/-1.2 +/-1.1 +/-0.9 +/-0.9 +/-1.2 +/-1.1 +/-0.9 +/-0.9 +/-1.2 +/-1.1 +/-0.9 +/-0.9
+/-0.6 +/-0.5 +/-0.5 +/-0.4 +/-0.6 +/-0.5 +/-0.5 +/-0.4 +/-0.6 +/-0.5 +/-0.5 +/-0.4
+/-0.5 +/-0.4 +/-0.4 +/-0.3 +/-0.5 +/-0.4 +/-0.4 +/-0.3 +/-0.5 +/-0.4 +/-0.4 +/-0.3
-3.0 -2.7 -2.5 -2.3 -3.0 -2.7 -2.5 -2.3 -3.0 -2.7 -2.5 -2.3
-2.2 -1.9 -1.8 -1.7 -2.2 -1.9 -1.8 -1.7 -2.2 -1.9 -1.8 -1.7
-1.9 -1.7 -1.5 -1.4 -1.9 -1.7 -1.5 -1.4 -1.9 -1.7 -1.5 -1.4
-0.7 -0.6 -0.6 -0.5 -0.7 -0.6 -0.6 -0.5 -0.7 -0.6 -0.6 -0.5
0 0 0 0 0 0 0 0 0 0 0 0
Table 7 - Spread % Selection 3-LEVEL DIGITAL INPUTS
LOGIC LOW (0)
LOGIC MIDDLE (M)
LOGIC HIGH (H)
VDD
DO, D1, S0, S1 and FRSEL to GND
D0, D1, S0, S1 and FRSEL UNCONNECTED
D0, D1, S0, S1 and FRSEL to VDD
GND
Figure 3. 3-Level Logic
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 6 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
S0, S1, D0, D1 and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High "1", Low "0" and Middle "M". With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0, S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL. S0, S1, D0, D1 and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to implement the 3-Level logic levels as shown below: Logic State "0" = 3-Level logic pin connected to GND. Logic State "M" = 3-Level logic pin left floating (no connection). Logic State "1" = 3-Level logic pin connected to VDD. Figure 3 illustrates how to implement 3-Level Logic. POWER DOWN (PD#) CY25568 includes a Power Down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to VDD (HIGH). Connect this pin to GND if power is to be turned off.
MODULATION RATE Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency or fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the Modulation Rate. In the case of CY25568, the (Spread Spectrum) Modulation Rate is given by the following formula: fmod = fin/DR Where; fmod is the Modulation Rate, fin is the Input Frequency and DR is the Divider Ratio as given in Table 8. Notice that Input Frequency Range is set by FRSEL. FRSEL 0 1 M INPUT FREQUENCY RANGE (MHz) 4 to 8 8 to 16 16 to 32 Table 8 DIVIDER RATIO (DR) 128 256 512
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 7 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
CHARACTERISTIC CURVES The following curves demonstrate the characteristic behavior of the CY25568 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in tables 3 and 4.
600 500
2.75
6.0 MHz 32.0 MHz
2.5
400
CCJ (ps)
BW %
300 200 100
2.25
2
1.75
0 4 8 12 16 20 24 28 32
-40
Input Frequency (MHz)
-25
-10
5
20
35
50
65
80
95
110
125
Temp (C)
Figure 4A. Jitter vs. Input Frequency (No Load)
Figure 4B Bandwidth % vs. Temperature
30 28 26 24
IDD (mA)
FRSEL = M 16 - 32 MHz
3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8
7.5 8
22 20 18 16 14 12 10 4 4.5 5 5.5
FRSEL = 1 8 - 16 MHz
BW (%)
4.0 MHz
8.0 MHz
FRSEL = 0 4 - 8 MHz
6
6.5
7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Frequency (MHz) no load, normalized to FRSEL = 0, (4 - 8 MHz).
VDD (volts)
Figure 4C. IDD vs. Frequency (FRSEL = 0, 1, M)
Figure 4D. Bandwidth % vs. VDD
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 8 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
SSCG PROFILES The CY25568 uses a non-linear frequency profile as shown in Figure 5. The use of Cypress proprietary "optimized" frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems.
Xin = 6.0 MHz S1, S0 = 0 FRSEL = 0
SSCLK1 = 6.0 MHz D1, D0 = 1
Xin = 24.0 MHz S1, S0 = 0 FRSEL = M
SSCLK1 = 24.0 MHz D1, D0 = 1
Xin = 12.0 MHz S1, S0 = 0 FRSEL = 1
SSCLK1 = 48.0 MHz D1, D0 = 1
Xin = 24.0 MHz S1, S0 = 0 FRSEL = M
SSCLK1 = 96.0 MHz D1, D0 = 1
Figure 5. Spread Spectrum Profiles (Frequency versus Time)
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 9 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
APPLICATION SCHEMATIC
VDD C1 0.1 uF 12 27 pF. C2 1 Y1 16 MHz C3 16 XOUT REFOUT 7 XIN/CLKIN VDD 13 VDD
27 pF.
CY25568SC
VDD 10 PD# SSCLK3 8
11 4 5 15 VDD 14
FRSEL S1 S0
SSCLK2
9
SSCLK1 D1 D0 VSS 2 VSS 3
6
Figure 6. Application Schematic
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 10 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
16 PIN SOIC PACKAGE DRAWING AND OUTLINE
16 Pin SOIC Outline Dimensions (150 mil)
INCHES SYMBOL A A1 C L E H A2 B C D E D A2 A1 B e A
a
MILLIMETERS MAX 0.069 0.010 0.059 0.020 0.010 0.394 0.157 MIN 1.35 0.10 1.20 0.33 0.19 9.80 3.80 NOM 1.27 BSC 0.244 0.050 8 5.80 0.40 0 6.20 1.27 8 MAX 1.75 0.25 1.50 0.51 0.25 10.00 4.00
MIN 0.053 0.004 0.047 0.013 0.007 0.366 0.150
NOM 0.050 BSC
e H L a 0.228 0.016 0
-
Table 9. SOIC16 Outline Figure 7. SOIC16 Drawing
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01 Page 11 of 12
Approved Product
CY25568
Spread Spectrum Clock Generator
Document Title: CY25568 Spread Spectrum Clock Generator Document Number: 38-07111
Rev. ECN No. ** 107515 *A 108182 *B 122682
Issue Date 06/14/01 07/03/01 12/21/02
Orig. of Change NDP NDP RBI
Description of Change Convert from IMI to Cypress Delete "Junction Temp" in Absolute maximum Ratings (page 4) Added power up requirements to Absolute Maximum Ratings information.
Cypress Semiconductor Corporation http://www.cypress.com
Document#: 38-07111 Rev. *B
12/21/02 Page 12 of 12

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