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DS3100DK Stratum 3/E3 Timing Card IC Demo Kit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3100DK is an easy-to-use demo and evaluation kit for the DS3100 Stratum 3/3E timing card IC. A surface-mounted DS3100 and careful layout provide maximum signal integrity. An on-board Dallas 8051-compatible microcontroller and included software give point-and-click access to configuration and status registers from a personal computer. LEDs on the board indicate interrupt, power-supply function, and GPIO status. The board provides BNC and bantam connectors for the composite clock and BITS interfaces. Single-ended and LVDS clocks are accessed via SMB connectors. All LEDs and connectors are clearly labeled with silkscreening to identify associated signals.
FEATURES
Soldered DS3100 for Best Signal Integrity SMB Connectors, BNC, Bantam, Transformers, and Termination Ease Connectivity Careful Layout for Analog Signal Paths On-Board Stratum 3 Oscillator with Footprints for Stratum 3E Oscillators DS3100 Configured for CPU Bus Operation for Complete Control Over the Device On-Board Dallas Microcontroller and Included Software Provide Point-and-Click Access to the DS3100 Register Set LEDs for Interrupt, Power Supplies, and GPIO Included International Power Supply Banana Jack VDD and GND Connectors Support Use of Lab Power Supplies Easy-to-Read Silkscreen Labels Identify the Signals Associated with All Connectors, Jumpers and LEDs Header Provided for Master/Slave Connection to a Second DS3100DK Software Provides GUI Fields for Most Commonly Used Features Plus Full Read/Write Access to the Entire Register Set Software Support for Creating and Running Configuration Scripts Saves Time During Evaluation
DEMO KIT CONTENTS
DS3100DK PCB CD_ROM Includes: DS3100 Software DS3100 Initialization File DS3100DK Data Sheet DS3100 Data Sheet/Errata Sheet
MINIMUM SYSTEM REQUIREMENTS
PC Running Windows(R) XP or Windows 2000 Display with 1024 x 768 Resolution or Higher Available Serial (COM) Port DB-9 Serial Cable
ORDERING INFORMATION
PART DS3100DK DESCRIPTION Demo kit for DS3100
Windows is a registered trademark of Microsoft Corp.
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REV: 110206
DS3100DK
TABLE OF CONTENTS
1.
1.1 1.2 1.3 1.4 1.5 1.6
BOARD FLOORPLAN........................................................................................................4
INPUT AND OUTPUT CLOCKS............................................................................................................5 JUMPERS, HEADERS, AND SWITCH SETTINGS ..................................................................................5 COMPOSITE CLOCK INTERFACE .......................................................................................................5 BITS INTERFACES ...........................................................................................................................5 MICROCONTROLLER ........................................................................................................................5 POWER-SUPPLY CONNECTORS........................................................................................................5
2. 3.
3.1
BASIC HARDWARE SETUP..............................................................................................6 INSTALLING AND RUNNING THE SOFTWARE...............................................................6
COMMAND LINE OPTIONS ................................................................................................................6
4.
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
OVERVIEW OF THE SOFTWARE INTERFACE................................................................7
GLOBAL CONFIGURATION ................................................................................................................7 INPUT CLOCK MONITOR, DIVIDER, AND SELECTOR ...........................................................................7 T0 DPLL ........................................................................................................................................ 8 T4 DPLL ........................................................................................................................................ 9 T0 APLL....................................................................................................................................... 10 T4 APLL....................................................................................................................................... 10 OUTPUT CLOCKS...........................................................................................................................11 DPLL FREQUENCY LIMITS, PHASE DETECTORS, DPLL LOCK CRITERIA..........................................12 BITS RECEIVERS AND BITS TRANSMITTERS ..................................................................................13
Note About Working with the BITS Receivers and Transmitters ......................................................... 13
4.9.1
4.10 4.11 4.12 4.13
4.13.1 4.13.2
COMPOSITE CLOCK RECEIVERS .................................................................................................14 REFCLK CALIBRATION ..............................................................................................................14 REGISTER VIEW WINDOW...........................................................................................................14 CONFIGURATION SCRIPTS AND LOG FILE ....................................................................................15
Configuration Log File .......................................................................................................................... 15 Configuration Scripts............................................................................................................................ 15
5.
5.1 5.2 5.3
ADDITIONAL INFORMATION AND RESOURCES .........................................................15
DS3100 INFORMATION..................................................................................................................15 DS3100DK INFORMATION.............................................................................................................15 TECHNICAL SUPPORT ....................................................................................................................15
6. 7. 8. 9.
APPENDIX 1: HARDWARE COMPONENTS...................................................................16 APPENDIX 2: BITS MODE WRITE SEQUENCES...........................................................19 SCHEMATICS ..................................................................................................................19 DOCUMENT REVISION HISTORY ..................................................................................19
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LIST OF FIGURES
Figure 1-1. Board Floorplan......................................................................................................................................... 4
LIST OF TABLES
Table 4-1. Mapping Between Input Clock Software Fields and DS3100 Register Fields ........................................... 7 Table 4-2. Mapping Between T0 DPLL Software Fields and DS3100 Register Fields ............................................... 8 Table 4-3. Mapping Between T4 DPLL Software Fields and DS3100 Register Fields ............................................... 9 Table 4-4. Mapping Between T0 APLL Software Fields and DS3100 Register Fields ............................................. 10 Table 4-5. Mapping Between T4 APLL Software Fields and DS3100 Register Fields ............................................. 10 Table 4-6. Mapping Between Output Clock Software Fields and DS3100 Register Fields ...................................... 11 Table 4-7. Mapping Between DPLL Software Fields and DS3100 Register Fields .................................................. 12 Table 4-8. Mapping Between BITS Software Fields and DS3100 Register Fields ................................................... 13 Table 4-9. Mapping Between CC Software Fields and DS3100 Register Fields ...................................................... 14 Table 4-10. Mapping Between REFCLK Software Fields and DS3100 Register Fields ........................................... 14
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1.
BOARD FLOORPLAN
Figure 1-1 shows the floorplan of the DS3100DK. The DS3100 is in the center of the board, input clock SMB connectors are along the top edge of the board, and output clock connectors are on the bottom edge. Between the input clock connectors and the DS3100, land patterns are provided for several different types of local oscillators, ranging from tiny, inexpensive TCXOs to larger, high-performance OCXOs. The right edge contains, from top to bottom, power supply connectors, DC-DC converters and power-indicator LEDs, reset push-button, serial connector and USB connector. An on-board DS87C520 microcontroller is located near the USB connector. The left edge of the board is occupied by connectors and transformers for the DS3100's built-in BITS (DS1/E1/2048kHz) and composite clock (64kHz) receivers and transmitters. Between the BITS and composite clock connectors are a JTAG header and three switches to control the DS3100's MASTSLV, SONSDH, and SRCSW pins. See APPENDIX 1: HARDWARE COMPONENTS for a complete component list. Complete board schematics follow Appendix 2.
Figure 1-1. Board Floorplan
Power Option 5V Banana Jack
LVDS Input Clocks
Single-ended Input Clocks
GND Banana Jack
Oscillator Circuitry BITS Interfaces
DS3100 GPIO Circuitry
Reset
Power Supply Circuitry RS232 9-Pin Connector
JTAG Header
Switches
USB Connector
Microprocessor
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Composite Clock Input Composite Clock Output
LVDS Output Clocks
Single-ended Output Clocks
M\S Hdr
DS3100DK
1.1
Input and Output Clocks
There are 13 SMB connectors at the top of the board labeled IC1-IC4, IC7-IC14, and SYNC2K that provide a single-ended clock input to the DS3100. All single-ended clock inputs are connected to the DS3100 with a 50 characteristic impedance trace and terminated with 50 at the device. Four additional SMB connectors labeled IC5P, IC5N, IC6P, and IC6N provide differential clock inputs to the DS3100. These differential inputs have 50 trace impedance and 50 termination at the device (i.e., 100 differential). On the other end of the PCB are eight SMB clock output connectors labeled OC1-OC5 and OC9, OC10, and OC11. All single-ended clock outputs are buffered at the DS3100 and connected to the SMB connector via a 50 characteristic impedance trace. Four additional SMB connectors labeled OC6P, OC6N, OC7P, and OC7N provide connections to the differential outputs from the DS3100.
1.2
Jumpers, Headers, and Switch Settings
Jumpers JMP1 to JMP4 (upper right of board) provide input settings to the four DS3100 GPIO pins. If a jumper is installed the corresponding GPIO input is high. With no jumper the GPIO pin defaults low. LEDs DS5-DS8 indicate the logic level of the GPIO pins (LED lit means GPIO pin is high). Switches SW7 to SW9 set the SONSDH, SRCSW and MASTSLV pins, respectively, high or low as indicated by the silkscreen. Headers J1 and J2 provide access to BITS1 and BITS2 framer signals, respectively. Header J51 provides access to the JTAG port of the DS3100. Header J15 provides interface to a master or slave board depending on position of switch SW6.
1.3
Composite Clock Interface
Bantam jacks J89 and J90 provide access to composite clock inputs IC1A and IC2A through a 2:1 transformer. Jumpers JMP7 and JMP6 configure termination for IC1A and IC2A respectively. Silkscreen text indicates which jumper is necessary to set the interface at 110, 120, or 133. Bantam jack J117 provides an interface through a 1:1 transformer to the OC8 composite clock output. Jumpers JMP8, JMP9, and JMP10 provide different attenuation configurations that are represented in silkscreen (Rs = 91 with no jumper installed). See the schematics for additional details on the composite clock termination circuitry.
1.4
BITS Interfaces
The BITS1 DS1/E1 LIU uses bantam connectors J85 and J55 or BNC connectors J83 and J57 for transmit and receive interfaces, respectively. The BITS2 LIU uses bantam connectors J86 and J56 or BNC connectors J84 and J58 for transmit and receive, respectively. There is a dual transformer package for each BITS transceiver (component T1 for BITS1 and T2 for BITS2). See the schematics for additional details on the BITS termination circuitry.
1.5
Microcontroller
The DS87C520 microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware translates memory access requests from the RS-232 serial port or USB port into register accesses on the DS3100. When the microcontroller starts up it turns on DS16 to indicate that the controller is working correctly. A pushbutton switch labeled RESET (SW5) at the right middle of the board resets the microcontroller as well as the DS3100.
1.6
Power-Supply Connectors
The included international power supply can be connected to jack J3 to power the board or a 5V lab power supply can be connected across the red (J13) and black (J19) banana jacks. The 5V input is then regulated to 3.3V and 1.8V and distributed to board components.
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2.
BASIC HARDWARE SETUP
The following steps provide a quick start to using the DS3100DK. 1) Configure the board for serial (RS-232) communication by placing jumpers to connect the left and middle pins of JMP62 and JMP63 (near the serial connector). USB operation is not yet supported. 2) Ensure switch SW6 (near the OC1 and OC2 connectors) is in the "MAS" position. 3) Set switch SW9 (MASTSLV) in the "1" (master) position. 4) Set switch SW8 in "0" (normal operation) position. 5) Set switch SW7 to "1" to have the 1.544/2.048MHz frequency options in the DS3100 default to 1.544MHz. Set SW7 to "0" for 2.048MHz. 6) Connect a standard DB-9 serial cable between the serial port connector on the DS3100DK and an available serial port on the host computer. (Be sure the cable is a standard straight-through cable rather than a null-modem cable. Null-modem cables prevent proper operation.) 7) Attach the appropriate AC power supply prongs to the included international power supply. 8) Plug the power supply into an AC power outlet and connect the DC output of the supply to connector J3 (PWR in Figure 1-1). At this point the power indicator LEDs DS1-DS4 should be lit. Microcontroller status LED DS16 (to the right of the USB connector) should also be lit.
3.
INSTALLING AND RUNNING THE SOFTWARE
At this time the DS3100 demo kit software only runs on Windows 2000 or Windows XP operating systems. To install the demo kit software, run SETUP.EXE from the disk included in the DS3100DK box or from the zip file downloadable on our website at www.maxim-ic.com/DS3100DK. After software installation is complete, set up the hardware as described above and run the software by doubleclicking the DS3100 Demo Kit icon on the Windows desktop or by selecting StartProgramsDallas SemiconductorDS3100 Demo Kit. When the main window appears, select the correct serial port in the box in the lower right corner. When communication has been properly established between the software and the hardware, the ID field in the upper-left corner should indicate 3100 rev x, where x = 0 for a revision A1 device, and x = 1 for a revision A2 device. The demo kit software always starts in demo mode (with the DEMO MODE checkbox in the upper-left corner checked) in case a user wants to look at the software without having the DK hardware connected to the PC. To connect the software with the demo kit hardware, uncheck the DEMO MODE box. The software optionally initializes the DS3100 device and then reads the state of the device to get ready for use.
3.1
Command Line Options
The demo kit software has these command line options: -l -p[port#] specifies an alternate log file sets the serial (COM) port number example: "DS3100DK.exe -l mylog.mfg example: "DS3100DK.exe -p2" sets COM2
To add command line options to a shortcut, such as the DS3100 demo kit shortcut that the installer adds to the desktop, right click on the shortcut and select Properties. In the Shortcut tab, at the end of the text in the Target textbox, add a space followed by the command line option.
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4.
4.1
OVERVIEW OF THE SOFTWARE INTERFACE
Global Configuration
In the upper-left corner of the main window are several global status and configuration fields including the device ID and REV, the status of the MASTSLV pin (MCR3:MASTSLV), the software DEMO MODE check box, and the 1.544MHz vs. 2.048MHz frequency selection bit (MCR3:SONSDH).
4.2
Input Clock Monitor, Divider, and Selector
This box occupying the left-center section of the main window contains the most frequently used configuration and status associated with input clocks IC1-IC14. At the far left, inputs IC1 and IC2 can be configured for either composite clock (on the IC1A and IC2A pins, respectively) or CMOS (on the IC1 and IC2 pins, respectively). Similarly, IC5 and IC6 can be configured for LVDS or PECL operation. Just to the right of the input clock numbers 1-14 are software LEDs that indicate the state of each input as reported by its input monitor. These LEDs are red in the absence of any other condition. When a clock of the correct frequency is applied to an input, the associated LED turns yellow when activity is detected and, about 10 seconds later, it turns green if the input clock frequency is within range. If an input is disqualified by one of the DPLLs because the DPLL could not lock to it, the LED turns magenta. In the middle of the box, the FREQ and LK MODE fields configure the frequency and lock mode (direct-lock, DIVN, or LOCK8K) for each input clock. At the bottom is a field to configure the DIVN divider used for inputs configured for DIVN mode. All the fields in the box containing the PRIORITY fields display information about either the T0 DPLL or the T4 DPLL, depending on which of two radio buttons is selected at the bottom of the box. The PRIORITY fields configure the input clock priorities for the selected DPLL. The SEL REF field shows the selected reference for the DPLL, while the REF 1, REF 2, and REF 3 fields display the three highest priority valid inputs for the DPLL. The FREQ and PHASE fields show the real-time frequency and phase reported by the DPLL. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields.
Table 4-1. Mapping Between Input Clock Software Fields and DS3100 Register Fields
SOFTWARE FIELD IC1 Signal Format (CMOS or CC) IC2 Signal Format (CMOS or CC) IC5 Signal Format (LVDS or PECL) IC6 Signal Format (LVDS or PECL) DS3100 REGISTER FIELDS MCR5:IC1SF MCR5:IC2SF MCR5:IC5SF MCR5:IC6SF ISR1-ISR7 registers LED red when ACT = 1, HARD = 1 LED yellow when ACT = 0, HARD = 1 LED green when ACT = 0, HARD = 0, LOCK = 0 LED magenta when ACT = 0, HARD = 0, LOCK = 1 ICR1-ICR14, FREQ[3:0] ICR1-ICR14, LOCK8K, and DIVN IPR1-IPR7 PTAB1:SELREF PTAB1:REF1 PTAB2:REF2 PTAB3:REF3 FREQ1, FREQ2 and FREQ3 registers concatenated PHASE1 and PHASE2 register concatenated
Input Clock Status LEDs
FREQ LK MODE PRIORITY SEL REF REF 1 REF 2 REF 3 FREQ (ppm) PHASE (deg)
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4.3
T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE field. The STATE CHG, SRFAIL and PHMON fields are buttons that represent latched status bits in the device. When the button is raised in the middle, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit. STATE CHG indicates the state of the T0 DPLL has changed since the last time the button was pressed. SRFAIL indicates the selected reference has failed since the last time the button was pressed. PHMON indicates the phase monitor limit (set by PMLIM) has been exceeded. The state of the T0 DPLL can be forced using the combo box to the left of the STATE field, and the selected reference can be forced using the CLK SEL field. Below the CLK SEL field is a field that configures the T0 DPLL for revertive or nonrevertive input reference switching. The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3100 T0 DPLL). The acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0 DPLL's selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window), the SOFTLIM LED turns red. The PALARM status LED and the PHASE MONITOR and BUILDOUT fields are advanced topics. See Table 4-2 and the DS3100 data sheet for more details. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields.
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3100 Register Fields
SOFTWARE FIELD STATE combo box STATE status box CLK SEL Revertive/Nonrevertive FREQ ABW LBW DAMP STATE CHG SRFAIL PHMON PALARM SOFTLIM AUTOBW LIMINT PMLIM PMEN PMPBEN PBOEN PBOFRZ RECAL MANUAL PBO DS3100 REGISTER FIELDS MCR1:T0STATE OPSTATE:T0STATE MCR2:T0FORCE MCR3:REVERT Fixed by T0 DPLL architecture T0ABW T0LBW T0CR2:DAMP MSR2:STATE MSR2:SRFAIL MSR3:PHMON TEST1:PALARM OPSTATE:T0SOFT MCR9:AUTOBW MCR9:LIMINT PHMON:PMLIM PHMON:PMEN PHMON:PMPBEN MCR10:PBOEN MCR10:PBOFRZ FSCR3:RECAL OFFSET1 and OFFSET2
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4.4
T4 DPLL
The state of the T4 DPLL (locked or not locked) is shown in the STATE field. The LOCK and NO INPUT fields are buttons that represent latched status bits in the device. When the button is raised in the middle, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit. LOCK indicates the state of the T4 DPLL has changed since the last time the button was pressed. NO INPUT means the T4 DPLL has no valid inputs available. The selected reference for the T4 DPLL can be forced using the CLK SEL field. The frequency of the T4 DPLL is displayed in the FREQ field. When the FREQ field is changed, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all of the T4 options in the OC1-OC7 output clock combo boxes automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. The bandwidth of the T4 DPLL is set by the BW field, while the damping factor is set by the DAMP field. If the frequency of the T4 DPLL's selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of the window), the SOFTLIM LED turns red. Digital feedback (vs. analog feedback through the T4 APLL) can be selected using the DIGFB checkbox. The LKT4T0 and T4MT0 fields are advanced topics. See Table 4-3 and the DS3100 data sheet for more details. In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields.
Table 4-3. Mapping Between T4 DPLL Software Fields and DS3100 Register Fields
SOFTWARE FIELD STATE CLK SEL FREQ BW DAMP LOCK NO INPUT SOFTLIM DIGFB LKT4T0 T4MT0 DS3100 REGISTER FIELDS OPSTATE:T4LOCK MCR4:T4FORCE T4CR1:T4FREQ T4BW T4CR2:DAMP MSR3:T4LOCK MSR3:T4NOIN OPSTATE:T4SOFT MCR4:T4DFB MCR4:LKT4T0 T0CR1:T4MT0
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4.5
T0 APLL
The T0 APLL can be connected to the output of the T0 Output DFS or to the T0 Low-Frequency DFS (see DS3100 data sheet for details). The frequency options listed in the T0 APLL field are all APLL input frequencies. The APLL output frequency is always four times the input frequency. The difference between the "77.76 Analog" and "77.76 Digital" options is whether or not the feedback path of the T0 DPLL includes the T0 feedback APLL. The non-77.76 options in the T0 APLL field are all frequencies from the T0 Low-Frequency DFS. When the T0 APLL setting is changed, the frequencies of all the T0 options in the OC1-OC7 output clock combo boxes automatically change to frequencies derived from the new T0 APLL frequency. These changes match what happens inside the DS3100 device.
Table 4-4. Mapping Between T0 APLL Software Fields and DS3100 Register Fields
SOFTWARE FIELD T0 APLL DS3100 REGISTER FIELDS T0CR1:T0FREQ
4.6
T4 APLL
The T4 APLL can be connected to the output of the T4 DPLL or to the output of the T0 DPLL (specifically the T0 low-frequency DFS; see DS3100 data sheet for details). The frequency options listed in the T4 APLL field are all APLL input frequencies. The APLL output frequency is always four times the input frequency. When the FREQ field is changed in the T4 DPLL box, the frequency of the T4 option listed in the T4 APLL combo box automatically changes to match. If the T4 option in the T4 APLL box is currently selected, the frequencies of all the T4 options in the OC1-OC7 output clock combo boxes automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. Similarly, if the T4 APLL option is changed, the frequencies of all the T4 options in the OC1-OC7 output clock combo boxes automatic change to frequencies derived from the new T4 APLL frequency.
Table 4-5. Mapping Between T4 APLL Software Fields and DS3100 Register Fields
SOFTWARE FIELD T4 APLL DS3100 REGISTER FIELDS T0CR1:T4APT0, T0CR1:T0FT4
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4.7
Output Clocks
The fields in this box configure the DS3100's 11 output clocks. The 2K8K field specifies the source (T0 path or T4 path) for the 2kHz and 8kHz clock options for output clocks OC1-OC7. Similarly the DIG1 and DIG2 fields configure the Digital1 and Digital2 frequency options for OC1-OC7 (see the DS3100 data sheet for details). The OC1-OC7 fields specify the output frequencies for outputs OC1-OC7. Note that when the T0 APLL setting is changed, the frequencies of all the T0 options in the OC1-OC7 fields automatically change to frequencies derived from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the frequencies of all the T4 options in the OC1-OC7 fields automatically change to frequencies derived from the new T4 APLL frequency. These changes match what happens inside the DS3100 device. The OC89 field specifies whether the T0 path or the T4 path is the source for output clocks OC8 and OC9. OC8 is the 64kHz composite clock output. The OC8 field configures the OC8 output clock for 50% or 5/8 duty cycle, and also for whether or not the output signal has 8kHz BPVs and optionally 400Hz absence-of-BPVs per ITU-T G.703 Appendix II options a) and b). The "8K" options in the list enable the 8kHz BPVs but not the 400Hz absence-ofBPVs. The "400" options enable both the 8kHz BPVs and the 400Hz absence-of-BPVs. OC9 is a dedicated 1.544MHz or 2.048MHz output. When OC89 specifies that OC8 and OC9 are sourced from the T4 path, the Auto Squelch checkbox specifies whether or not OC8 and OC9 are automatically squelched when T4 has no valid input references. When OC89 indicates T0 path, Auto Squelch is not available to match DS3100 behavior. OC10 is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be inverted. OC11 is a 2kHz output that can be similarly configured.
Table 4-6. Mapping Between Output Clock Software Fields and DS3100 Register Fields
SOFTWARE FIELD 2K8K DIG1 DIG2 OC1-OC7 OC89 Auto Squelch OC8 OC9 OC10 OC11 DS3100 REGISTER FIELDS FSCR1:2K8KSRC MCR6:DIG1SS, MCR7:DIG1F MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF OCR1-OCR4 MCR4:OC89 T4CR1:ASQUEL OCR4:OC8EN, T4CR1:OC8DUTY MCR8:OC8NO8, MCR8:OC8400 OCR4:OC9EN, T4CR1:OC9SON OCR4:OC10EN, FSCR1:8KPUL, FSCR1:8KINV OCR4:OC11EN, FSCR1:2KPUL, FSCR1:2KINV
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4.8
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
The DPLL frequency limits specify the hard and soft limits of the DPLL frequency range. When the selected reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is not disqualified. If the FLLOL (frequency limit loss of lock) box is checked in the DPLL Lock Criteria box, when the selected reference for a DPLL exceeds the hard limit the DPLL will lose lock (T4 transitions to Not Locked state, and T0 transitions to LOL state). The remaining fields are advanced topics. See Table 4-7 and the DS3100 data sheet for more details.
Table 4-7. Mapping Between DPLL Software Fields and DS3100 Register Fields
SOFTWARE FIELD HARD LIMIT SOFT LIMIT MCPDEN USEMCPD D180 COURSELIM FINELIM FLEN CLEN FLLOL NALOL DS3100 REGISTER FIELDS HARDLIM[9:0] in DLIMIT1 and DLIMIT2 DLIMIT3:SOFTLIM PHLIM2:MCPDEN PHLIM2:USEMCPD TEST1:D180 PHLIM2:COARSELIM PHLIM1:FINELIM PHLIM1:FLEN PHLIM2:CLEN DLIMIT3:FLLOL PHLIM1:NALOL
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4.9
BITS Receivers and BITS Transmitters
The Mode fields in these boxes set the basic line mode for each port (DS1 ESF or SF, E1, 2048kHz, and--for receivers only--6312kHz). The termination fields specify the line termination for the receiver or transmitter port. The DS3100 supports either internal termination (inside the device) or external termination (resistors on the board). As shipped from the factory the demo kit hardware does not have external termination resistors populated, and therefore only the internal termination options should be selected in the software. The input clock (IC1-IC14) to which each BITS receiver should be connected is specified in the CLOCK DEST fields. The output clock to which each BITS transmitter should be connected is specified in the CLOCK SOURCE fields. In the BITS Transmitters box, when a transmitter is in DS1 ESF or E1 mode, the SSM value to be transmitted can be specified in the SSM fields below the TX1 and TX2 headings. In E1 mode, the Sa bit channel in which to transmit SSMs can be specified (for both transmitters) in the small combo box next to the SSM label. In the BITS Receivers box, when a receiver is in DS1 ESF or E1 mode, the received SSM values are displayed in the SSM fields below the RX1 and RX2 headings. In E1 mode, the Sa channel in which to look for incoming SSMs can be specified (for both receivers) in the small combo box next to the SSM label. In future releases of the DS3100DK software, the headings RX1, RX2, TX1, and TX2 will also be buttons that open secondary windows with additional configuration and status fields.
4.9.1
Note About Working with the BITS Receivers and Transmitters
1) When switching BITS transmitter or receiver modes, the termination must be changed to match: internal 100 for DS1, internal 75 or 120 for E1 and 2048kHz, internal 75 for 6312kHz. 2) When switching BITS transmitter modes between DS1 and E1/2048kHz modes, the rate of the transmit clock source (typically OC9) must be changed to match: 1.544MHz for DS1 and 2.048MHz for E1/2048kHz. 3) Enabling analog loopback between BITS transmitter 1 and BITS receiver 1 and between BITS transmitter 2 and BITS receiver 2 can be useful in evaluating the DS3100. During device initialization the DS3100DK software enables analog loopback for both BITS transmitter/receiver pairs by setting ALB = 1 in registers B1BLCR4 (address 93h) and B2BLCR4 (address 113h).
Table 4-8. Mapping Between BITS Software Fields and DS3100 Register Fields
SOFTWARE FIELD BITS RECEIVERS Mode Termination Clock Dest Left-Hand SSM Combo (E1 Only) SSM Textboxes BITS TRANSMITTERS Mode Termination Clock Source Left-and SSM Combo (E1 Only) Main SSM Combos BMCR:TMODE, BTMMR, BTCR1:TB8ZS, BTCR3:TFM, BTCR4:THDB3, BTCR4:TCRC4, 60, 61 See APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences. BLCR2:TION, BLCR2:TIMP BCCR1:TCLKS Indicates which of BTSa4-BTSa8 to use DS1 ESF: BRBOC:RBOC E1: BTSa4-BTSa8 BMCR:RMODE, BCCR3:MCLKFC, BRMMR, BRCR1:RB8ZS, BRCR1:RFM, BRCR3:RHDB3, BRCR3:RCRC4 See APPENDIX 2: BITS MODE WRITE SEQUENCES for exact write sequences for each mode BLCR3:RION, BLCR3:RIMP BCCR2:RCLKD BRMCR:SSMCH DS1 ESF: BTBOC:TBOC E1: BRMSR, BRSSM:SSM DS3100 REGISTER FIELDS
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DS3100DK
4.10
Composite Clock Receivers
The AMI and LOS fields are buttons that represent latched status bits in the device. When the button is raised in the middle, the corresponding latched status bit has been set in the DS3100. Pressing the button clears the latched status bit. The AMI buttons indicate a deviation from the expected one-BPV-in-eight pattern has occurred since that button was last pressed. The LOS buttons indicate no pulses were detected in the input signal in a 32s period (i.e., after two missing pulses). In future releases of the DS3100DK software, the More button will open a secondary window with additional configuration and status fields.
Table 4-9. Mapping Between CC Software Fields and DS3100 Register Fields
SOFTWARE FIELD IC1 AMI IC1 LOS IC2 AMI IC2 LOS DS3100 REGISTER FIELDS MSR3:AMI1 MSR3:LOS1 MSR3:AMI2 MSR3:LOS2
4.11
REFCLK Calibration
Any known frequency error in the local oscillator can be calibrated out inside the DS3100 by setting the ppm value in the REFCLK box. Also the significant edge of the REFCLK signal can be selected in XOEDGE field.
Table 4-10. Mapping Between REFCLK Software Fields and DS3100 Register Fields
SOFTWARE FIELD REFCLK slider/textbox XOEDGE DS3100 REGISTER FIELDS MCLKFREQ[15:0] in MCLK1 and MCLK2 MCR3:XOEDGE
4.12
Register View Window
When the Register View button in the upper-right corner of the main window is pressed, the Register View window appears. In this window the DS3100's entire register set can be viewed and manually written as needed. The large grid that takes up most of the window displays the DS3100 register map. For each register, its hexadecimal address in square brackets is followed by its register name and its contents in 2-digit hex format. The DS3100's core register space is 00h to 7Fh, its BITS transceiver 1 register space is 80h to FFh, and its BITS transceiver 2 register space is 100h to 17Fh. To distinguish between BITS1 and BITS2 registers, all BITS1 register names start with "B1" and all BITS2 register names start with "B2." When a register is clicked on in the main register grid, its register description and fields are displayed at the bottom of the window. Due to the limited speed of the serial port, the demo kit software does not continually poll every register and make real-time updates to the data displayed on the Register View screen. Register of concern should be manually read as described below. The Register View window supports the following actions: * Read a register. Select the register in the register map and click the Read button. * Read all registers. Press the Read All button. * Write a register field. Select the register, double-click the field, and enter the value to be written. * Write a register. Double-click the register name in the register array and enter the value to be written. * Write a multi-register field. Double-click on one of the register names in the register array and enter the value for the field. The software will not allow writes to read-only registers or fields, but it does allow writes to registers that have a mix of read/write and read-only fields.
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DS3100DK
4.13
Configuration Scripts and Log File
4.13.1 Configuration Log File
Every write command issued by the software to the DS3100DK board is logged in file DS3100DKLog.mfg located in the same directory as the software executable. This file can be viewed in Notepad by pressing the Log File button in the upper-right corner of the main window. Command line option "-l " can be used to cause the software to write to a different file than DS3100DKLog.mfg.
4.13.2 Configuration Scripts
All or part of the text in the Configuration Log File can be copied to a text file with a .mfg file extension for use as a configuration script. Configuration scripts are useful for quickly configuring the DS3100 without having to remember all of the required settings. Two types of configuration scripts are possible: full and partial. A full configuration script can start with the DS3100 in its power-on default state and configure every aspect of the device to bring it to a desired state. To make a full configuration script, run the software, uncheck the Demo Mode checkbox, configure the device using the DK software fields (including Register View writes as needed), press the Log File button, and use File->Save As in Notepad to save a copy of the entire log file to a different file name. A partial configuration file only affects a subset of the DS3100 device settings. To make a partial configuration script, press the Log File button to view the Log File, press Ctrl-End to jump to the end of the file, and add to the end of the file a carriage return or comment line (starting with a semicolon) to delimit the start of the configuration. Then save and exit the Log File. Next configure the device using the DK software fields (including Register View writes as needed). Finally view the log file again, jump to the end, and copy everything from the delimiter you made earlier to the end of the file into a new .mfg file. To run a configuration script, press the Config Script button in the upper-right corner of the main window. In the script window, type the path to the file or press the Browse button to navigate to the file. Note that the browser window does not have Desktop and My Documents at the top of the file hierarchy like Windows XP does. Both Desktop and My Documents for can be found under c:\Documents and Settings\. Note that when the Demo Mode checkbox is unchecked, during the "Initializing the DS3100" step, the software runs configuration script startup.mfg located in the same directory as the software executable. Startup.mfg can be edited or replaced as needed to change the initial configuration of the device.
5.
5.1
ADDITIONAL INFORMATION AND RESOURCES
DS3100 Information
For more information about the DS3100, refer to the DS3100 data sheet at www.maxim-ic.com/DS3100.
5.2
DS3100DK Information
For more information about the DS3100DK including software downloads, refer to the DS3100DK Quick View page at www.maxim-ic.com/DS3100DK.
5.3
Technical Support
For additional technical support, e-mail your questions to telecom.support@dalsemi.com.
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DS3100DK
6.
APPENDIX 1: HARDWARE COMPONENTS
DESIGNATION QTY DESCRIPTION SUPPLIER PART
C1, C2, C3, C8, C42, C59-C138, C140, C142, C143, C145, C147, C149, C151, C155, C163-C166, C168, C169 C4, C5, C6, C27 C6 C7 C13, C14, C16, C41 C17, C18, C20 C28, C29 C34-C38, C51-C58, C139, C141, C153, C154 C39, C40 C43 C48, C49 D1 D7 DS1-DS4 DS5-DS10 DS16 J1, J2 J3 J6-J12, J20-J41 J13 J14 J15 J19 J50 J51 J54 J55, J56, J85, J86, J89, J90, J117 J57, J58, J83, J84
99
0.1F 20%, 16V X7R ceramic capacitors (0603)
AVX
0603YC104MAT
4 1 1 4 3 2 17 2 1 2 1 1 4 6 1 2 1 29 1 1 1 1 1 1 1 7 4
Ceramic capacitors (0805) DO NOT POPULATE 470pF 5%, 50V CGO ceramic capacitor (0805) 68F 20%, 16V tantalum capacitor (D case) 4.7F 10%, 25V X5R ceramic capacitors (1206) 6.8F 10%, 6.3V X5R ceramic capacitors (1206) 560pF 5%, 50V NPO ceramic capacitor (0805) 10F 20%, 10V ceramic capacitors (1206) 22pF 10%, 100V ceramic capacitors (1206) 1F 10%, 16V ceramic capacitor (1206) 0.47F 10%, 16V ceramic capacitors (0805) 1A, 50V general-purpose silicon diode 1A, 40V Schottky diode Green LEDs (SMD) Red LEDs (SMD) Green LED (SMD) 6-pin socket strip (single row, vertical) 2.1mm/5.5mm closed frame power jack, high current (right angle PCB, 24VDC at 5A) 5-pin vertical SMB connectors (50) Red socket (banana plug, horizontal) 5-pin vertical SMB connector (50) DO NOT POPULATE 10-pin terminal strip (dual row, vertical) Black horizontal banana plug socket DB9 right-angle connector (long case) 10-pin terminal strip (dual row, vertical) USB Type B black connector (right angle) Bantam jack connectors (right angle) 5-pin BNC connectors (50, right angle)
-- AVX Panasonic Panasonic Panasonic Panasonic Panasonic AVX Corp. Panasonic Panasonic Vishay General Semiconductor International Rectifier Panasonic Panasonic Panasonic Samtec CUI Inc. AMP Mouser AMP Samtec Mouser AMP -- Molex Switchcraft Trompeter
-- 08055A471JAT ECS-T1CD686R ECJ-3YB1E475K ECJ-3YB0J685K ECJ-2VC1H561K ECJ-3YB1A106M 12061A220KAT2A ECJ-3YB1C105K ECJ-2YB1C474K 1N4001 10BQ040 LN1351C LN1251C LN1351C SS-106-TT-2-N PJ-002AH 413990-1 164-6219 413990-1 TSW-105-07-T-D 164-6218 747459-1 -- 67068-0000 RTT34B02 CBJR220
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DS3100DK
DESIGNATION JMP1-JMP5, JMP8, JMP9, JMP11, JMP12, JMP36, JMP37 JMP6, JMP7, JMP10, JMP62, JMP63 R1 R2, R3, R6, R7, R9, R11, R16-R18 R4, R5, R8, R10, R12R14, R20, R25, R42, R46, R84, R91, R92, R95-R97, R110, R113, R115, R116, R120R123 R15, R22, R23, R24, R41, R43, R45, R47,R49, R51, R53, R55, R80, R81, R111, R112, R117, R118 R19, R21, R40, R44 R26, R27, R48, R50, R52 R28 R29-R35, R59-R68 R36-R39, R94, R108 R54, R56, R57, R58, R74, R77, R89, R90 R69, R72 R70, R93 R71, R73 R75, R76 R78 R79 R82, R83 R85-R88 SW5 SW6 SW7, SW8, SW9 T1, T2 T3 T4 TP1-TP10, TP18- TP42, TP49-TP61, TP65-TP84 U1 U2, U3, U5, U7, U9-U26 QTY 11 DESCRIPTION 2-pin vertical headers, 0.100" centers SUPPLIER Samtec PART TSW-102-07-T-S
5 1 9
3-pin vertical headers, 0.100" centers 10k 5%, 1/10W resistor (0805) Resistors (0603) DO NOT POPULATE
Samtec Panasonic --
TSW-103-07-T-S ERJ-6GEYJ103V --
25
10k 5%, 1/16W resistors (0603)
Panasonic
ERJ-3GEYJ103V
18
0 1%, 1/16W resistors (0603) 1.0k 5%, 1/16W resistors (0603) 470 5%, 1/16W resistors (0603) 33.2 1%, 1/16W resistors (0603) 51.1 1%, 1/16W resistors (0603) 330 5%, 1/16W resistors (0603) 0 5%, 1/8W resistors (1206) 110 1%, 1/10W resistors (0805) 10.0 1%, 1/10W resistors (0805) 13.0 1%, 1/10W resistors (0805) 90.9 1%, 1/10W resistors (0805) 357 1%, 1/10W resistor (0805) 301 1%, 1/10W resistor (0805) 0.0 5%, 1/10W resistors (0805) Resistors (0805) DO NOT POPULATE 4-pin single-pole switch 6-pin, through-hole, DPDT slide switch 3-pin, through-hole, SPDT slide switches 16-pin SMT T1 transformers (1CT:1CT and 1CT:2CT, 1500V) 12-pin dual SMT transformer (64kbps, 1CT:2CT, 1500V) 64kbps interface transformer (1CT:1CT, 1500V, 6-pin DIP) 1 plated hole test points DO NOT STUFF High-frequency, surface-mount socket (1mm, 256-pin BGA) TinyLogic ultra-high-speed 2-input OR gates (5-pin SOT23)
AVX
CJ10-000F
4 5 1 17 6 8 2 2 2 2 1 1 2 4 1 1 3 2 1 1 68 1 22
Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic -- Panasonic Tyco Tyco Pulse Engineering Pulse Engineering Pulse Engineering -- Ironwood Electronics Fairchild Semiconductor
ERJ-3GEYJ102V ERJ-3GEYJ471V ERJ-3EKF33R2V ERJ-3EKF51R1V ERJ-3GEYJ331V ERJ-8GEYJ0R00V ERJ-6ENF1100V ERJ-6ENF10R0V ERJ-6ENF13R0V ERJ-6ENF90R9V ERJ-6ENF3570V ERJ-6ENF3010V ERJ-6GEY0R00V -- EVQPAE04M SSA22 SSA12 PE-68678 T7015 PE-65540 -- SG-BGA-6017 NC7SZ32M5
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DS3100DK
DESIGNATION U4, U6 U8 U27 U41 U42 U44 U45 U46 Y1 Y2 Y3 Y7 QTY 2 1 1 1 1 1 1 1 1 1 1 1 DESCRIPTION 3.3V linear regulator (16-pin TSSOP-EP) 1.8V linear regulator (16-pin TSSOP-EP) 3-line to 8-line decoder/demultiplexer (16-pin SO ) Dual RS-232 transmitter/receiver (16-pin, 300-mil SO) High-speed microcontroller (44-pin TQFP, 0C to +70C) Microprocessor voltage monitor (3.08V reset threshold) (4-pin SOT143) Microprocessor voltage monitor (4.38V reset threshold) (4-pin SOT143) Single-chip USB to UART bridge (28-pin QFN) 3.3V, 12.8MHz OCXO (5-pin) through-hole DO NOT POPULATE 3.3V, 12.8MHz TCXO (4-pin SMD) 3.3V, 12.8MHz OCXO (4-pin SMD) DO NOT POPULATE Low-profile 11.0592MHz crystal SUPPLIER Maxim Maxim Texas Instruments Dallas Semiconductor Dallas Semiconductor Maxim Maxim Silicon Laboratories Vectron Vectron Vectron Pletronics PART MAX1793EUE-33 MAX1793EUE-18 SN74HC138NSR DS232AS DS87C520-ECL MAX811TEUS-T MAX812MEUS-T CP2101 MC853X4-035W C22601A1-0028 C4400A1-0044 LP49-33-11.0592M
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DS3100DK
7.
APPENDIX 2: BITS MODE WRITE SEQUENCES
BITS Transmitter
DS1 ESF address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 00h address 21h, write 80h address 21h, write C0h DS1 SF/D4 address 04h, set TMODE[1:0]=00 address 21h, write 02h address 21h, write 00h address 27h, write 0Ch address 29h, write 04h address 21h, write 80h address 21h, write C0h E1 address 04h, set TMODE[1:0]=01 address 21h, write 02h address 21h, write 00h address 29h, write 00h address 2Ah, write 05h address 21h, write 81h address 21h, write C1h address 60h, write 1Bh address 61h, write 40h 2048kHz address 04h, set TMODE[1:0]=10 address 21h, write 02h address 21h, write 00h
BITS Receiver
DS1 ESF address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 40h address 20h, write 80h address 20h, write C0h DS1 SF/D4 address 04h, set RMODE[1:0]=00 address 0Ah, write 40h address 20h, write 02h address 20h, write 00h address 22h, write 60h address 20h, write 80h address 20h, write C0h E1 address 04h, set RMODE[1:0]=01 address 20h, write 02h address 20h, write 00h address 24h, write 68h address 20h, write 81h address 20h, write C1h 2048 kHz address 04h, set RMODE[1:0]=10 address 20h, write 02h address 20h, write 00h 6312 kHz address 04h, set RMODE[1:0]=11 address 20h, write 02h address 20h, write 00h
8. 9.
SCHEMATICS DOCUMENT REVISION HISTORY
REVISION DATE 091806 110206 DESCRIPTION Initial DS3100DK data sheet release. Updated document to describe software v0.7 features: (page 1) Features section; (page 6) Section 3.1; (page 14) Section 4.12; (page 15) added Section 4.13, 4.13.1, 4.13.2; updated table captions.
The DS3100DK schematics are featured in the following 13 pages.
19 of 32
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
8
7
6
5
4
3
2
1
D
R80
0.0
NA NA NA NA NA NA NA NA NA NA NA NA TP29 TP32 TP36 TP38 TP40 TP42 TP31 TP34 TP37 TP39 TP41 TP61
D VCC
RESREF JTRST JTCLK JTDI JTMS JTDO GPIO1 GPIO2 GPIO3 GPIO4
R1
T7 T8 R8 R9 T9 P9
E2 F3 H2 J1
R13 1 TM1 2 R81 0.0 T15 1 TM2 2
R6 1 L14 1 T6 1 K16 1 R7 1 K15 1
2
10K
P2 1 R15 1 N3 1 P13 1 P3 1 P14 1
INTREQ
2
R97 330
1
2
TM1
TM2
JTDI
JTMS
JTDO
JTCLK
GPIO1
GPIO2
GPIO3
RESREF
JTRST*
1
IC1A
GPIO4
R94
WDT
TST_RA1
TST_RA2
TST_RB1
TST_RB2
TST_RC1
TST_RC2
TST_TA1
TST_TA2
TST_TB1
TST_TB2
TST_TC1
IC2 OC1 OC2 OC3 OC4 OC5 OC6POS OC6NEG
TST_TC2
DS10 RED
1 2
C8
IC3
A7 B7 C7 A8 B3 A3 C2 C1 C8 B8 A9 B9 C9 E15 D16 C16 D15 C15 E14
IC4
IC5POS
C
2
.1UF
IC2A
C6
1
1
IC1
10K
IC5NEG
C
IC6POS
IC6NEG
IC7 OC7POS OC7NEG OC8POS
NA
IC8
U1 DS3100_U1
OC8NEG OC9
VCC
IC9
IC11
2 2
IC10
NA
R95
IC13 AD<0>_SDO AD<1>_SDI AD<2>_SCLK AD<3> AD<4> AD<5> AD<6>_CPHA AD<7>_CPOL
OC11
OC1 OC2 OC3 OC4 OC5 OC6POS OC6NEG OC7POS OC7NEG OC8POS OC8NEG OC9 OC10 OC11
R98DNP
IC1 A10 IC1A P6 IC2 B10 IC2A P7 IC3 C10 IC4 A11 IC5POS B5 IC5NEG A5 IC6POS B4 IC6NEG A4 IC7 B11 IC8 C11 IC9 A12 IC10B12 IC11 A13 IC12C12 IC13B13 IC14A14
1 2
IC14
B
1 R96 1 10K
IC12
CONTROL
OC10
10K
SYNC2K 0L_SMT0603_1PCT B14 CJ10-000F SYNC2K
NA SONSDH
SW7 1
2 3
B
1
R99 0.0
2
H16
A<0>
H15
A<1>
SPDT
G16
A<2>
NA
D14 C14
H14
A<3>
G15
SRCSW
SW8 1
2 3
A<4>
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
F16
A<5>
SPDT
VCC IFSEL<0> IFSEL<1> IFSEL<2> REFCLK RST* HIZ* MASTSLV SONSDH SRCSW SRFAIL WDT ALE CS* WR_RW* RD_DS* RDY* INTREQ NC1
G14
A<6>
F15
A<7>
NC2
R7
R9
NC3
INTEL MUX
A8 E16
MASTSLV
SW9 1
2 3
A<8>
2
2
2
2
A
2
SPDT
A
R8
REFCLK H1 PORNOT B6 HIZ 1 R14
IFSEL0 N1 IFSEL1 N2 IFSEL2 P1
TP28
2
R10 10K
R82
R84 10K R91 DNP R92 DNP
IFSEL0 DNP 2 1 R12 IFSEL11 10K 2 R83 IFSEL2 DNP 2 1 AD6 1 DNP AD7 1 DNP
2
MASTSLV R11 SONSDH M3 SRCSW M2 SRFAIL J2 WDT C5 ALE K14 CS_3100 J16 WR J15 RD J14 RDY 1 B15 INTREQ 1 A15
TP1TP2 TP3 TP5 TP4
NC1 1 P12 NC2 1 C13 NC3 1 F14
Wed May 10 13:21:44 2006
TITLE: DATE:
1
1 DNP
1
1
1
DS3100DK01B0
ENGINEER: 6 5 4 3
110705 JML
2 PAGE: 1
1 OF 13
8
7
8
7
6
5
4
3
2
1
NA
0.0 0.0 0.0 0.0
1
1
1
C163.1UF
C164.1UF
C165.1UF
2
2
2
I30 TP10
TRINGA TRINGB THZE TCLK
T2 K3 L2
MCLK
1
RCLK
1
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24
DVDD
1
AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4
TIN
L1
C
R13 10K
2
RSER1 J3
TSER
RSER
L3
TTIPA1 TTIPA1 TRINGA1 TRINGA1 TP6 THZE1 TP8 TCLK1 TOUT1 TIN1 TSER1
R15
DUT33 B1
VDD_ICDIFF VDD_OC6 VDD_OC7
MCLK1 F2 RCLK1 K1 ROUT1 K2
TOUT
ROUT
M1
RVDD_P1 RVDD_P2 TVDD_P1 TVDD_P2
D6 D8 D9 D11 E6 E11 F4 F5 F12 F13 H4 H13 J4 J13 L4 L5 L12 L13 M6 M11 N6 N8 N9 N11 D1 E1 F1 G1 H3 T4 M15 R4 M16 A6 B2 C3
RRING1 R5
R2
RRING
2
C166.1UF
TTIPB
T3
R22 1AVDD_PLL1 2 R23 1AVDD_PLL2 2 R24 1AVDD_PLL3 2 1AVDD_PLL4 2
RTIP1 T5
TTIPA
DS3100_U1
R3
RTIP
PORT
DUT18
DUT33
1
AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4
D
U1
D
C
J1
1
1 2 3 4 5 6
1
NA
2 3 4 5 6
U1 DS3100_U1
PWR & GND
RCLK1 TIN1 ROUT1 RSER1 TSER1
NA
CONN_6P_U
B
U1
TTIPA TTIPB TRINGA TRINGB THZE TCLK TOUT TIN
B16 D7 D10 E7 E8 E9 E10 G4 G5 G12 G13 H5 H12 J5 J12 K4 K5 K12 K13 M7 M8 M9 M10 N7 N10 R1 R16
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28
A1 A16 D4 D5 D12 D13 E4 E5 E12 E13 F6 F7 F8 F9 F10 F11 G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11
B
RTIP2L16
N15 N16 P15 P16 T14 T12 P11 R12
DS3100_U1
GND
RTIP
PORT
AVSS_PLL1 AVSS_PLL2 AVSS_PLL3 AVSS_PLL4
RVSS_P1 RVSS_P2 TVSS_P1 TVSS_P2
VSS_ICDIFF VSS_OC6 VSS_OC7
DVSS
I31 TP18
MCLK
1
RCLK
MCLK2T10 RCLK2R10 ROUT2P10
1 2
TSER
ROUT
RSER2T11
T13
RSER
TTIPA2 TTIPA2 TRINGA2 TRINGA2 I14 THZE2 TP7 I15 TP9 TCLK2 TOUT2 TIN2 TSER2
1
NA
R14 10K
A
D2 E3 G2 G3 P5 M14 P4 N14 C4 A2 D3 P8 J6 J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 L6 L7 L8 L9 L10 L11 M4 M5 M12 M13 N4 N5 N12 N13 T1 T16
VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56
RRING2 L15
RRING
J2
1
1 2
A
1
2 3 4 5 6
3 4 5 6
RCLK2 TIN2 ROUT2 RSER2 TSER2
Wed May 10 13:21:51 2006
TITLE: DATE:
DS3100DK01B0
CONN_6P_U ENGINEER: 5 4 3
110705 JML
2 PAGE: 1
2 OF 13
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6
8
7
6
5
4
3
2
1
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE 12.8MHZ_3.3V
J6
1
Y1
R29 51.1 5
R17
IC1
2
D
1 1 2
DNP
SUPPLY_V
OSC33
1
D
2
1
GND
RF_OUT
C1
.1UF
OSC_MC853X4
1
J7
2
R30 51.1
IC2
12.8MHZ_3.3V
1
VS
R28
Y2
4
OSC_TCXO
1
VC
2
2
1
C
33.2
2
GND
RF_OUT
3 .1UF
1
2
REFCLK
1
J8
R31 51.1
IC3
C
C2
12.8MHZ_3.3V
Y3 J9
1 14 8 1
DNP
2
1
OSC_OCXO
VCC
R11
IC4
2
51.1 R32
1
EFC
7
1
12.8MHZ
C3
R102 DNP
.1UF
2
B
2
J10
1
1
GND
RF_OUT
2
IC7
2
U29
FOUT
B
R33
DNP 1R100
2
VREF VCC VOSC VCCD
13 2 3 4 16
SCL
DNP R101
1
GNDA
11
GND
J11
1
1
51.1
OSC33 1
15
2
12
SDA
1
IC8
2
5
GNDOSC
14
GNDD
1
1
1
1
1
R34
C11DNP
C12DNP
C15DNP
C19DNP
2
2
2
2
2
C21DNP
DS4026_U
1
51.1
A
J12
1
IC9
2
51.1
A
J14
R18
DNP
2
R35
1
1
2
R16
DNP
1
Wed May 10 13:21:45 2006
TITLE: DATE:
1
DS3100DK01B0
ENGINEER: 6 5 4 3
110705 JML
2 PAGE: 1
INPUT CLOCKS 3 OF 13
8
7
8
7
6
5
4
3
2
1
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE
D
D
J28
PLACE TESTPOINTS ON 100 MIL CENTER
1
1
IC10
2 1 1 2
51.1 R59 R65
J34
TP49
IC5POS NA
51.1 1
JMP36
1 21
2 R66 51.1
1
J29
IC11
1
J35
1
TP50
I59 TP53 I60 TP54
1
2
C
R60
51.1
1
IC5NEG
GND
1
C
J30
IC12
1
J36
1
PLACE TESTPOINTS ON 100 MIL CENTER IC6POS
1 2
1
2
NA
R67 51.1 1
R61
51.1
JMP37
1 21
2 R68 51.1
1
TP51 TP52 IC13
1
I61 TP55 I62 TP56
J31
1 2
R62 51.1
J37
1
B
1
IC6NEG
B
J32
IC14
2
R63 51.1
1
J33
SYNC2K
2
R64 51.1
1
A
1
1
A
1
Wed May 10 13:21:49 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER: 6 5 4 3
110705 JML
2 PAGE: 1
INPUT CLOCKS
4 OF 13
8
7
8
7
6
5
4
3
2
1
NA
NA
D
OC1
1
A C B
R41
1 1
0.0
21 4 1 2
A
U9 J20
OC10
21
R53
U21 J26
NA
C
0.0
2
C
4
D
B
NA
NC7SZ32 U10
1
1
A
NC7SZ32 U22
50 OHM VERT
2
B A
2
C
4
4
50 OHM VERT
B
NC7SZ32
NA
4
NA
NC7SZ32
OC2
1
A C B
0.0
R43
1 1 2
21
A
U11 J21
OC11
21
R55
U23
1
J27
0.0
2
C
4
B
NA NA
C B
NC7SZ32 U12
1
1
A
NC7SZ32 U24
50 OHM VERT
2
A
C
2
C
4
4
50 OHM VERT
B
C
NC7SZ32
NA
NC7SZ32
OC3
1
R45
1
21
A
U13 J22
OC6POS
1
0.0
2
C
4
J40
1
I105
B
NA 50 OHM VERT I114 TP60 I113 TP59
NC7SZ32 U14
1
A
2
C
4
B
NC7SZ32
NA
J41
1
1
I107
B
1
OC4
R47
1
21
A
U15 J23
OC6NEG
0.0
2
C
4
B
B
NA 50 OHM VERT OC7POS
1
1
NC7SZ32 U16
I109
1
A
2
C
4
B
J38
I115 TP57 I116 TP58 I111 OC7NEG
1
1
NC7SZ32
NA
OC5
1
R49
1
21
A
U17 J24
0.0
2
C
4
B
NA 50 OHM VERT
NC7SZ32 U18
1
A
2
C
4
J39
A
A
B
NC7SZ32
NA
PLACE TESTPOINTS ON 100 MIL CENTER
OC9
R51
1 1
21
A
U19 J25
0.0
2
C
4
B
NA Thu Oct 13 10:14:03 2005 50 OHM VERT
TITLE: DATE:
NC7SZ32 U20
DS3100DK01B0
ENGINEER: 6 5 4 3
1
A
2
C
4
B
092205 JML
2 PAGE: 1
NC7SZ32
OUTPUT CLOCKS
5 OF 13
8
7
8
7
6
5
4
3
2
1
D VCC VCC
D
2
1.0K
2
R40
R19
11
I20
11
I8 I19
2
1.0K
I5 I1
2
R52470
JMP1
2
JMP3
GPIO1
1
A
U3
GPIO3
1
A
U2
SRFAIL
1
A C B
JMP5 1 2
U26
4 2
I9
4
2
2
B
2
2
B
2 10K R48470
R20
10K
R26470
1
R42
NC7SZ32
11 1 11
NC7SZ32
DS7 I11 RED
2
C
4
C
NC7SZ32
C
DS5 I15 RED
2
11
DS9 I4 RED
2
C
VCC
2
VCC
2
1.0K
R21
11
R44
I36 I35
1
A
I24
11
1.0K
B
2
B
I25
1
A C B
2
JMP2
GPIO2
2 2
B
U7
2
JMP4
GPIO4
4
U25
4 R50470
10K
R27470
R25
1
R46
11
1
10K
NC7SZ32
DS6 I31 RED
2
2
2
NC7SZ32
11 2
2
C
DS8 I27 RED
A
2
A
Thu Oct 13 10:14:03 2005
TITLE: DATE:
GPIO
ENGINEER: 6 5 4 3
DS3100DK01B0 JML
2 PAGE: 1
092205 6 OF 13
8
7
8
7
6
5
4
3
2
1
D
D
I13 RTIP1
2 2
2 C28 DNP 560PF R85 5 16
C26
J55
I12
0.0
TTIPA1
6 7 8 9 10 5
R89
0L_SMT1206_5PCT ERJ-8GEYJ0R00V I5 1 2
I1
T1
2
T
11
T R
J85
R
T1
1
21
15
2
2
1
1
TRINGA1
1:2
14
DNP
3
CONN_BANTAM I14 J57
1:1
R86 DNP 1
CONN_BANTAM I2 J83
1
C
C
1
RRING1
2
B
1
JMP11 2
I3
2
B
R90
I27 RTIP2
2
2 DNP R87 5 16
C27
J56
I25
TTIPA2
0L_SMT1206_5PCT ERJ-8GEYJ0R00V I19 1 2
2
0.0
I15
6 C29 7 8 560PF
T2
T
11 2 10 5 9
T R
J86
1
R
T2
1 2
15
1
2
DNP
1
CONN_BANTAM I28 J58
14 3
2
TRINGA2
1:2
1:1
R88
CONN_BANTAM I16 J84
1
1
DNP
1
RRING2
2
1
A
JMP12 2
I17
2
A
Wed May 10 13:21:42 2006
TITLE: DATE:
BITS TRANSCEIVER
ENGINEER: 6 5 4 3
DS3100DK01B0 JML
2 PAGE: 1
110705 7 OF 13
8
7
8
7
6
5
4
3
2
1
D
D
NA
R57 C48
2
1
2
2
1
IC1A
1
R75 0.0
OC8POS
2 2 1 2
R74
JMP8
2 2
1
0.0
.47UF
NA
90.9
R72
24
NA
21 2
4 C4 DNP
1
J89
1:1
1
357 R78 R79 301
C10 330PF
NA
6 2
T
1
9
T3
NA
1 2
T
2
1
.01UF
2
21
1
JMP7 3
C6 1
7
6
R93
R
2.4
5
JMP10 3
1 2
3
8
NA
T4
J117
5 4
R
2
CONN_BANTAM
1 2
R73 4.7
R58
2:1
1 2
R76 90.9
1:1
NA
2
R770.0
CONN_BANTAM
C
C
1
C5
DNP
1
0.0
2
OC8NEG
1 2 1 2
JMP9
R54 C49
2
1
0.0 .47UF
2
2
1
IC2A
B
B
R69 1
1
J90
21
C9 330PF
NA NA
3 R70 2.4 1
12
T3
21
T
2
11
R
5
10
2
24
NA
0.0
A
1
1
R71
2
4.7
R56
2
CONN_BANTAM
2:1
JMP6 3
A
Wed May 10 13:21:43 2006
TITLE: DATE:
COMPOSITE CLOCK
ENGINEER: 6 5 4 3
DS3100DK01B0 JML
2 PAGE: 1
110705 8 OF 13
8
7
8
7
6
5
4
3
2
1
D
V5_0 D
RS232
C34
1
10UF
2
C38
C35
U41 DS232A
NA J15
1 3 5 2 4 6
2
VPOS
VCC
16 2 4 6 7
7 8
12 10UF 2 C36 16 1
10UF
2 C37
10UF
VNEG
GND
15
11
10UF
C1POS
C2POS
42
3
C1NEG
C2NEG
5
(SCLK) AD2 1 (SDIO) AD1 3 SLAVE 5 NA
1
A C B
330
RX232 TX232 GREEN
R108
13
R1IN
R1OUT
12
8 9
9 10
8
R2IN
R2OUT
9
10
11
T1IN
T1OUT
14
10 14 2 1 2 2
C
T2IN
T2OUT
7
U5
DS16
V5_0
VCC
CONN_10P
C
NC7SZ32
1
JMP62 USB_TXD 3 U42
40
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 RST P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 XTAL1 XTAL2 GND<2-0> EA ALE PSEN P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC
USB_RXD JMP63 1 3
2
2
U27 RXD0
41 42 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 20 19 18 43 44 1 2 3 37 38
TXD0
SCS 1 GND 1
R5 DNP 2 R6 0.0
5 2
G2B*
Y0* Y1*
15 14
CSS CSM A12 1
2
A B Y2* Y3*
13 12
SCS AD2 AD1
1R2 1R3 1R4
0.0 2 0.0 2 0.0 2
V5_0
3
C
Y4* Y5*
11 10
B
J50
POR
4 5 7 8 9 10 11
2
6
R110 10K
6
A
1
G1
Y6*
9 4
G2A* Y7*
B
7
F
G
8
C
TX232 3 RX232 RXD0 TXD0 INTREQ
1
7
B
2
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE
H
74AHC138
9
D
4
J
E
5
NA
SW6 DPDT
CONN_DB9P
WR RD
12 13 14
A12
CS_3100 SLAVE
1 2 3 6 5 4
CSM SLAVE CSS
Y7
1 2
11.0592MHZ 15
1 1
A
A8
A
C39
2
22PF
DS87C520_TQFP
22PF C40
2
Thu Oct 13 10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER: 6 5 4 3
092205 JML
2 PAGE: 1
9 OF 13
8
7
8
7
6
5
4
3
2
1
D
D
VCC
1
2 R115
1
2
R113
2
NA
1 2 1
VDD
J51
C41 10K
4.7UF C42
10K
.1UF
6
C
1 3 5
USBDP VBUS RST*
J54
2 4 6 8 10
TXD RXD
26 1
25 1
RTS*
R117 0.0 2 R118 0.0
2 24 1
USB_TXD USB_RXD NA
CTS*
C
1 4 6 4 8 9 7 11 12 8 5
USBDM
3
USB
2
9
9
10
CP2101_U1
REGIN SUSPEND_LOW*
DCD* RI* NC7 NC8 NC9 SUSPEND_HIGH NC10
11 21 18 19 20 21
NA
2 2
JTCLK JTDO JTMS JTRST JTDI
VDD DATDAT+ GND SH
1 2 3 4
23 1
2
7
7
5
DSR*
27 1
TP84 TP83 NA
5
R120 10K
U46
DTR*
28 1
2
R121 10K R122 10K R123 10K
CONN_10P
B
B
1
I40 3.08V
I37 4.38V
C43
2
NC11
22
GND
NC1
NC2
NC3
NC4
10K
NC5
SW5
VCC
4
MR* GND RESET VCC
1UF R116
I42
V5_0
4 2
2
1
3
1
VCC RESET*
4 3 1
U44 MAX811_U
2
U45 MAX812_U
2
3
3
MR*
1
GND
R111
1
0.0 0.0
2
PORNOT
1 2
R112
POR
A
10 13 14 15 16 17
NC6
A
Thu Oct 13 10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER: 6 5 4 3
092205 JML
2 PAGE: 1
10 OF 13
8
7
8
7
6
5
4
3
2
1
D V5_0 V5_0
C7
D
U4
JMP13
2
IN1 IN2 IN3 OUT3 OUT2 OUT1
VCC
12 1 2
J13
A B
1 2
68UF
1
2
DUT33
1
CONN_BANANA_2P
1 4 C17
IN4 RST* SHDN* SET GND OUT4
2 14 4.7UF C13 6.8UF
2
2.1MM/5.5MM
7 11 10 1 2
6
C V5_0
J19
A B
2
1 2 2
IN1 IN2 IN3 IN4 OUT2 OUT3 OUT4 RST* SHDN* SET OUT1
CONN_BANANA_2P
1
4 5
14 C18 15 6 11
GND
4.7UF
1
C14
2
2
6.8UF
V5_0
7
R36
DS1
21 2 10
B
330
2
1
1
V5_0
OSC33 1
21
330
R37
DS2
2
1
IN2
OUT2
4.7UF
C16
DUT33 1
21
330
2
2
C20
IN4
OUT4 RST*
NA DUT18 1
A C B
330 R39
6 7
SHDN* SET
11
GND
U28
DS4
21 2 41
10
2
A
NC7SZ32
2
6.8UF
R38
DS3
4 5
IN3
OUT3
14 15
1
8
7
6
D1
5 15
J3
1
3
13
C
MAX1793_U2 U6
12 13 1 3
NA
JMP14 OSC33 2
D7 1 AMP
B V5_0
2 3
MAX1793_U2 U8
IN1 OUT1
NA
JMP15
12 13 1 2
DUT18
MAX1793_U2
A
Wed May 10 13:21:47 2006
TITLE: DATE:
DS3100DK01B0
ENGINEER: 5 4 3
110705 JML
2 PAGE: 1
11 OF 13
A
C54
C
D
C53
B
C52
C51
TP67 TP66
.1UF C106
.1UF C105
.1UF C104
TP73 TP71 TP72 TP70
.1UF C126
.1UF C125
.1UF C124
TP78 TP76 TP77 TP75
.1UF
.1UF
.1UF
TP82 TP80 TP81
8 7 6 5 4 3 ENGINEER: TITLE:
8
2
10UF C58
1 1
10UF C62
2
10UF C57
1 1
10UF C61
2
10UF C56
1
VCC
2
10UF C55
1
VCC
GND
DUT18
DUT33
2 2
.1UF C66
2 2
.1UF C65
2
10UF C60
1 1
.1UF C64
2
10UF C59
1 1
.1UF C63
VCC
1 1
.1UF C70
1 1
.1UF C69
2 2
.1UF C68
2 2
.1UF C67
2 2
.1UF C74
2 2
.1UF C73
1 1
.1UF C72
1 1
.1UF C71
1 1
.1UF C78
1 1
.1UF C77
2 2
.1UF C76
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2
.1UF C75
I112 I111 I113 TP65
2 2
.1UF C82
2 2
.1UF C81
1 1
.1UF C80
1 1
7
.1UF C79
1 1
.1UF C86
1 1
.1UF C85
2 2
.1UF C84
2 2
.1UF C83
2 2
.1UF C90
2 2
.1UF C89
1 1
.1UF C88
1 1
.1UF C87
1 1
.1UF C94
1 1
.1UF C93
2 2
.1UF C92
2 2
.1UF C91
2 2
.1UF C98
2 2
.1UF C97
1 1
.1UF C96
1 1
.1UF C95
1 1
.1UF C102
1 1
.1UF C101
2 2
.1UF C100
2 2
.1UF C99
I96 I97 I92 I91 I99 I98 TP68 TP69
2 2 2
.1UF C110
2 2 2
.1UF C109
1 1 1
.1UF C108
1 1
.1UF C103
1 1 1
.1UF C114
1 1 1
.1UF C113
2 2 2
.1UF C112
2 2
.1UF C107
1 1
.1UF C111
6
2 2
.1UF C118
2 2
.1UF C117
1 1
.1UF C116
2 2
C115 .1UF
1 1
.1UF C122
1 1
.1UF C121
2 2
.1UF C120
1 1
.1UF C119
I79 I78 I77 I76 I90 TP74
2 2 2
.1UF C130
2 2 2
.1UF C129
1 1 1
.1UF C128
2 2
.1UF C123
1 1 1
.1UF C134
1 1 1
.1UF C133
2 2 2
.1UF C132
1 1
.1UF C127
2 2
.1UF C131
2 2 2
2 2 2
1 1
.1UF C136
1
5
1
C138 .1UF
1
C137 .1UF
2 2
2
.1UF C135
I69 I70 I60 I71 TP79
1 1
.1UF
1
1
1
2
4
C153
C139
2
10UF C154
1
2
10UF C141
1
V5_0
OSC33
2
10UF C155
1 1
.1UF C168
2
10UF C143
1 1
.1UF C145
V5_0
2 2
.1UF C169
2 2
.1UF C147
1 1
.1UF
1
3
2
2
.1UF C149
1 1
.1UF C151
2 2
.1UF C140
1 1
.1UF C142
JML
2 PAGE: 1
2 2
.1UF
1
2
DS3100DK01B0
DATE:
1
Thu Oct 13 10:14:03 2005
092205
12 OF 13
B
A
C
D
8
7
6
5
4
3
2
1
D
D
REVISION HISTORY 050206 012106 RELEASE TO FAB 011306 010406 CHANGED REF DESIGNATORS TO MATCH EE REMOVED 5V CAPS, LEDS AND SWITCHES FROM MICRO, LOW Z TP FROM ICN 112105 MOVED MEMORY MAP,OTHER MISCELLANEOUS 111905 110705 RELEASE FOR REVIEW FIX TRANSFORMER ISSUES,ADDED POWER JACK,FIXED CSM/CSS LOGIC,ADDED TPS
C
01
02
C
03
04
05
A0
B0
B
ADDED BUFFER TO 1.8V LED ADDED 0 OHM RESISTORS AT SDIO,SCLK,SCS ADDED INTEL BUS CONNECTIONS MADE INTEL MUX MODE DEFAULT ADDED 330PF CAPS AT COMPOSITE CLOCK INPUT FIXED COMPOSITE CLOCK TERMINATION RES CHANGED 138 TO AHC FROM HC MOVED UP OK LED TO P1.1 AND REVERSED LOGIC CHANGED CAP ON COMPOSITE CLOCK TX TO .01UF ADDED SHORTED JUMPERS AT REGULATORS FOR ACCESS MOVED CSM TO 1000 AND CSS TO 0 ADDED DS4026 TCXO AND SUPPORTING COMPONENTS
B
A
A
Thu Oct 13 10:14:03 2005
TITLE: DATE:
DS3100DK01B0
ENGINEER: 6 5 4 3
092205 JML
2 PAGE: 1
13 OF 13
8
7

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