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Elan Microelectronics Crop.
EM65100
69COM/ 101SEG 4 Gray Level STN LCD Driver
March 08, 2005 Version 0.6
Version 0.1
0.2
0.3 0.4 0.5 0.6
EM65100 Specification Revision History Content Initial version Page 12:Power circuit block diagram Page 16:Parallel input order Page 16,51:delete slave mode Page 18,60:First step to read the specific register Page 21:RAM address of Monochrome mode Page 38: bank number Page 40,41: write/read one byte data into DDRAM Page 57:The table of SC register set up Page 63,64: driver sink current, Ron value of SSEG and SCOM DC characteristics values Remove the word "Preliminary" Page 6: Modify RESB ITO Resistor value Page 7: CSB and WRB exchange pad sequence Page 15: "CK" pin voltage for using internal clock. Modify dynamic current of Display off on page 63 Modify ITO value Modify RESET time
Date April 13, 2003
June 3,2003
August 1,2003 August 28,2003 October 12,2004 March 08,2005
Caution: The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
GENERAL DESCRIPTION ................................................................................................................................................. 4 FEATURE ............................................................................................................................................................................... 4 APPLICATIONS .................................................................................................................................................................... 4 PIN CONFIGURATIONS (PACKAGE) ............................................................................................................................. 5 FUNCTIONAL BLOCK DIAGRAM ................................................................................................................................ 10 PIN DESCRIPTION ............................................................................................................................................................ 12 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 16 CONTROL REGISTER ...................................................................................................................................................... 41 RELATIONSHIP BETWEEN SETTING AND COMMON/DISPLAY RAM.............................................................. 61 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 62 DC CHARACTERISTICS .................................................................................................................................................. 63 AC CHARACTERISTIC .................................................................................................................................................... 66 APPLICATION CIRCUIT.................................................................................................................................................. 74
EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
1. General description
EM65100 is one STN-LCD drivers for 4-gray scale display. The sub-screen display function makes it possible to display different images and data in a sub-screen inside the main LCD screen. It also has a built-in display RAM, a power supply circuit for LCD drive, and an LCD controller circuit, therefore contributing to compact system design. Its partial display function realizes low power consumption. *Partial display function: A function that utilizes only part of the screen, thus reducing power consumption.
2. Feature
Display RAM capacity Graphic: 104*67*2=13,936 bits Icons: 104*2*2=416 bits Ratio of display duty cycle: 1/10, 1/18, 1/26, 1/34, 1/42, 1/50, 1/58, 1/69 Outputs Segment:101 outputs, Common: 67 outputs Static driver: 2 outputs Built-in display104x69x2=14352bit RAM and power supply circuit Partial display functions Bus connection with 80-family/ 68-family and Elan MPU Serial interface is available Logic power supply voltage: 1.8 to 3.3 V LCD driving voltage: 5.0 to 12.0 V Booster: 2 to 4 times Write system cycle: 140 ns Package(Ordering information): Part Number EM65100AGH Package Gold bumped chip Description NA Package information Page 5
Note: The EM65100 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad without bumped); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example EM65100AGH EM65100: Elan number ; A: Package Version ;GH: COF Gold bumped chip
3. Applications
Mobile phone Small PDA
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
4. Pin configurations (package)
246
117
247
116
EM65100AGH
268 95
1
Figure 1. Pin configuration
94
Note: With the Elan logo in down left the pin 1 is in the down left corner
Mark U-Left D-Left U-Left and D-Right:
Coordinate (X,Y) -3195.0,350.0 -3195.0,-350.0
Mark U-Right D-Right
Coordinate (X,Y) 3195.0,350.0 3195.0,-350.0
D-Left and U-Right: 100um
40 20 40 100um
100um
40
20 40
100um
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Pad configuration
Size X 7260 56 63 63 63 48 36 50 (min.) 508 +/- 25.4 All Pad 17 +/- 3 (within die) 14 Chip center Y 1570 63 56 36 48 63 63 m
Item Chip size
Pad No. 1~94 95,96,267,268 97~115,248~266 116,247 117,246 118~245
Unit
Bump Size
Pad Pitch Die thickness
(excluding bumps)
Bump Height Minimum Bump Gap Coordinate Origin
Recommended COG ITO Traces Resistor
Interface V0~V4 CAP1+,CAP1-,CAP2+,CAP2-,CAP3+,Vcc VDD,Vci VSSL,VSSH WRB,RDB,CSB,...,D0~D7 RESB ITO Traces resistances Max=50 Max=3K Max=5~10 K
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
PAD Coordinates Table
Pin NO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad Name
WRB RESB RS CSB RDB D0 D1 D2 D3 D4 D5 D6 D7 VSS CK CKS VREF VREF VREF VREF VREF VDD VDD VDD VDD VDD Vci Vci Vci Vci Vci VSSL VSSL VSSL VSSL VSSL Vcc Vcc Vcc Vcc Vcc CAP3+ CAP3+ CAP3+ CAP3+ CAP3+ CAP1CAP1CAP1CAP1-
Coordinate (X,Y)
-3348.6 ,-654.5 -3278.6 ,-654.5 -3208.6 ,-654.5 -3138.6 ,-654.5 -3068.6 ,-654.5 -2998.6 ,-654.5 -2928.6 ,-654.5 -2858.6 ,-654.5 -2788.6 ,-654.5 -2718.6 ,-654.5 -2648.6 ,-654.5 -2578.6 ,-654.5 -2508.6 ,-654.5 -2438.6 ,-654.5 -2368.6 ,-654.5 -2298.6 ,-654.5 -2228.6 ,-654.5 -2158.6 ,-654.5 -2088.6 ,-654.5 -2018.6 ,-654.5 -1948.6 ,-654.5 -1878.6 ,-654.5 -1808.6 ,-654.5 -1738.6 ,-654.5 -1668.6 ,-654.5 -1598.6 ,-654.5 -1528.6 ,-654.5 -1458.6 ,-654.5 -1388.6 ,-654.5 -1318.6 ,-654.5 -1248.6 ,-654.5 -1178.6 ,-654.5 -1108.6 ,-654.5 -1038.6 ,-654.5 -968.6 ,-654.5 -898.6 ,-654.5 -828.6 ,-654.5 -758.6 ,-654.5 -688.6 ,-654.5 -618.6 ,-654.5 -548.6 ,-654.5 -478.6 ,-654.5 -408.6 ,-654.5 -338.6 ,-654.5 -268.6 ,-654.5 -198.6 ,-654.5 58.6 ,-654.5 128.6 ,-654.5 198.6 ,-654.5 268.6 ,-654.5
Pin NO
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name
CAP1CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2CAP2CAP2CAP2CAP2V4 V4 V4 V4 V3 V3 V3 V3 V2 V2 V2 V2 V1 V1 V1 V1 V0 V0 V0 V0 VSSH VSSH VSSH VSSH VSSH TEST P/S VDD NC1 SCOM COM33 COM32 COM31 COM30
Coordinate (X,Y)
338.6 ,-654.5 408.6 ,-654.5 478.6 ,-654.5 548.6 ,-654.5 618.6 ,-654.5 688.6 ,-654.5 758.6 ,-654.5 828.6 ,-654.5 898.6 ,-654.5 968.6 ,-654.5 1038.6 ,-654.5 1108.6 ,-654.5 1178.6 ,-654.5 1248.6 ,-654.5 1318.6 ,-654.5 1388.6 ,-654.5 1458.6 ,-654.5 1528.6 ,-654.5 1598.6 ,-654.5 1668.6 ,-654.5 1738.6 ,-654.5 1808.6 ,-654.5 1878.6 ,-654.5 1948.6 ,-654.5 2018.6 ,-654.5 2088.6 ,-654.5 2158.6 ,-654.5 2228.6 ,-654.5 2298.6 ,-654.5 2368.6 ,-654.5 2438.6 ,-654.5 2508.6 ,-654.5 2578.6 ,-654.5 2648.6 ,-654.5 2718.6 ,-654.5 2788.6 ,-654.5 2858.6 ,-654.5 2928.6 ,-654.5 2998.6 ,-654.5 3068.6 ,-654.5 3138.6 ,-654.5 3208.6 ,-654.5 3278.6 ,-654.5 3348.6 ,-654.5 3499.5 ,-469.5 3499.5 ,-399.5 3499.5 ,-339.5 3499.5 ,-289.5 3499.5 ,-239.5 3499.5 ,-189.5
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Pin NO
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name
COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMA SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18
Coordinate (X,Y)
3499.5 ,-139.5 3499.5 ,-89.5 3499.5 ,-39.5 3499.5 ,10.5 3499.5 ,60.5 3499.5 ,110.5 3499.5 ,160.5 3499.5 ,210.5 3499.5 ,260.5 3499.5 ,310.5 3499.5 ,360.5 3499.5 ,410.5 3499.5 ,460.5 3499.5 ,510.5 3499.5 ,560.5 3499.5 ,616.5 3231.0 ,654.5 3175.0 ,654.5 3125.0 ,654.5 3075.0 ,654.5 3025.0 ,654.5 2975.0 ,654.5 2925.0 ,654.5 2875.0 ,654.5 2825.0 ,654.5 2775.0 ,654.5 2725.0 ,654.5 2675.0 ,654.5 2625.0 ,654.5 2575.0 ,654.5 2525.0 ,654.5 2475.0 ,654.5 2425.0 ,654.5 2375.0 ,654.5 2325.0 ,654.5 2275.0 ,654.5 2225.0 ,654.5 2175.0 ,654.5 2125.0 ,654.5 2075.0 ,654.5 2025.0 ,654.5 1975.0 ,654.5 1925.0 ,654.5 1875.0 ,654.5 1825.0 ,654.5 1775.0 ,654.5 1725.0 ,654.5 1675.0 ,654.5 1625.0 ,654.5 1575.0 ,654.5
Pin NO
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name
SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49
Coordinate (X,Y)
1525.0 ,654.5 1475.0 ,654.5 1425.0 ,654.5 1375.0 ,654.5 1325.0 ,654.5 1275.0 ,654.5 1225.0 ,654.5 1175.0 ,654.5 1125.0 ,654.5 1075.0 ,654.5 1025.0 ,654.5 975.0 ,654.5 925.0 ,654.5 875.0 ,654.5 825.0 ,654.5 775.0 ,654.5 725.0 ,654.5 675.0 ,654.5 625.0 ,654.5 575.0 ,654.5 525.0 ,654.5 475.0 ,654.5 425.0 ,654.5 375.0 ,654.5 325.0 ,654.5 275.0 ,654.5 225.0 ,654.5 175.0 ,654.5 125.0 ,654.5 75.0 ,654.5 25.0 ,654.5 -25.0 ,654.5 -75.0 ,654.5 -125.0 ,654.5 -175.0 ,654.5 -225.0 ,654.5 -275.0 ,654.5 -325.0 ,654.5 -375.0 ,654.5 -425.0 ,654.5 -475.0 ,654.5 -525.0 ,654.5 -575.0 ,654.5 -625.0 ,654.5 -675.0 ,654.5 -725.0 ,654.5 -775.0 ,654.5 -825.0 ,654.5 -875.0 ,654.5 -925.0 ,654.5
SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Pin NO
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name
SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51
Coordinate (X,Y)
-975.0 ,654.5 -1025.0 ,654.5 -1075.0 ,654.5 -1125.0 ,654.5 -1175.0 ,654.5 -1225.0 ,654.5 -1275.0 ,654.5 -1325.0 ,654.5 -1375.0 ,654.5 -1425.0 ,654.5 -1475.0 ,654.5 -1525.0 ,654.5 -1575.0 ,654.5 -1625.0 ,654.5 -1675.0 ,654.5 -1725.0 ,654.5 -1775.0 ,654.5 -1825.0 ,654.5 -1875.0 ,654.5 -1925.0 ,654.5 -1975.0 ,654.5 -2025.0 ,654.5 -2075.0 ,654.5 -2125.0 ,654.5 -2175.0 ,654.5 -2225.0 ,654.5 -2275.0 ,654.5 -2325.0 ,654.5 -2375.0 ,654.5 -2425.0 ,654.5 -2475.0 ,654.5 -2525.0 ,654.5 -2575.0 ,654.5 -2625.0 ,654.5 -2675.0 ,654.5 -2725.0 ,654.5 -2775.0 ,654.5 -2825.0 ,654.5 -2875.0 ,654.5 -2925.0 ,654.5 -2975.0 ,654.5 -3025.0 ,654.5 -3075.0 ,654.5 -3125.0 ,654.5 -3175.0 ,654.5 -3231.0 ,654.5 -3499.5 ,616.5 -3499.5 ,560.5 -3499.5 ,510.5 -3499.5 ,460.5
Pin NO
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268
Pad Name
COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COMB SSEG M86
Coordinate (X,Y)
-3499.5 ,410.5 -3499.5 ,360.5 -3499.5 ,310.5 -3499.5 ,260.5 -3499.5 ,210.5 -3499.5 ,160.5 -3499.5 ,110.5 -3499.5 ,60.5 -3499.5 ,10.5 -3499.5 ,-39.5 -3499.5 ,-89.5 -3499.5 ,-139.5 -3499.5 ,-189.5 -3499.5 ,-239.5 -3499.5 ,-289.5 -3499.5 ,-339.5 -3499.5 ,-399.5 -3499.5 ,-469.5
Note: For PCB layout, IC substrate must be floated or connected to VSS
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
5. Functional block diagram
5.1 System Block Diagram
COM 67 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SCOM SSEG COM B COM A COM 0 SEG4 SEG5 SEG 3 SEG0 SEG2 SEG1
VDD V0 V1 V2 V3 V4 VSS (VSSH,VSSL) CAP1CAP1+ CAP2CAP2+ CAP3+
---Com m on Driver
---------Segment Driver Gradation Selection Circuit Static Driver
Shift Register Data Latch
Data Latch
Line Address Decoder
Display Line Register
Display Line Counter
Voltage Converter
Y Address Decoder
Y Address Register
Y Address Counter
Booster Circuit
Display RAM (DDRAM ) 101 X 67 X 2 bits
Vcc Vci VREF
Pixel Display RAM (PGRAM ) 101 X 2 X 2 bits X Address Decoder
D7 D6 D5 D4 D3 D2 D1/SDA D0/SCL Input/Output Buffer
RAM Interface
X Address Counter
X Address Register
Alternation Circuit
Bus Holder
Instruction Decoder
Register Read
M PU Interface
OSC
Display Tim ing Gen.
CSB
RS
RDB W R B P/S M 86 RESB TEST (E) (R/W B)
CK CKS
Figure 2. System Block Diagram
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
5.2 Power Circuit Block Diagram
CAP3+ CAP1CAP2CAP1+ CAP2+
V0
Vci
Vcc Booster Circuit
V1 Dividing Resistor V2
VREG AMP VREF
+ -
Rb
Electronic Volum e Register
Bias Register
V3
Ra
Booster step set Register
V4 Im pedence Converter
Figure 3. Power Circuit Block Diagram
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
6. Pin Description
6.1 Power Supply Pins Symbol VDD VSSL VSSH V0 V1 V2 V3 V4 I/O Power Supply Power Supply Power Supply Power Supply Description Power supply pin for logic circuit to +1.8 to 3.3V Ground pin for logic circuit, connect to 0V Ground pin for high voltage circuit, connected to 0V Bias power supply pin for LCD drive voltage When using an external power supply, convert impedance by using resistance-division of LCD drive power supply or operation amplifier before adding voltage to the pins. These voltages should have following relationship: VSS6.2 LCD Power Supply Circuit Pins Symbol CAP1+ CAP1CAP2+ CAP2CAP3+ VREF Vci Vcc I/O O O O O O I Power Supply O Description When internal Booster circuit is used, external capacitor(s) is/are connected to these pin
Voltage input pin for generating reference power source Voltage supply pin for booster circuit. Usually the same voltage level as VDD. Output pin of boosted voltage in the built-in booster. The capacitor must be connected between this pin and VSS.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
6.3 System Bus Pins Symbol RESB I/O I Description Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = "H"), The D7-D0 are 8-bits bi-directional data bus, connect to MPU data bus. When serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for data transfer clock SDA: Serial data input pin SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of 8th clock of SCL After completing data transferring, or when making no access, be sure to set SCL to "L". Chip Select input pin. CSB = "L": accepts access from MPU CSB = "H": denies access from MPU RAM/Register select input pin. RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin Select 80-family MPU type (M86 = "L") The RDB is a data read signal. When RDB is "L", D7-D0 are in an output status. Select 68-family MPU type (M86 = "H") R/WB = "H": When E is "H", D7-D0 are in an output status. R/WB = "L": The data on D7-D0 are latched at falling edge of the E signal. Read/Write control pin Select 80-family MPU type (M86 = "L") The WRB is a data write signal. The data on D7-D0 are latched at rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" Parallel/Serial interface select pin. P/S Chip select Data identification Data Read/Write Serial clock H CSB RS D0-D7 RDB, WRB L CSB RS SDA Write only SCL P/S = "H": For parallel interface. P/S = "L": For serial interface. Fix D15-D5 pins are Hi-Z, RDB and WRB pins to either "H" or "L". For testing. Fix to "L".
D0/SCL D1/SDA D2-D7
I/O
CSB RS
I I
RDB (E)
I
WRB (R/WB)
I
M86
I
P/S
I
TEST
I
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
6.4 LCD Drive Circuit Signals Symbol I/O Description Segment output pins for LCD drives. According to the data of the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode). non-lighted at "1", lighted at "0" (Reverse Mode) and, by a combination of M signal and display data, one signal level among V0,V2,V3 and VSS signal levels are selected. (When Monochrome Display) O
M Signal Display RAM Data Normal Mode Reverse Mode V2 V0 V0 V2 V3 VSS VSS V3
SEG0SEG101
Common output pins for LCD drivers. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS signal level is selected. COM0COM66 O Data M Output level H H VSS L H V1 H L V0 L L V4 Common output pin for LCD drive exclusively for icons. Common output pin for LCD drive exclusively for icons. LCD driver output pin for static driver
COMA COMB SCOM SSEG
O O O
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
6.5 Oscillating Circuit Pin Symbol CKS CK I/O I I Description Display timing clock source select input pin. CKS = "H": Use external clock from CK pin. CKS = "L": Use internal oscillated clock. External clock input pin for display timing. When use internal clock, fix the CK pin at "L".
* This specification is subject to be changed without notice.
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7. Functional Description
7.1 MPU Interface 7.1.1 Selection of Interface Type The EM65100 transfers data through 8-bit parallel I/O (D7-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can select by state of P/S pin. When select serial interface, data reading cannot be performed, only data writing can operate. P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 -
7.1.2 Parallel Input When parallel interface is selected with the P/S pin, the EM65100 allows data to be transferred in parallel to an 8-bit MPU through the data bus. For the 8-bit MPU, either the 80-family MPU interface or the 68-family MPU interface can be selected with the m86 pin. M86 H L MPU Type 68-family MPU 80-family MPU CSB CSB CSB RS RS RS RDB E RDB WRB R/WB WRB Data D7~D0 D7~D0
7.1.3 Read/Write functions of Register and display RAM The EM65100 have four read/write functions at parallel interface mode. Each read/write function select by combinations of RS, RDB and WRB signals. RS 1 1 0 0 68-family R/WB 1 0 1 0 80-family RDB WRB 0 1 1 0 0 1 1 0 Function Read internal Register Write internal Register Read display data Write display data
7.1.4 Serial Interface The serial interface of EM65100 can accept inputs of SDA and SCL in the state of chip select (CSB="L"). When not in the state of chip select. The internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. The identification whether are serial data inputs (SDA) are display data or control register data is judged by input to RS pin. RS = "L": display RAM data RS = "H": control register data After completing 8-bit data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board wiring. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 8-bit data transferring.
* This specification is subject to be changed without notice.
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When serial interface is used, access is only made for 8-bit data transfer.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
valid
D7 D6 D5 D4 D3 D2 D1 D0
Figure 4. Serial Interface
7.2 Data write to Display RAM and Control Register The data write to display RAM and Control Register use almost same procedure, only different setting of RS that select access object. RS = "L": Display RAM data RS = "H": Control register data In the case of the 80-family MPU, the data is written at the rising edge of WRB. In the case of the 68-family MPU, the data is written at the falling edge of signal E. Data write operation
D0~D7 W RB RS W rie to which W rie to control register W rie to display RAM
Data0 Data1 Data2 Data3 Data4
Figure 6. Data write operation 7.3 Internal Register Read In the case of display RAM read operation, need dummy read one time. The designated address data are not output to read operation immediately after the address set to AX or AY register, but are output when the second data read. Dummy read is always required one time after address set and write cycle.
* This specification is subject to be changed without notice.
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Read display RAM operation
W RB D0~D7
n
Address set (AX,AY) Address = n
***
Dum m y Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
RDB RS
Figure 7. Read display RAM operation The EM65100 can be read the control registers, in case of control register read operation, data bus upper nibble (D3-D0) use for register address (0 to FH). In maximum, 16 registers can access directly. But number of register is more than 16 registers. Therefore, EM65100 has register bank control. The RE register is set bank number to access. And the RE address is 0FH, in any bank can access RE register. It is need 4-steps to read the specific register in maximum case. (1) Write 02H to RE register for access to RA register. (2) Writes specific register address to RA register. (3) Write specific register bank to RE register. (4) Read specific register contents. Register read operation
W RB D0~D7
04H
Bank number write to RE for RA
addr
Address write to RA
bank
Bank number write to RE
data
read specific register
RDB RS
Figure 8. Register read operation 7.4 Display Start Address Register This register determines the Y-address of the display RAM corresponding to the display start line. The display RAM data that addressed Display Start Address register output to common driver start line. The actual common start line of LCD panel depend on Display Start Common register and SHIFT bit of Display Control register. The register are preset every timing of FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates line addresses which read out sequentially 288 bits data from display RAM to LCD drive circuit. 7.5 Addressing of Display RAM The EM65100 has built-in bit mapped display RAM. The display RAM consists of 208 bits in the X-direction and 69 bits in the Y-direction. In the gradation display mode, the EM65100 provides segment driver output for 4-gradation display using 2 bits. When connected to an STN LCD panel, the EM65100 can display 101*69 pixels with 4-gradation display. The address area in the X-direction depends on the access bus size. When use 8-bits bus size, can access 00H to 19H address. In the X-direction, X Address register use to access; and in the Y-direction, Y Address register use to access. Do not specify any address outside the effective address area in each access mode because it is not permitted.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
In Gradation Display Mode (MON="0") 8-bits bus size access X-address 0H 1H ----------------------------------------------------------------- 18H 19H 0H 8bit 8bit 8bit 8bit ---------------44H 8bit 8bit 8bit 8bit RAM data = "1" lighted Reverse display (REV=1): RAM data = "0" lighted RAM data = "1" not lighted 7.7 Segment Display Output Order/Reverse Set up The order of display output, SEG0 to SEG100 can be reversed. If REF control bit set to "1", display by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing IC when assembling an LCD panel module. 2005/3/8 (V0.6) 19
Y-address
The addresses, X Address and Y Address are possible to be set up so that they can increment automatically with the address control register. The increment is made every time display RAM is read or written from MPU. In the Y-direction, 208 bits of data are read out to the display data latch circuit by internal operation when the LP rises in a one-line cycle. They are output from the display data latch circuit when the LP fails. When FLM signals being output in one frame cycle are at "H", the values in the display starting line register are preset in the line counter and the line counter counts up at the falling of LP signals. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of address counters X and Y.
7.6 Display RAM Data and LCD (only monochrome mode) One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are set up as follows. Normal display (REV=0): RAM data = "0" not lighted
* This specification is subject to be changed without notice.
EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.8 Relationship between Display RAM and Address The Display RAM block diagram shows in the figure below:
Bit-order reverse W rite:depend on REF Read:depend on REF
Internal Data Bus Data Conversion Bit order reverse
Read Data Segm ent data
SEGMENT Output I/F Data conversion is depend on MON,,REF
Display start address
W rite Data Effective Y address
MPU I/F
The EM65100 execute address conversion that depends on control register setting. In case of auto increment mode, usually AX register is added one. For instance when REF and AXI are both "1", AX register is added one, but effective X address seems decrement because of address conversion. The effective Y address use AY register values as it is.
* This specification is subject to be changed without notice.
AY Register
Display RAM
X-Address (00H~19H)
Effective X address
Address conversion circuit
Address conversion is depend on M ON,REF setting Valid m aximum is depend on M ON setting
AX Register
Figure 10. The Display RAM block diagram
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LA Register
Y-Address (00H~44H)
Counter
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(1) Monochrome mode, 8-bits Access mode
X Address REF=1 REF=0 X =0CH X = 00H X =0BH X = 01H --------X = 00H X = 0CH Common Output
Display Start Line
* This specification is subject to be changed without notice.
Y Address
Note 1 D6 D7 D4 D5 D2 D3 D0 D1 D6 D7 D4 D5 D2 D3 D0 D1 ----- D6 D7 D4 D5 D2 D3 D0 D1 Note 2 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ----- D0 D1 D2 D3 D4 D5 D6 D7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H Segment Output ------------------------------00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------Line Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 ------------
-----
3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H
COM61 COM62 COM63 COM64 COM65 COM66 COM67 COMA COMB
SEG100
SEG99
Note1: REF=1 Note2: REF=0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
-----
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(2)Gradation mode, 8 bits access mode, REF =0
X Address X = 00H 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H Segment SEG100 SEG99 Output SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 ------------------------------X = 01H ----X = 19H Y Address
Common Output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ----- D0 D1 D2 D3 D4 D5 D6 D7
Display Start Line
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------Line Address
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 ------------
-----
3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H
COM61 COM62 COM63 COM64 COM65 COM66 COM67 COMA COMB
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.9 Display Data Structure and Gradation Control For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65100 has 2-bit data per output to achieve the gradation display. The EM65100 is connected to an STN LCD panel. It can display 101*69 pixels with 4-gray level. In this case, since the gradation display data is processed by a single access to the memory, the data can be rewritten fast and naturally. The weighting for each data bit is dependent on the status of the REF bit that is selected when data is written to the display RAM.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
REF=0
SEGi
SEGi+1
SEGi+2
SEGi+3
i=0 to 100
palette j
palette j
palette j
palette j
Gradation palette j=0 to 3
Gradation control
0
LSB
0
M SB
0
LSB
1
MSB
1
LSB
0
M SB
1
LSB
1
M SB
display RAM data
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU write data X address: nH
Note : Internal X address : nH : 19H-nH
(REF="0") (REF="1")
REF=1
SEGi+3
SEGi+2
SEGi+1
SEGi
i=0 to 100
palette j
palette j
palette j
palette j
Gradation palette j=0 to 3
Gradation control
1
LSB
1
M SB
0
LSB
1
M SB
1
LSB
0
M SB
0
LSB
0
M SB
Display RAM data
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU write data X address: nH
Note : Internal X address : nH : 19H-nH
(REF="0") (REF="1")
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.10 Gradation Palette The EM65100 has two gradation display modes, the gradation fixed display mode and the gradation variable display mode. Select either of the two modes using the gradation display mode register. PWM = "0": Selects the variable display mode using 4 gradation selected from 16 gradation. PWM = "1": Selects the fixed display mode using specific 4 gradation. To select the best gradation level suited to the LCD panel, use the gradation palette register among the 16-level gradation palettes in the gradation variable display mode. The segment driver output is set up by the selected 4-levels of gradation palettes. Each register consists of a 2-bit register, selecting 4-gradations from the pattern for 16-gradations. Initial values on gradation palette register [Three groups of palettes WAj~WDj, LAj~LDj, DAj~DDj, and BAj~BDj are available] (MSB) RAM data (LSB) 0 0 0 1 1 0 1 1 Register Name Gradation Palette 0 Gradation Palette 1 Gradation Palette 2 Gradation Palette 3 Initial value 0000 0101 1010 1111
Gradation level table (PWM = "0", variable mode) [Three groups of palettes WAj~WDj, LAj~LDj, DAj~DDj, and BAj~BDjand Cj (j=0-3) are available]
Palette 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Gradation level 0 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 15/15
Remark Gradation palette 0
Gradation palette 1
Gradation palette 2
Gradation palette 3
Caution: Different gradation levels can't be set in the same palette.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Gradation level table (PWM = "1", fixed mode) (MSB) RAM data (LSB) 0 0 0 1 1 0 1 1 7.11 Display Timing Circuit The display timing circuit generates internal signals and timing pulses (internal LP, FLM, M) by clock. It can select external input (CK) or internal oscillation. Description The LP is latch clock signal. LP(internal) At the rising edge, count the display line counter. At the falling edge output the LCD drive signal. The signal for LCD display synchronous signals (first line maker). FLM(internal) When FLM is set to "H", the display start-line address is preset. In the display line counter M(internal) The signal for alternated signals of LCD drive output. Symbol Gradation level 0 1/3 2/3 3/3
7.12 Signal Generation to Display Line Counter, and Display Data Latching Circuit Both the clock to the line counter and clock to display data latching circuit from the display clock (internal LP) are generated. Synchronized with the display clock (internal LP), the line addresses of Display RAM are generated and 208-bits display data are latched to display data latching circuit to output to the LCD drive circuit (Segment outputs). Read-out of the display data to the LCD drive circuit is completely independent of MPU. Therefore, MPU that has no relationship the read-out operation of the display data can access.
7.13 Generation of the Alternated Signal (internal M) and the Synchronous Signal (internal FLM) LCD alternated signal (internal M) and synchronous signal (internal FLM) are generated by the display clock (internal LP). The FLM generates alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame (M-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1", n-line reverse waveform is generated.
7.14 Display Data Latching Circuit Display data latching Circuit temporally latches display data that is output display data to LCD driver circuit from display RAM every one common period. Normal display/reverse display, display ON/OFF, and display all on functions are operated by controlling data in display data latch. Therefore, no data within display RAM changes.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.15 Output Timing of LCD Driver Display timing at Normal mode (not reverse mode), 1/69 DUTY, and on monochrome mode.
68 LP(internal) FLM(internal) M(internal)
69
1
2
3
69
1
2
3
69
1
COM0
COM1
SEG0
SEG1
7.16 LCD Drive Circuit This drive circuit generates four levels LCD drive voltage. The circuit has 101 segment outputs and 69 common outputs and outputs combined display data and M signal. Two of common outputs, COMA and COMB, are special outputs. The COMA and COMB outputs be not influenced by partial setting. Mainly use for display. The common drive circuit that has shift register sequentially outputs common scan signals.
7.17 Oscillating Circuit The EM65100 has the CR oscillator. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster. This can use only in the master operation mode.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
When in the master operation mode and external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of CR oscillator is programmable. If change this ratio, also change frame frequency for display. 7.18 Power Supply Circuit This circuit supplies voltages necessary to drive a LCD. The circuit consists of booster and voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3 and V4 that are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels. Otherwise, display quality will degrade considerably. Instead, use an external power supply. When using the external power supply, turn off the internal power supply (AMPON, DCON="00"), disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, Vcc, Vci, VREF Then, feed external LCD drive voltages to pins V0, V1, V2, V3 and V4. The power circuit can be control by power circuit related register. So partial function of built-in power circuit can use with external power supply.
DCON AMPON Booster circuit Voltage conversion circuit 0 0 1 0 1 1 DISABLE DISABLE ENABLE DISABLE ENABLE ENABLE Extemal voltage input V0,V1,V2,V3 and V4 are supplied Vcc is supplied Note 1 2 -
1 Because the booster and voltage converter not operating, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+,, Vcc, Vci, and VREF. Apply external LCD drive voltages to corresponding pin. 2 Because the booster is not operating, disconnect pins CAP1+, CAP1-, CAP2+, CPA2-, CAP3+ Derive the voltage source to be supplied to the voltage converter from Vcc pin and then Input the reference voltage at VREF pin. 7.19 Booster Circuit Using the booster voltage circuit equipped within the EM65100 chip it is possible to product a four times step-up, and a three times , and two times step-up of the Vci voltage level. The twice, third, or fourth boosted voltage output to the Vcc pin by the boost step register set. The boost step registers set by the command.
(1) In case of using only twice boosted voltage, placing Capacitor across CAP1+ and CAP1-, and connect CAP2+ and CAP3+. (2) In case of using only third boosted voltage, placing Capacitor across CAP1+ and CAP1-, across CAP2+ and CAP2-. (3) In case of using only fourth boosted voltage, placing Capacitor across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
When use built-in booster circuit, output voltage (Vcc) must less than recommended operating voltage (12.0 Volt). If output voltage (Vcc) over recommended operating voltage, correct work of chip can not guarantee.
Vcc=12V
Vcc=9 V
Vci=3V
Vci=3V
VSS=0V 3 times boostng
VSS=0V 4 times boostng
7.20 Electronic volume The voltage conversion circuit has built-in an electronic volume, which allows the LCD drive voltage level V0 to be controlled with DV register setting and allows the tone of LCD to be controlled. The DV registers are 7-bits, so can select 128 voltage values for the LCD drive voltage V0.
7.21 Voltage Regulator The EM65100 has built-in reference voltage regulator, which generate the voltage amplified by input voltage from VREF pin. The generated voltage is output at the VREG (internal). Even if the boosted voltage level fluctuates, VREG (internal) remains stable so far as Vcc is higher than VREG Stable power supply can be obtained using this constant voltage, even if the load fluctuates. The EM65100 uses the generated VREG level for the reference level of the electronic volume to generate LCD drive voltage.
7.22 LCD Drive Voltage Generation Circuit The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, that is, V1, V2, V3 and V4 are obtained by dividing V0 through a resistor network. The LCD drive voltage from EM65100 is biased at 1/5, 1/6, 1/7, 1/8 or 1/9. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. When using the external power supply, apply external LCD drive voltages to V0, V1, V2, V3, V4, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, Vcc, Vci, and VREF. When using only the voltage conversion circuit, turn off the internal booster circuit, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, and Vci. Derive the voltage source to be supplied to the voltage converter from Vcc pin and then input the reference voltage to VREF pin.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
VDD VDD Vci VREF
VDD VDD Vci VREF
CAP1CAP1+ CAP2CAP2+ CAP3+ C1
C1 C1
CAP1CAP1+ CAP2CAP2+ CAP3+
C1 Vcc V0 V0 V1 V2 V3 V4 vss vss C2 C2 C2 C2 C2 Vcc V0 V1 V2 V3 V4
External V1 Power V2 Supply V3
V4
When using external power supply.
When using internal power circuit. (4 times boosting)
Recommended value.
C1 C2
1.0 to 4.7 F 1.0 to 2.2 F
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
VDD VDD Vci VREF
Thermistor
VDD VDD Vci VREF CAP1CAP1+ CAP2CAP2+ CAP3+
C1 C1 C1
CAP1CAP1+ CAP2CAP2+ CAP3+
C1 C1 C1
C1 vss C2 C2 C2 C2 vss C2 Vcc V0 V1 V2 V3 V4 vss vss
C1 Vcc V0 V1 V2 V3 V4
C2 C2 C2 C2 C2
When using internal power circuit with external reference voltage input. (4 times boosting)
When using internal power circuit with thermistor for temperature independt. (4 times boosting)
Recommended value.
C1 C2
1.0 to 4.7 F 1.0 to 2.2 F
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
VDD VDD Vci VREF
CAP1CAP1+ CAP2CAP2+ CAP3+
External Power Supply C2 C2 C2 C2 vss C2
Vcc V0 V1 V2 V3 V4
When using internal power circuit. (Vcc supplied from external, no use boosting circuit) Recommended value.
C2
1.0 to 2.2 F
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.23 Partial Display Function The EM65100 has the partial display function, which can display a part of graphic display area. This function is used be set lower bias ratio, lower boost step, and lower LCD drive voltage. Since setting partial display function, EM65100 provides low power consumption. Partial display function is the most suitable for clock indication or calendar indication when a portable equipment stand-by.
ELAN LCD DRIVER Low Power and Low Voltage Normal Display Image of partial Display When using the partial display function, it is necessary to keep following sequence.
Any display condition Display off (ON/OFF= "0") Power circuit off (DCON= "0", AMPON= "0") W AIT
LCD DRIVER
Partial Display
Setting Power Function * Boost step set * Electronic volume set * Bias Ratio set
Power circuit on (DCON= "1", AM PON= "1") W AIT
Setting Display Function * Duty Ratio set * Display start Address * Display start common
Display on (ON/OFF= "1") Partial Display
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Select a display duty ratio for the partial display from 1/10, 1/18, 1/26, 1/34, 1/42, 1/50 and 1/58 using the DS(LCD duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and others according to the actually used LCD panel and the selected duty ratio. 7.24 Discharge circuit The EM65100 has built-in the discharge circuit, which discharges electricity from capacitors for a stability of power sources(V0~V4). The discharge circuit is valid, while the DIS register is set to "1" or the RESB pin is set "L". When the built-in power supply is used, should be set DIS="1" after the power source is turned off (DCON, AMPON)=(0, 0). And don't turn on both the built-in power source and the external power source (V0~V4, Vcc) while DIS="1".
7.25 Initialization The EM65100 is initialized by setting RESB pin to "L". Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power ON, be sure to make RESB="L".
ITEM Display RAM X Address Y Address Display starting line Display ON/OFF Display Normal/Reverse Display duty n-line alternated Common shift direction Increment mode REF mode Register in electronic volume Power Supply Display mode Bias ratio Gradation palette 0 Gradation palette 1 Gradation palette 2 Gradation palette 3 Gradation display mode RAM access data length Discharge Register Booster frequency Static Pictograh
Initial value Not fixed 00H set 00H set Set at the first line(0H) Display OFF Normal 1/69 every frame unit COMOCOM67, COMA, COMB Increment OFF Normal (0,0,0,0,0,0,0) OFF Gradation display mode 1/9 bias (0, 0, 0, 0, 0) (0, 0, 1, 0, 1) (0, 1, 0, 1, 0) (0, 1, 1, 1, 0) Variable mode 8-bits mode "0" (0,0) OFF
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
7.26 Precaution when Power ON and Power OFF This LSI may be permanently damaged by high current that may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating. The detail is as follows.
( i )When using as external power supply Procedure for Power ON (1) Logic system (VDD) power ON, make reset operation. (2) Supply external LCD drive voltage to corresponding pins (V0, V1, V2, V3 and V4) Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Cut off external LCD drive voltage. (3) Logic system(VDD) power OFF. Note: connect the serial resistor (50 to 100) or fuse to the LCD drive power V0 or Vcc(when only use internal voltage conversion circuit) of the system as a current limiter. Moreover, set up the suitable value of the resistor in consideration of LCD display grade. ( ii )When using the built-in power supply Procedure for Power ON (1) Logic system (VDD) power ON (2) Booster circuit system (Vci) power ON (3) Make reset operation, booster and voltage conversion circuit enable. If VDD and Vci voltages aren't same potential, power on logic system (VDD) first. Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Booster circuit system (Vci) power ON (3) Logic system (VDD) power OFF. If VDD and Vci are not same potential, cut off Vci first. After Vci, Vcc, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for Liquid crystal turn on), power off logic system (VDD).
( iii )Power supply rising time Though especially there is no constraint on the rising time of the power supply, the tr (rising time) of the following is recommended in the practical use.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
VDD,Vci tr
Item tr
Recommended rising time 30us ~ 10ms
Applicable Power VDD, Vci
Note: The rising time is the time from 10% of VDD, VEE to 90%. 7.27 Example of Setting Registers (1) Initialization
Power ON (VDD,Vci-VSS) Power will stable RESET W AIT
Setting Operational Functions * Electrical volume set * Bias Ratio set
Setting Operational Functions * Setting power control (DCON= "1", AMPON= "1")
End of initialization
If VDD and Vci voltage are not same, connect the logic system power supply (VDD) first.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(2) Display data
End of initialization
* * * *
Setting Operational Functions Setting display start address Setting address increment control Setting X address Setting Y address
Setting Operational Functions * W rite dsiplay data
Setting Operational Functions * Setting display on/off control (ON/OFF= "1")
End of initialization
(3) Power OFF
Any condition
Setting Operational Functions * Setting HALT= "1" or make reset operation (LCD driver output VSS level) * Setting DIS= "1" (Discharge V0-V4 capacitor)
W AIT
Power OFF ( Vci,VDD)
When turning off the power, set HALT command or make reset operation. If VDD and Vci voltage are not same, disconnect the booster circuit power supply (Vci) first.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
PROGRAM EXAMPLES
Use Elan Risc MCU assembly
;***************************************************************************** ; INITIALIZATION SETTING EXAMPLE OF EM65100 ;***************************************************************************** WRITEOR macro REGSEL,INSDAT ; Write macro MOV OR CALL endm EM65100_INI: WRITEOR WRITEOR MOV CALL WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR WRITEOR RET #REREGISTERSET,#0b00000000 #POWERCONTROL,#0b00000001 ; A,#50 WAIT_A_MS #BOOSTERSET,#0b00000011 # POWERCONTROL,#0b00001010 #BIASRATIOCONTROL,#0b00000000 #LCDDUTYSET,#0b00000000 #INCREMENTCONTROL,#0b00000011 ;BOOSTER x 4 (B1,B0=1,1) ;BOOSTER CIRCUIT(B1) ON,OPAMP(B3) ON ;BIAS=1/9(B2,B1,B0=000) ;LCD DUTY SET 1/69 DUTY(B2,B1,B0=000) ;X INCREMENT(B0),Y INCREMENT(B1) ;SET DISPLAY START LOWER LINE=0 ;SET DSIPLAY START UPPER LINE=0 ;SET RE FLAG 000--> INSTRUCTION bank 0 ;SET ACL(B0)=1 initialization ON ;WAIT 50ms FOR EM65100 INITIAL SETTING A,INSDAT A,REGSEL WRITE_LCD_1BYTE ; Write data ; Write register address ;Write A to LCD
#DISPLAYSTARTLINELOWER,#0b00000000 #DISPLAYSTARTLINEUPPER,#0b00000000 #XADDRESSLOWER,#0b00000000 #XADDRESSUPPER,#0b00000000 #YADDRESSLOWER,#0b00000000 #YADDRESSUPPER,#0b00000000 #DISPLAYCONTROL1,#0b00000000 #REREGISTERSET,#0b00000010
;SET X ADDRESS=0 ;SET Y ADDRESS=0 ;DISPLAY(B0) OFF ; SHIFT(B3) = '0' ;SET RE FLAG 010--> INSTRUCTION bank 2
#ELECTRONICVOLUMEUPPER,#0b00000111 ;SET ELECTRONIC UPPER TO MAX 0111 #ELECTRONICVOLUMELOWER,#0b00001111 ;SET ELECTRONIC LOWER TO MAX 1111 #COMMONSTARTLINESET,#0b00000000 ;SET COMMON START FROM COM 0 (B2,B1,B0=000) #STATICPICTGRAPHCONTROL,#0b00000000 ;Static Pictograph Control =000 #DISPLAYSELECTCONTROL,#0b00001000 ;PWM (B3)=1 4-gradation fixed display #DISCHARGECONTROL,#0b00000000 ;Discharge(B0) off; High power mode(B1) off #REREGISTERSET,#0b00000000 ;SET RE FLAG 000--> INSTRUCTION bank 0
* This specification is subject to be changed without notice.
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***************************************************************************** ; WRITE DISPLAY_PICTURE DATA INTO DISPLAY DATA RAM OF EM65100 ;***************************************************************************** DATA_WRITE_65100: BS REG_PORTB,RS ; LCD RS = 1 INSTRUCTION OUTPUT ;SET X Add=0 ;SET Y Add=0 ;COMMON = 44H (68) WRITEOR #XADDRESSLOWER,#0b00000000 WRITEOR #XADDRESSUPPER,#0b00000000 WRITEOR #YADDRESSLOWER,#0b00000000 WRITEOR #YADDRESSUPPER,#0b00000000 MOV MOV MOV MOV BC TBRD CALL DEC JBS DEC JBS BS RET ;***************************************************************************** ; WRITE ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES) ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_1BYTE: BC BC MOV BS BS RET PORTB,CSB1 PORTB,WRB PORTC,A PORTB,WRB PORTB,CSB1 ;SET CSB LOW ;SET /WR=0 ENABLE WRITE ;MOVE A==> PORT_C ;SET /WR=1 DISABLE WRITE ;SET CSB1 HIGH A,#LINE_Y_MAX DRAMY,A A,#LINE_X_MAX DRAMX,A REG_PORTB,RS 01,REG_ACC WRITE_LCD_1BYTE DRAMX REG_STATUS,F_C,DATA_W2 DRAMY REG_STATUS,F_C,DATA_W1 REG_PORTB,RS ;LCD RS = 1 INSTRUCTION OUTPUT ;SET LCD RS=0 DATA READ/WRITE ;WRITE LCD SCREEN FROM DATA INDEX ;SEGMENT = 19h (25)
DATA_W1:
DATA_W2:
* This specification is subject to be changed without notice.
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;***************************************************************************** ; ; READ ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES) ; ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC PORTB,CSB1 BC PORTB,RDB MOV A,PORTC BS PORTB,RDB BS PORTB,CSB1 RET ;SET CSB LOW ;SET /RD=0 READ ENABLE ;MOVE PORT_C ==> A ;SET /RD=1 READ DISABLE ;SET CSB HIGH
* This specification is subject to be changed without notice.
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8. Control Register
8.1 control register Control Register Table (Bank 0)
Control Register Display Data write Display Data read Internal Register read X Address (Lower nibble) X Address (Upper nibble) Y Address (Lower nibble) Y Address (Upper nibble) Display start address (Lower nibble) Display start address (Upper nibble) n-line altemation (Lower nibble) n-line altemation (Upper nibble) Display control (1) Pins (for 80-family) & Bank CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 0 0 0 1 0/1 0/1 0/1 0 0 1 0 0/1 0/1 0/1 0 1 1 0 0/1 0/1 0/1 * * * [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Address & Code D4 D3 D2 D1 Write Data Read Data * Read Data 0 AX3 1* 0 AY3 1* 0 LA3 1* 0 N3 1* Function Write to Display RAM Read from Display RAM Read out Internal Register Set of X direction Address AX2 AX1 AX0 in display RAM Set of X direction Address * * AX4 in display RAM Set of X direction Address AY2 AY1 AY0 in display RAM Set of X direction Address AY6 AY5 AY4 in display RAM Set address of display RAM LA2 LA1 LA0 making common starting line display Set address of display RAM LA6 LA5 LA4 making common starting line display Set the number of altemated N2 N1 N0 reverse line Set the number of altemated N6 N5 N4 reverse line SHIFT: Select common shift direction MON: Select Monochrome/gradation ALL ON/ ALLON: All display ON MON ON OFF ON/OFF: Display ON/OFF control REV: Display normal/reverse NLIN: n line reverse control REF REF: Seqment normal/reverse AIM: Select increment mode AYI AXI AYI: Y increment, AXI: X increment AMPON: Intemal AMP. ON HALT: Power saving DC DCON: Boosting circuit ON ON ACL ACL: Resetting Set LCD drive duty ratio DS1 DS0 Set number of boosting step for VU1 VU0 booster circuit Set bias ratio B1 B0 for LCD driving voltage TST0: for LS1 test,must set to "0" RE1 RE0 RE: set register bank number D0
[8H] Display control (2)
0
1
0
1
0
0
0
1
0
0
SHI 0 FT
[9H] Increment control [AH] Power control
0 0
1 1
0 0
1 1
0 0
0 0
0 0
1 1
0 0
0 1
1 REV NLIN * 0* AIM
[BH] LCD Duty Ratio [CH] Booster [DH] Bias ratio control [EH] Register Access Control [FH]
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1 0/1
0 0 0 0 0/1
0 0 0 0 0/1
0 0 0 0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
AMP HA 1 ON LT 0* 1* 0* TS 1 T0 DS2 * B2 RE2
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
Control Register Table (Bank 1)
Control Register Gray Mode--White 1stFR Gray Mode--White 2ndFR Gray Mode--White 3rdFR Gray Mode--White 4thFR Gray Mode--Light Gray 1stFR Gray Mode--Light Gray 2ndFR Gray Mode--Light Gray 3rdFR Gray Mode--Light Gray 4thFR Gray Mode--Dark Gray 1stFR Gray Mode--Dark Gray 2ndFR Gray Mode--Dark Gray 3rdFR Gray Mode--Dark Gray 4thFR Gray Mode--Black 1stFR Gray Mode--Black 2ndFR Register Access Control [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] [DH] [FH] Pins (for 80-family) & Bank Address & Code D2 WA2 WB2 D1 WA1 WB1 D0 WA0 WB0 CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 WA3 1 WB3 Function Set White 1st frame Set White 2nd frame
0 WC3 WC2 WC1 WC0 Set White 3rd frame 1 WD3 WD2 WD1 WD0 Set White 4th frame 0 LA3 1 LB3 0 LC3 1 LD3 0 DA3 1 DB3 0 DC3 1 DD3 0 BA3 1 BB3 TS 1 T0 LA2 LB2 LC2 LD2 DA2 DB2 DC2 DD2 BA2 BB2 RE2 LA1 LB1 LC1 LD1 DA1 DB1 DC1 DD1 BA1 BB1 RE1 LA0 LB0 LC0 LD0 DA0 DB0 DC0 DD0 BA0 BB0 RE0 Set Light Gray 1st frame Set Light Gray 2nd frame Set Light Gray 3rd frame Set Light Gray 4th frame Set Dark Gray 1st frame Set Dark Gray 2nd frame Set Dark Gray 3rd frame Set Dark Gray 4th frame Set Back 1st frame Set Back 2nd frame TST0: for LS1 test,must set to "0" RE: set register bank number
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register. Caution: Different gradation levels can't be set in the same palette.
* This specification is subject to be changed without notice.
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Control Register Table (Bank 2)
Control Register Gray Mode--Black 3rdFR Gray Mode--Black 4ndFR Display start common Static Pictograph control [7H] Display Select Control [8H] Electronic Volume (Lower nibble) Electronic Volume (Upper nibble) Register read Control Select Rf [DH] Extended power control 0 1 0 1 0 1 0 1 1 0 1* RF2 RF1 RF0 DIS:Discharge capacitance of V0,V1,V2,V3,V4 Pins HPM : high power mode set BF: Set Booster frequency TST0: for LS1 test,must set to "0" RE: set register bank number [AH] [BH] [CH] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 PWM * 0 DV3 1* 0 RA3 DV2 DV6 RA2 * DV1 DV5 RA1 * DV0 DV4 RA0 Select Rf ratio of OSC circuit Select PWM Mode Set Electronic Volume Register (lower code) Set Electronic Volume Register (upper code) Set Register Address for read 0 1 0 1 0 1 0 0 1 1 1* * [0H] [1H] [6H] 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 BC3 1 BD3 0* BC2 BD2 SC2 BC1 BD1 BC0 BD0 Set Back 3d frame Pins (for 80-family) & Bank Address & Code D2 D1 D0 CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 Function
Set Back 4th frame Set Common Driver SC1 SC0 Start Line Set Static Pictgraph SPC1 SPC0 Drive Mode
[EH] Register Access Control [FH]
0 0
1 1
0 0
1 1
0 0/1
1 0/1
0 0/1
1 1
1 1
1 1
0 BF1 TS 1 T0
BF0 RE2
HPM DIS RE1 RE0
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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8.2 Functions of Control Registers The EM65100 has many control registers. In case of control register access, upper nibble of data bus (D7~D4) represent register address, lower nibble of data bus (D3~D0) represent data. The access example is shown in the following. The Pins (CSB, RS, RDB, WRB) setting are for 80-family MPU interface. Only the setting of terminal (RDB,WRB) is different, when it is accessed by the 68-fanily MPU. (Example) X Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 AX3 AX2 AX1 AX0 Data CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
Register address
Pins setting
Register Bank
In the writing to the control register, it is used directly as addressing D7~D4 of the data bus. In case of register read, first set RA register for specific register address, next can read specific register. Therefore, it is need 2-step for register read. Then, specific register output to D3~D0 of data bus. Except D3~D0 of data bus are all "H". Prohibit access to undefined register address area. When RS is "L", all read/write operations are accessed to display RAM. Then data bus doesn't include register address. In case of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the WRB signal. In case of read, register can output to data bus is RDB active period. Control register and display RAM are the equal access timing. 8.2.1 Data Write to Display RAM
D7 D6 D5 D4 D3 D2 Display RAM write data D1 D0 CSB 0 RS 0 RDB WRB RE2 1 0 0/1 RE1 0/1 RE0 0/1
The Display RAM data of 8-bit are written in the designated X and Y address. 8.2.2 Data Read from Display RAM
D7 D6 D5 D4 D3 D2 Display RAM read data D1 D0 CSB 0 RS 0 RDB WRB RE2 0 1 0/1 RE1 0/1 RE0 0/1
The 8-bit contents of Display RAM designated in X. and Y address and read out. Immediately after data are set in X and Y address, dummy read is necessary one time. 8.2.3 Internal Register Data Read
D7 D6 D5 D4 D3 D2 D1 D0 Internal Register read data CSB 0 RS 1 RDB WRB RE2 0 1 0/1 RE1 0/1 RE0 0/1
Mark shows "Don't care" This command is used to read data from an internal register. Before executing the command. You need to set the address and RE flag for reading data from the internal register.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
8.2.4 X Address Register Set
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 AX4 CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
(At the time of reset: {AX4}= 0H, read address: 1H) Mark shows "Don't care" The AX register set to X-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 1-bit respectively. Be sure to do setting from the lower bit. 8.2.5 Y Address Register Set
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
AY3 AY2 AY1 AY0
CSB 0
RS 1
RDB WRB RE2 1 0 0
RE1 0
RE0 0
(At the tine of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
1
0
AY6 AY5 AY4
0
1
1
0
0
0
0
(At the time of reset: {AY6, AY5, AY4}=0H, read address: 3H) Mark shows "Don't care" The AY register set to Y-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 3-bit respectively. 00H to 44H are applicable to the values for AY6 to AY0, and 45H to FFH are not permitted. The address for (AY6 to AY0) = 43H, 44H are in the display RAM area for icon display.
8.2.6 Display Start Address Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
0
LA3
LA2
LA1
LA0
0
1
1
0
0
0
0
(At the tine of reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
LA6
LA5
LA4
0
1
1
0
0
0
0
(At the time of reset: {LA6,LA5, LA4}=0H, read address: 5H) Mark shows "Don't care" This display line address is require to designate, and the designated address becomes the display line of COM0. The display of LCD panel is indicated in the increment direction of the designated display starting address to the line address.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
LA6 0 0
LA5 0 0
LA4 0 0
1
0
0
LA3 0 0 0
LA2 0 0
LA1 0 0
LA0 0 1
Line Address 0 1
0
1
0
66
8.2.7 n Line Alternated Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
N3
N2
N1
N0
0
1
1
0
0
0
0
(At the tine of reset: {N3, N2, N1, N0}=0H, read address: 6H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
1
N6
N5
N4
0
1
1
0
0
0
0
(At the time of reset: {N6, N5, N4}=0H, read address: 7H) Mark shows "Don't care" The reverse line number of LCD alternated drive is required to set in the register. The line number has a limit, must keeps between from 2 to 67 lines. The values set up by the alternated register become enable when NLIN control bit is "1". When NLIN control bit is "0", alternated drive waveform reverses by each frame is generated.
N6 0 0
N5 0 0
N4 0 0
1
0
0
N3 0 0 0
N2 0 0
N1 0 0
N0 0 1
Line Address 2
0
1
0
67
Alternated Timing
(i)
NLIN="0" (in case of 1/69 DUTY Display)
1st Line 2nd Line 3rd Line 68st Line 69th Line 1st Line
LP
FLM
M
* This specification is subject to be changed without notice.
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(ii)
NLIN="1"
nth line Cycle
1st Line
2nd Line
3rd Line
nth Line
1st Line
2nd Line
LP
M
8.2.8 Display Control (1) Register Set
D7 D6 D5 D4
1
0
0
0
SHIF ALL T MON ON
D3
D2
D1
D0
CSB
RS
RDB WRB
RE2
RE1
RE0
ON/ OFF
0
1
1
0
0
0
0
(At the tine of reset: {SHIFT, MON, ALLON, ON/OFF}=0H, read address: 8H) Various control of display is set up.
ON/OFF
To control ON/OFF of display ON/OFF = "0": Display OFF ON/OFF = "1": Display ON
ALLON
Regardless of the data for display, all is on. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display lighted
MON
Select Monochrome or Gradation display MON = "0": Gradation display mode MON = "1": Monochrome display mode
SHIFT
The shift direction of display scanning data in the common driver output is selected. SHIFT = "0": COM0 COM66 shift-scan SHIFT = "1": COM66 COM0 shift-scan
* This specification is subject to be changed without notice.
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8.2.9 Display Control (2) Register
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
REV NLIN
REF
0
1
1
0
0
0
0
(At the tine of reset: {REV, NLIN, REF}=0H, read address: 9H) Mark shows "Don't care" Various control of display is set up.
REF
When MPU accesses to display RAM, the X address and data can reverse. The REF function shows in the table below: The order of segment driver output can be reversed by register by register setting, lessening the limitation in placing IC when assembling a LCD module.
NLIN
The NLIN control n-line alternated drive. NLIN = "0": n-line alternated drive OFF. In each frame, the alternated signals (internal M) are reversed. NLIN ="1": n-line alternated drive ON. According to data set up in n-line alternated register, the alternation is made.
REV
Corresponding to the data of display RAM, the lighting or not-lighting of the display is set up. REV ="0": When RAM data at "H", LCD at ON voltage (normal) REV ="1": When RAM data at "L", LCD at ON voltage (reverse)
8.2.10 Increment Control Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
0
AIM
AYI
AXI
0
1
1
0
0
0
0
Mark shows "Don't care" (At the tine of reset: {AIM, AYI, AXI}=0H, read address: AH) The increment mode is set up when accessing to display RAM. By AIM, AYI, AXI register, the setting up of increment operation/non-operation for the X address counter and the Y address counter every write access or every read access to display RAM is possible. In setting to this control register, the increment operation of address can be made without setting successive address for writing data or for reading data to display RAM from MPU.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
After the increment control register has been set. be sure to assign address to the X and Y address registers starting from the lowest bit. Because it is not assuring the data of X and Y address register after setting increment control register. The increment control of X and Y address by AIM, AYI, AXI registers is as follows.
AIM Address Increment Timing When writing to Display RAM or reading from Display RAM This is effective when access to successive address area Only when writing to Display RAM This is effective the case of "Read Modify Write
0 1
AYI 0 0 1 1
AXI 0 1 0 1
Select Address Increment Operation Address is not increment X-Address is increment Y-Address is increment X and Y both are increment
Remark (1) (2) (3) (4)
(1) Regardless of AIM, no increment for AX and AY register. (2) According to the setting-up of AIM, automatically change X address. In accordance with the REF register, AX register and X address becomes as follows.
REF 0
Transition of AX Register
Transition of X Address Same as AX register
00H
1
01H
.......
max max maxH ..... 00H
Note: maxH: The internal maximum X-address in each access mode. (3) According to the setting-up of AIM, automatically change Y address. Regardless of REF, increment by loop of
Transition of AY Register
00H
01H
.......
44H
Transition of Y Address Same as AY register
(4) According to the setting-up of AIM, cooperative change X and Y address. When the X address exceed maxH, Y address increment occurs.
REF 0
Transition of AX and AY Register
AX: 00H 00H max AY: When each AX exceed maxH, increment AY 00H 00H 44H
Transition of X and Y Address Same as AX and AY register
AX: max AY: maxH 00H
1
Same as AY register
Note: maxH: The internal maximum X-address in each access mode.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
In each operation mode, the following increment operation is performed: (i) (ii) When gradation display mode and 8-bit access are selected: Address are incremented as described above. When monochrome display mode and 8-bit access are selected: In the monochrome display mode, 0H to 19H are available for X-addresses in the access area.
8.2.11 Power Control Register
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
1
AMP HAL DCO ACL ON T N
0
1
1
0
0
0
0
(At the tine of reset: {AMPON, HALT, DCON, ACL}=0H, read address: BH)
ACL
The internal circuit can be initialized. ACL = "0": Normal operation ACL = "1": Initialization ON When the reset operation begins internally after ACL register sets to "1", the ACL register is automatically cleared to "0". The internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle. Since built-in oscillation circuit ,the setting of the ACL register becomes the invalidity.
DCON
The internal booster circuit is set ON/OFF DCON = "0": Booster circuit OFF DCON="1": Booster circuit ON
HALT
The conditions of power saving are set ON/OFF by this command. HALT = "0": Normal operation HALT="1": Power-saving operation When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current.
* This specification is subject to be changed without notice.
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The internal condition at power saving are as follows. (a) (b) (c) (d) (e) The oscillating circuit and power supply circuit are stopped. The LCD drive is stopped, and output of the segment driver and common driver are VSS level. The clock input from CK pin is inhibited. The contents of Display RAM data are maintained. The operational mode maintains the state of command execution before executing power saving command.
AMPON Command
The internal OP-AMP circuit block (voltage regulator, electronic volume, and voltage conversion circuit) is set ON/OFF by this command. AMPON = "0": The internal OP-AMP circuit OFF AMPON = "1": The internal OP-AMP circuit ON
8.2.12 LCD Duty Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
0
DS2
DS1
DS0
0
1
1
0
0
0
0
(At the time of reset: {DS2, DS1, DS0}=0H, read address: CH)
Mark shows "Don't care"
The DS register set to LCD display duty.
DS2 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 Display width and Duty 67-dot width display in Y-direction, 1/69 duty 56-dot width display in Y-direction, 1/58 duty 48-dot width display in Y-direction, 1/50 duty 40-dot width display in Y-direction, 1/42 duty 32-dot width display in Y-direction, 1/34 duty 24-dot width display in Y-direction, 1/26 duty 16-dot width display in Y-direction, 1/18 duty 8-dot width display in Y-direction, 1/10 duty
Partial display can be made possible by setting an arbitrary duty ratio.
8.2.13 Booster Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
1
VU1
VU0
0
1
1
0
0
0
0
(At the time of reset: { VU1, VU0}=0H, read address: DH)
Mark shows "Don't care"
* This specification is subject to be changed without notice.
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The booster steps set to VU register
VU1 0 0 1 1 VU0 0 1 0 1 Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output
8.2.14 Bias Setting Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
0
B2
B1
B0
0
1
1
0
0
0
0
(At the time of reset: {B2, B1, B0}=0H, read address: EH)
Mark shows "Don't care"
This register is used to set a bias ratio. A bias ratio can be selected from 1/9, 1/8, 1/7, 1/6, and 1/5 by setting B2, B1, and B0.
B2 0 0 0 0 1 1 1 1
D7 D6
B1 0 0 1 1 0 0 1 1
D5
B0 0 1 0 1 0 1 0 1
D4
Bias
1/9 Bias 1/8 Bias 1/7 Bias 1/6 Bias 1/5 Bias Prohibit code Prohibit code Prohibit code
D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
8.2.15 Register Access Control
1 1 1 1 TST0 RE2 RE1 RE0 0 1 1 0 0/1 0/1 0/1
(At the time of reset: {TST0, RE2, RE1, RE0}=0H, read address: FH)
Mark shows "Don't care"
The RE register set to number of register bank. Access to each control register, set RE register at first.
The TST0 register use for test of LSI, Therefore this register must be set to "0" 8.2.16 FRC(Frame Rate Control) and PWM(Pulse Width Modulation) control Register data Caution: Different gradation levels can't be set in the same palette. Gray Mode--White
D7 D6 D5 D4
0
0
0
0
D3 WA3
D2 WA2
D1 WA1
D0 WA0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 0H) (At the time of reset: WA3~WA0 = "0000")
* This specification is subject to be changed without notice.
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D7
D6
D5
D4
0
0
0
1
D3 WB3
D2 WB2
D1 WB1
D0 WB0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 1H) (At the time of reset:WB3~WB0 = "0000")
D7
D6
D5
D4
0
0
1
0
D3 D2 D1 WC3 WC2 WC1
D0 WC0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 2H) (At the time of reset:WC3~WC0 = "0000")
D7
D6
D5
D4
0
0
1
1
D3 D2 D1 WD3 WD2 WD1
D0 WD0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 3H) (At the time of reset:WD3~WD0 = "0000")
Gray Mode--Light gray
D7 D6 D5 D4
0
1
0
0
D3 LA3
D2 LA2
D1 LA1
D0 LA0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 4H) (At the time of reset:LA3~LA0 = "0101")
D7
D6
D5
D4
0
1
0
1
D3 LB3
D2 LB2
D1 LB1
D0 LB0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 5H) (At the time of reset: LB3~LB0 = "0101")
D7
D6
D5
D4
0
1
1
0
D3 LC3
D2 LC2
D1 LC1
D0 LC0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 6H) (At the time of reset: LC3~LC0 = "0101")
D7
D6
D5
D4
0
1
1
1
D3 LD3
D2 LD2
D1 LD1
D0 LD0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 7H) (At the time of reset: LD3~LD0 = "0101")
* This specification is subject to be changed without notice.
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Gray Mode--Dark gray
D7 D6 D5 D4
1
0
0
0
D3 DA3
D2 DA2
D1 DA1
D0 DA0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 8H) (At the time of reset: DA3~DA0 = "1010")
D7
D6
D5
D4
1
0
0
1
D3 DB3
D2 DB2
D1 DB1
D0 DB0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: 9H) (At the time of reset: DB3~DB0 = "1010")
D7
D6
D5
D4
1
0
1
0
D3 DC3
D2 DC2
D1 DC1
D0 DC0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: AH) (At the time of reset: DC3~DC0 = "1010")
D7
D6
D5
D4
1
0
1
1
D3 DD3
D2 DD2
D1 DD1
D0 DD0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: BH) (At the time of reset: DD3~DD0 = "1010")
Gray Mode--Black
D7 D6 D5 D4
1
1
0
0
D3 BA3
D2 BA2
D1 BA1
D0 BA0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: CH) (At the time of reset: BA3~BA0 = "1111")
D7
D6
D5
D4
1
1
0
1
D3 BB3
D2 BB2
D1 BB1
D0 BB0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(Read address: DH) (At the time of reset: BB3~BB0 = "1111")
D7
D6
D5
D4
0
0
0
0
D3 BC3
D2 BC2
D1 BC1
D0 BC0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
1
0
(Read address: 0H) (At the time of reset: BC3~BC0 = "1111")
* This specification is subject to be changed without notice.
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D7
D6
D5
D4
0
0
0
1
D3 BD3
D2 BD2
D1 BD1
D0 BD0
CSB
RS
RDB WRB
RE2
RE1
RE0
0
1
1
0
0
1
0
(Read address: 1H) (At the time of reset: BD3~BD0 = "1111") Set Gray Scale Mode RAM Data[2n:2n+1] are used to specify the four gray level's pulse width 2n 0 1 0 1 RAM DATA 2n+1 0 0 1 1 Gray Mode White Light Gray Dark Gray Black 1st WA LA DA BA 2nd WB LB DB BB frame 3rd WC LC DC BC 4th WD LD DD BD
These gradation palette register set up gradation level. The EM65100 has 16 gradation levels. Gradation level table [Three groups of palettes WAj~WDj, LAj~LDj, DAj~DDj, and BAj~BDj (j=0-3) are available]
Palette 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Gradation level 0 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 15/15
Remark Gradation palette 0
Gradation palette 1
Gradation palette 2
Gradation palette 3
Caution: Different gradation levels can't be set in the same palette.
* This specification is subject to be changed without notice.
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8.2.17 Display Start Common Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
SC2
SC1
SC0
0
1
1
0
0
1
0
(At the time of reset:{ SC2,SC1,SC0}=0H, read address: 6H)
Mark shows "Don't care"
The SC register set up the scanning start output of the common driver.
SC2 SC1 SC0 Display starting common when SHIFT=0 COM0~ COM8~ COM16~ COM24~ COM32~ COM40~ COM48~ COM56~ Display starting common when SHIFT=1 COM66~ COM58~ COM50~ COM42~ COM34~ COM26~ COM18~ COM10~
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SHIFT="0": COM0 SHIFT="1": COM66
COM66 shift-scan COM0 shift-scan
8.2.18 Static Pictograph Control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
1
SPC1 SPC0
0
1
1
0
0
1
0
(At the time of reset:{ SPC1,SPC0}=0H, read address: 7H) Mark shows "Don't care" This command is used to select a signal to drive static pictograph.
SPC1 SPC0 Signal for static pictograph 0 0 VSS level is always output at SCOM and SSEG 0 1 Phase deviates by 45 degrees at SCOM and SSEG 1 0 Phase deviates by 90 degrees at SCOM and SSEG 1 1 Phase deviates by 135 degrees at SCOM and SSEG
Drive waveform when (SPC1, SPC0) =(0, 1)
VDD level SCOM VDD level SSEG VSS level VSS level
1 frame
1 frame
* This specification is subject to be changed without notice.
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Drive waveform when (SPC1, SPC0) =(1, 0)
VDD level SCOM VDD level SSEG VSS level VSS level
1 frame
1 frame
Drive waveform when (SPC1, SPC0) =(1, 1)
VDD level SCOM VSS level VDD level SSEG VSS level
1 frame
1 frame
8.2.19 Display Select Control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
0
PWM
0
1
1
0
0
1
0
(At the time of reset: {PWM } = 0H, read address: 8H)
PWM
The PWM register selection the gradation display mode. PWM = "0": Variable display mode using 4 gradations selected from 16 gradations PWM = "1": 4-gradation fixed display mode
* This specification is subject to be changed without notice.
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8.2.20 Electronic Volume Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
0
DV3 DV2
DV1
DV0
0
1
1
0
0
1
0
(Read address: AH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
1
DV6
DV5
DV4
0
1
1
0
0
1
0
(Read address: BH) (At the time of reset: {DV6~DV0} = 00H)
Mark shows "Don't care"
The DV register can control V0 voltage. The DV register has 7-bits, so can select 128 level voltage.
DV6 0 0 DV5 0 0 DV4 0 0 DV3 0 0 DV2 0 0 DV1 0 0 DV0 0 1 Output voltage Smaller
1 1
1 1
1 1
1 1
1 1
1 1
0 1
Larger
The LCD driver voltage V0 is determined by VREF level, N times charge pump and electronic volume code equation. When 4 times charge pump, the V0 voltage is equation (1) V0 = 0.9 * VREF * [2 + ( 2 DV/127)] --------------------------(1) When 3 times charge pump, the V0 voltage is equation (2) V0 = 0.9 * VREF * [1 + ( 85 + 2 DV/169)] --------------------(2) When 2 times charge pump, the V0 voltage is equation (3) V0 = 0.9 * VREF * [1 + ( DV/127)] ----------------------------(3) (DV: DV6 to DV0 register values) In order to prevent transient voltage from generating when an electronic volume code is set, the circuit design is such that the set value is not reflected as a level immediately after only the upper bits (DV6-DV4) of the electronic code have been set. The set value becomes valid when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
8.2.21 Internal Register Read Address
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
0
RA3
RA2
RA1
RA0
0
1
1
0
0
1
0
(At the time of reset: {RA3, RA2, RA1, RA0} = 0H, Read address: CH)
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
The RA register set to specify the address for register read operation. The EM65100 has many registers and has register bank. Therefore, it is need 4-steps to read to read the specific register in maximum case. (1) (2) (3) (4) Write 02H to RE register for access to RA register. Writes specific register address to RA register. Write specific register bank to RE register. Read specific contents.
8.2.22 Resistance Ratio of CR Oscillator
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
1
RF2
RF1
RF0
0
1
1
0
0
1
0
(At the time of reset: {RF2, RF1, RF0} = 0H, read address: DH)
Mark shows "Don't care"
The RF registers can control resistance ratio of CR oscillator. Therefore frame frequency can change RF registers setting. When change RF registers value, should be need to check LCD display quality.
RF2 RF1 RF0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation Initial Resistance Ratio 0.8 times of initial Resistance Ratio 0.9 times of initial Resistance Ratio 1.1 times of initial Resistance Ratio 1.2 times of initial Resistance Ratio Prohibit Code Prohibit Code Prohibit Code
8.2.23 Extended power control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
0
BF1
BF0
HPM
DIS
0
1
1
0
0
1
0
At the time of reset: {HPM, DIS} = 0H, {BF1,BF0}=0H;read address: EH)
mark shows "Don't care"
The DIS register can control capacitors discharged that connected between the power supply V1-V4 for LCD drive voltage and VSS. V0 is discharged to VDD. DIS = "0": Discharge OFF DIS = "1": Discharge start
* This specification is subject to be changed without notice.
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The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM = "H": High power mode HPM = "L": Normal mode BF1~BF0: The operating frequency in the booster is selected. When the boosting frequency is high, the driving ability of booster become high, but the current consumption is increased. Adjust the boosting frequency considering the external capacitors and the current consumption.
BF1 0 0 1 1 BF0 0 1 0 1 Operating clock frequency in the booster 1.5K Hz * 8 1.5K Hz * 4 1.5K Hz * 2 1.5 K Hz
* This specification is subject to be changed without notice.
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9. Relationship between Setting and Common/Display RAM
The relationship between the COM pin numbers and the addresses in the Y-direction on the display RAM changes according to the SHIFT command. LCD Duty Set command. Display Starting Common Position Set command, and Display Starting Line Set command. When "0" is selected for the display starting line: The relationship between the COM pin and the addresses in the vertical direction of the display RAM (hereafter called MY) changes on an 15 dots basis according to the LCD Duty Set command and the Display Starting Common Position Set command. When the SHIFT bit is "0", the common position change in the forward direction. When "1" they change reverse direction. When "0" is selected as the values for LA6 to LA0 in the Display Starting Line Set command, the MY number corresponding to the display starting position is "0". The MY numbers are sequentially shifted backward when display occurs. In any case, the relations of COMA = MY67 and COMB = MY68 do not change. When non-zero is selected for the display starting line: The relationship between the COM pins and the addresses in the vertical direction on the display RAM, MY changes on an 15 dots basis according to the information in the LCD Duty Set command and Display Starting Common Position Set command. The common positions change in the forward when the SHIFT bit is "0", and change in the reverse direction when the SHIFT bit is "1". If non-zero is selected for the values for LA6 to LA0 by the Display Starting Line set command. the MY number corresponding to the display starting position shifts by the set value. The MY number shifts backward when display occurs. If it exceeds 66, it returns to 0, and the shifts sequentially. In any case, the relations of COMA = MY67 and COMB = MY68 do not change.
* This specification is subject to be changed without notice.
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10. Absolute maximum ratings
10.1 Absolute maximum ratings Item Symbol Condition Pin use Rating Supply voltage (1) VDD VDD -0.3 ~ + 4.0 Supply voltage (2) Vci Vci -0.3 ~ + 4.0 Supply voltage (3) Vcc Vcc -0.3 ~ + 13.0 Supply voltage (4) V0 V0 -0.3 ~ + 13.0 Ta=25 Supply voltage (5) V1,V2,V3,V4 V1,V2,V3,V4 -0.3 ~ V0+ 0.3 Input voltage VI *1 -0.3 ~ VDD+ 0.3 Storage Tstg -45 ~ +125 temperature 1: D0~D7, CSB, RS, M86, P/S, WRB, RDB, CK, CKS, RESB, TEST, VREF Pins Unit V V V V V V
10.2 Recommended operating conditions Item
Supply voltage Operating voltage Operating temperature
Symbol Application Pin VDD1 VDD Vci Vci V0 V0 Vcc Vcc VREF VREF Topr
Min. 1.8 2.4 5
2.4 -30
Max. 3.3 3.3 12 12 3.3 85
Unit V V V V V
Note *1 *2 *3
*4
1 shows applying voltage to VSS pin. 2 shows applying voltage to VSS pin. Usually, if applying voltage is same as VDD. Connect to VDD pin. 3 shows the voltage relationship of V0>V1>V2>V3>V4>VSS is required. 4 shows applying voltage to VSS pin.. In the case of using the voltage regulator. The voltage relationship of VREFVci
is required.
* This specification is subject to be changed without notice.
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11. DC characteristics
VSS=0V , VDD = 1.8~3.3V , Ta = -30 ~85
Item High level input voltage Low level input voltage High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance Symbol Condition Min. Typ. Max. Unit Pin used
VIH VIL IOH1 IOL1 ILI ILO RON RON ISTB fosc fosc fosc Vcc1 Vcc2 Vcc3 IDD1 IDD2 VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VDD |Von| = 0.5V V0=10V V0=6V
0.8VDD 0 -2.4 2.4 -2 -2 1.0 1.2 0.3
0.9VDD 0.1VDD -3.2 3.2 0 0 1.3 1.7 0.5 5
VDD 0.2VDD -4.5 4.5 2 2 1.6 2.2 0.7 15 248 42 16
V V mA mA A A K K A KHz KHz KHz V V V
1 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
LCD driver output resistance Standby current through VDD pin Oscillator frequency (variable gradation mode) Oscillator frequency (4 gradation mode) Oscillator frequency (monochrome mode) Booster output voltage on Vcc pin
|Von| = 0.5V, VDD=3V CK=0, CSB=VDD, Ta=25 , VDD=3V VDD=3V , Ta=25, Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V, Ta=25 , Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V , Ta=25, Rf setting = (Rf2,Rf1,Rf0)=(000) Four times boosting RL = 500K (Vcc-VSS) Three times boosting RL = 500K (Vcc-VSS) Two times boosting RL = 500K(Vcc-VSS) VDD = 3V, 4 times booster All ON pattern(gray), Display ON VDD = 3V, 4 times booster Checker pattern(gray), Display ON VDD = 3V, 3 times booster All ON pattern(gray), Display ON VDD = 3V, 3 times booster Checker pattern(gray), Display ON VDD = 3V, 4 times booster All ON pattern(mono), Display OFF
124 22 8 4*Vci *0.95 3*Vci *0.95 2*Vci *0.95
186 32 12
100 110 75 80 60 85
130 135 100 105 110
A A A A A
Current consumption
IDD3 IDD4 IDD5
* This specification is subject to be changed without notice.
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Relationship of oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each display mode Original oscillating clock When use built-in oscillating circuit (fosc) When use external clock from CK pin. (fCK) Display mode Variable gradation Simple gradation Monochrome Variable gradation Simple gradation Monochrome Ratio of display duty cycle (1/D) 1/69, 1/58, 1/50 1/42, 1/34, 1/26 1/18 fosc/(2*15*D) fosc/(2*3*D) fosc/(2*1*D) fCK/(2*15*D) fCK /(2*3*D) fCK /(2*1*D) fosc/(4*15*D) fosc/(4*3*D) fosc/(4*1*D) fCK /(4*15*D) fCK /(4*3*D) fCK /(4*1*D) fosc/(8*15*D) fosc/(8*3*D) fosc/(8*1*D) fCK /(8*15*D) fCK /(8*3*D) fCK /(8*1*D) 1/10 fosc/(16*15*D) fosc/(16*3*D) fosc/(16*1*D) fCK /(16*15*D) fCK /(16*3*D) fCK /(16*1*D) FLM(internal) Pin used
Pin used:

1 D0-D7, CSB, RS, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins. 2 D0~D7 pins 3 CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins 4 Applied when D0~D7 are in the state of high impedance. 5 SEG0~SEG100. COM0~COM66, COMA, COMB pins Resistance when being applied 0.5V between each
output pin and each power supply (V0, V1, V2, V3, V4) and when being applied 1/9 bias.

6 SSEG, SCOM pins 7 VDD pin, VDD pin current without load at the stoppage of original oscillating clock and at non-select
(CSB=VDD)

8 Oscillating frequency, when using the built-in oscillating circuit (variable gradation display mode) 9 Oscillating frequency, when using the built-in oscillating circuit (4 gradation fixed display mode)
10 Oscillating frequency, when using the built-in oscillating circuit (monochrome display mode) 11 Vcc pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 4 times is
used, this pin is applied. Vci=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/69 duty, without load. RL=500 K (between Vcc and VSS), C1=C2=1.0F, DCON=AMPON="1"
12 Vcc pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 3 times is
used, this pin is applied. Vci=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/69 duty, without load. RL=500 K (between Vcc and VSS), C1=C2=1.0F, DCON=AMPON="1"
13 Vcc pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 2 times is
used, this pin is applied. Vci=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/69 duty, without load. RL=500 K (between Vcc and VSS),
* This specification is subject to be changed without notice.
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C1=C2=1.0F, DCON=AMPON="1"
14 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access
from MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern (on gray mode display mode) and LCD driver pin with no load. Measuring conditions: VDD=Vci=VREF, C1=C2=1.0F, DCON=AMPON="1", (BF1,BF0)=1.5KHz.
15 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access
from MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern (on gray mode display mode) and LCD driver pin with no load. Measuring conditions: VDD=Vci=VREF, C1=C2=1.0F, DCON=AMPON="1" , (BF1,BF0)=1.5KHz.
16 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access
from MPU. This pin is applied. Boosting 3 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern (on gray mode display mode) and LCD driver pin with no load. Measuring conditions: VDD=Vci=VREF, C1=C2=1.0F, DCON=AMPON="1" , (BF1,BF0)=1.5KHz.
17 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access
from MPU. This pin is applied. Boosting 3 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern (on gray mode display mode) and LCD driver pin with no load. Measuring conditions: VDD=Vci=VREF, C1=C2=1.0F, DCON=AMPON="1" , (BF1,BF0)=1.5KHz.
18 VDD, Vci pin. When the built-in oscillating circuit and built-in power supply are used and there is no access
from MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display OFF (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=Vci=VREF, C1=C2=1.0F, DCON=AMPON="1" , (BF1,BF0)=1.5KHz.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
12. AC characteristic
(1) 80-family MCU write timing
tAS8
tAH8
CSB RS
tW RLW 8 W RB tDS8 tW RHW 8 tDH8
D0-D7
tCYCW R8
VSS=0V, VDD = 2.7~3.3V , Ta = -30~+85
Item Symbol Condition Address hold time tAH8 Address setup time tAS8 System cycle time in write tCYCWR8 Write pulse "L" width tWRLW8 Write pulse "H" width tWRHW8 Data setup time tDS8 Data hold time tDH8 VSS=0V, VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 250 60 185 60 5 Min. 0 0 330 80 240 80 10 Typ. Max. Unit ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns Pin used CSB RS
WRB (R/WB) D0~D7
Typ.
Max.
Pin used CSB RS
WRB (R/WB) D0~D7
VSS=0V, VDD = 2.4~3.3V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 660 140 500 100 20 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
WRB (R/WB) D0~D7
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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(2) 80-family MCU read timing
tAS8 CSB RS
tAH8
RDB
tRDLW8 tRDHW8 tRDH8
tRDD8 D0-D7
tCYCRD8
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 450 200 185 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL = 80 pF 10
250
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 600 220 240 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL = 80 pF 10
350
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 1000 450 500 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL = 80 pF 10
650
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(3) 68-family MCU write timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW6
tELW6
tDS6
tDH6
D0-D7
tCYCWR6
VSS=0V , VDD = 2.7 ~3.3V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 0 0 250 60 185 60 5 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
VSS=0V , VDD = 2.4 ~2.7V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 0 0 330 80 240 80 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
VSS=0V , VDD = 1.8 ~2.4V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 0 0 660 140 500 100 20 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(4) 68-family MCU read timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW6
tELW6
tRDD6
tRDH6
D0-D7
tCYCRD6
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 450 200 185 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL=80pF
250 10
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 600 220 240 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL=80pF
350 10
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 1000 450 500 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS
RDB(E) D0~D7
CL=80pF
650 10
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(5) Serial interface timing diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS
tAHS
tSHW
tDHS
D0-D7
tCYCS
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85
Item Symbol Condition Serial clock period tCYCS SCL pulse "H" width tSHW SCL pulse "L" width tSLW Address setup time tASS Address hold time tAHS Data setup time tDSS Data hold time tDHS CSB-SCL time tCSS CSB hold time tCSH VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Symbol Condition Serial clock period tCYCS SCL pulse "H" width tSHW SCL pulse "L" width tSLW Address setup time tASS Address hold time tAHS Data setup time tDSS Data hold time tDHS CSB-SCL time tCSS CSB hold time tCSH VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40 Min. 250 100 100 50 50 100 100 50 50 Min. 1000 400 400 80 80 400 400 80 80 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns Pin used
SCL RS SDA CSB
Typ.
Max.
Pin used
SCL RS SDA CSB
Typ.
Max.
Pin used
SCL RS SDA CSB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(6) Display control timing
tCLKH tCLKL CLK(internal) tDLP tDLP tLPLW LP(internal) tLPHW tDFLM
tDFLM FLM(internal) tDM
M(internal)
output timing VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85
Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Condition Min. 10 10 10 Typ. Max. 500 500 500 Unit ns ns ns Pin used LP(internal) FLM(internal) M(internal)
CL =15 pF
output timing VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85
Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Condition Min. 10 10 10 Typ. Max. 1000 1000 1000 Unit s s s Pin used LP(internal) FLM(internal) M(internal)
CL =15 pF
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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(7) Master clock input timing
tCKLW CK tCKHW
VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85
Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tTCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Min. 1.2 1.2 5.4 5.4 38 38 Typ. Max. 1.4 1.4 6.5 6.5 45 45 Unit s s s s s s Pin used CK 1 CK 2 CK 3
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85
Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Note1 Note1 Note2 Note2 Note3 Note3 Min. 1.2 1.2 5.4 5.4 3.8 3.8 Typ. Max. 1.4 1.4 6.5 6.5 4.5 4.5 Unit s s s s s s Pin used CK 1 CK 2 CK 3
1 Applied when the gradation display mode. 2 Applied when the simple gradation mode. 3 Applied when the monochrome mode.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(8) Reset timing
RESB
tRW tR
internal state
reset m ode
norm al dsiplay
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85
Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. Typ. Max. 1 Unit s s Pin used
500
RESB
VSS=0V, VDD = 1.8~2.4V, Ta = -30~+85
Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. Typ. Max. 1.5 Unit s s Pin used
500
RESB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
13. Application circuit
(1) Connection to 80-family MCU
VCC A0 A1 to A7 80 family MPU Decoder /IORQ D0 to D7 /RD /W R /RES G ND CSB RS
VDD
D0 to D7 RDB W RB RESB VSS
(2) Connection to 68-family MCU
VCC A0 A1 to A15 68 family MPU Decoder VMA D0 to D7 E R/W /RES G ND CSB RS
VDD
D0 to D7 RDB(E) W RB(R/W ) RESB VSS
* This specification is subject to be changed without notice.
EM65100
EM65100
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EM65100 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
(3) Connection to the MCU with serial interface
VCC A0 RS
VDD
A1 to A7 MPU
Decoder
CSB EM65100 VSS
PORT1 PORT2 /RES G ND
SDA SCL RESB
* This specification is subject to be changed without notice.
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