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EM65570
68COM / 98SEG 65K Color STN LCD Driver
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
September 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 4 General Description ........................................................................................1 Feature..............................................................................................................1 Applications .....................................................................................................2 Pin Configurations ..........................................................................................2
4.1 4.2 4.3 4.4 Alignment Key...................................................................................................... 3 Pin Dimensions .................................................................................................... 3 Recommended Cog Ito Traces Resistor ............................................................. 4 PAD Coordinates Table........................................................................................ 5
5 6
Functional Block Diagram ............................................................................12 Pin Descriptions ............................................................................................13
6.1 6.2 6.3 6.4 6.5 Power Supply Pins............................................................................................. 13 LCD Power Supply Circuit Pins ......................................................................... 13 System Bus Pins................................................................................................ 14 LCD Drive Circuit Signals .................................................................................. 15 Oscillating Circuit Pin......................................................................................... 16 MPU Interface .................................................................................................... 16
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Reset Pin Description (RESB).........................................................................16 Selection of Interface Type ..............................................................................16 Parallel Input ...................................................................................................17 Read/Write Functions of Register and Display RAM .......................................17 Serial Interface ................................................................................................17 7.1.5.1 4-Wire Type Serial Interface .............................................................17 7.1.5.2 3-Wire Type Serial Interface .............................................................18 Writing Data Operation ....................................................................................19 Read Display RAM Operation .........................................................................19 Register Read Operation.................................................................................20
7
Function Description ....................................................................................16
7.1
7.2 7.3
Writing Data to Display RAM and Control Register........................................... 19
7.2.1 7.3.1 7.3.2
Internal Display RAM and Register Read ......................................................... 19
7.4 7.5 7.6 7.7 7.8
16-Bit Data Access to Display RAM .................................................................. 20 Fast Burst RAM Write Function ......................................................................... 21 Display RAM Access Using the Windows Function .......................................... 22 Display RAM Data and LCD .............................................................................. 22 Correlation between Display RAM and Address ............................................... 23
7.8.1 7.8.2 7.8.3 7.8.4 Gradation Mode (65K Colors), (C256=0, 65K=1) ............................................23 Gradation Mode (4096 Colors), (C256=0, 65K=0)...........................................24 Gradation Mode (256 Colors), (C256=1, 65K=0).............................................25 Data Read and Write Bit Assignment ..............................................................26
* iii
Product Specification (V1.0) 09.05.2005
Contents
7.9
Display Data Structure and Gradation Control .................................................. 26
7.9.1 Gradation Mode (65K Color) ...........................................................................27 7.9.1.1 8-Bit Mode ........................................................................................27 7.9.1.2 16-Bit Mode ......................................................................................28 Gradation Mode (4096 Color)..........................................................................29 7.9.2.1 8-Bit Mode ........................................................................................29 7.9.2.2 16-Bit Mode ......................................................................................30 Gradation Mode (256 Color)............................................................................31 7.9.3.1 8-Bit Mode ........................................................................................31 7.9.3.2 16-Bit Mode (WLS=1) .......................................................................32
7.9.2
7.9.3
7.10 Gradation LSB Control...................................................................................... 33 7.11 Display Timing Circuit ........................................................................................ 33
7.11.1 Signal Generation to Display Line Counter and Data Latching Circuit .......................................................................................34 7.11.2 Generation of the Alternated Signal (internal M) and the Synchronous Signal (internal FLM) ...........................................................34 7.11.3 Display Data Latching Circuit ..........................................................................34
7.12 Output Timing of LCD Driver ............................................................................. 35 7.13 LCD Drive Circuit ............................................................................................... 36 7.14 Oscillator Circuit................................................................................................. 36 7.15 Power Supply Circuit ......................................................................................... 36 7.16 Booster Circuit ................................................................................................... 36 7.17 Electronic Volume .............................................................................................. 37 7.18 Voltage Regulator .............................................................................................. 37 7.19 Voltage Generation Circuit................................................................................. 38 7.20 EEPROM Function............................................................................................. 40
7.20.1 EEPROM Program, Read, and Erase Flow Charts..........................................41 7.20.2 Vop Calibration Offset Examples .....................................................................43
7.21 Partial Display Function ..................................................................................... 46 7.22 Discharge Circuit................................................................................................ 47 7.23 Scroll Function ................................................................................................... 47
7.23.1 Settings Scrolling Data Area in RAM ...............................................................50
7.24 Initialization ........................................................................................................ 51 7.25 Safety Measures when Switching Power ON and OFF .................................... 52
7.25.1 When Using the External Power Supply ..........................................................52 7.25.2 When Using the Built-in Power Supply ............................................................52 7.25.3 Power Supply Rising Time...............................................................................53
7.26 Example of Setting Registers ............................................................................ 53
7.26.1 Initialization......................................................................................................53 7.26.2 Display Data ....................................................................................................54 7.26.3 Power OFF ......................................................................................................54
iv *
Product Specification (V1.0) 09.05.2005
Contents
8
Control Registers ..........................................................................................55
8.1 Control Register ................................................................................................. 55
8.1.1 8.1.2 8.1.3 8.1.4 Control Register Table (Bank 0) ......................................................................55 Control Register Table (Bank 1) ......................................................................56 Control Register Table (Bank 4) ......................................................................57 Control Register Table (Bank 5) ......................................................................58 X Address Register (AX) .................................................................................59 Y Address Register (AY)..................................................................................59 n Line Alternate Register (N) ...........................................................................60 Display Control (1) Register ............................................................................61 Display Control (2) Register ............................................................................62 Increment Control Register Set .......................................................................62 Power Control Register ...................................................................................64 LCD Duty (DS) ................................................................................................65 Booster Setup (VU) .........................................................................................66 Bias Sett ing Register (B) ................................................................................66 Register Access Control...................................................................................67 Display Start Common .....................................................................................67 Temperature Compensation Set ......................................................................68 RAM Data Length Set......................................................................................69 RAM Data Writing Select Control.....................................................................69 Electronic Volume Register..............................................................................71 Internal Register Read Address .......................................................................72 Resistance Ratio of CR Oscillator....................................................................72 Extended Power Control..................................................................................73 Window End X Address ...................................................................................73 Window End Y Address ...................................................................................73 Regulator Multiple Ratio Control ......................................................................74 Line Reverse Start Address .............................................................................74 Line Reverse End Address ..............................................................................74 Line Reverse Control .......................................................................................75 EEPROM Mode Select Register ......................................................................76 Vop Calibration Offset Register........................................................................76 EEPROM Address Select Register..................................................................77 Scroll Top Address...........................................................................................78 Scroll Bottom Address .....................................................................................78 Scroll Specified Address ..................................................................................78 Scroll Start Address .........................................................................................79 Scroll Mode Select...........................................................................................79
8.2
Functions of Control Registers .......................................................................... 58
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 8.2.26 8.2.27 8.2.28 8.2.29 8.2.30 8.2.31 8.2.32 8.2.33
9
Absolute Maximum Rating ...........................................................................80
9.1 9.2 Absolute Maximum Ratings ............................................................................... 80 Recommended Operating Conditions ............................................................... 80
10 DC Electrical Characteristics .......................................................................81
Product Specification (V1.0) 09.05.2005 *v
Contents
11 AC Electrical Characteristics .......................................................................84
11.1 80-Family MCU Write Timing............................................................................. 84 11.2 80-Family MCU Read Timing ............................................................................ 85 11.3 68-Family MCU Write Timing............................................................................. 86 11.4 68-Family MCU Read Timing ............................................................................ 88 11.5 Serial Interface Timing Diagram ........................................................................ 89 11.6 Clock Input Timing ............................................................................................. 91 11.7 Reset Timing ...................................................................................................... 92
12 Application Circuit ........................................................................................92
12.1 Connected to 80-Family MCU ........................................................................... 92 12.2 Connected to 68-Family MCU ........................................................................... 93 12.3 Connected to Serial Interface MCU................................................................... 93
13
Packing Tray Dimensions............................................................................94
Specification Revision History
Doc. Version 0.1 0.2 Initial version 1. 2. 1. 2. 3. 4. 5. 6. 0.3 7. 8. 9. Modify Pad define: GND VSS Add VBA application circuit Remove all graphic function & graphic control registers descriptions. Modify system block diagram on page 11. Modify VBA and VREF pin descriptions on page 12. Modify power circuit diagram on page 37~38. Modify scroll function sample code on page 48~49. Modify description and diagram about `SWAP' on page 63~65. Add scrolling mode diagram on page 84. Modify VREF recommended value on page 85. Remove CSL pin, VPP pin, VPP_EXT control bit and its descriptions. 2005/04/21 Revision Description Date 2004/12/ 6 2005/02/21
10. Modify DV value table and add description of DV limitation on page 75. 11. Remove all external power mode descriptions, diagrams. 12. Modify Alignment Mark coordinate 1.0 Add tray information 2005/09/05
vi *
Product Specification (V1.0) 09.05.2005
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
1
General Description
EM65570 is one of the industry's most advanced wide-screen STN-LCD drivers for 65K-color display. It also has a built-in display RAM, a power supply circuit for LCD drive, an LCD controller circuit, and supports EEPROM function for programming information to tune the VLCD offset voltage to get the best contrast which helps in compacting system design. EM65570 contributes to compact system design and with its partial display function, low power consumption is achieved. Its "partial display"1 function realizes results in low power consumption.
2
Feature
65K-color display LCD output: Segment 98RGB (294 outputs); Common 68 outputs Display RAM capacity: 98x68x16=106624 bits Built-in display RAM and power supply circuit Partial display functions Bus connection with 80-family/68-family MPU Logic power supply voltage range: 2.2 to 3.3 V Analog power supply voltage range: 2.4 to 3.3 V LCD driving voltage range: 4.5 to 16 V Booster: 2 to 6 times Fast burst-RAM write function Screen scroll function EEPROM function for setting the LCD operating voltage Vop Write system cycle: 200 ns Package: Part Number
EM65570AGH Gold bumped chip
Package
NOTE The EM65570 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad with no bump); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example: EM65570AGH EM65570: Elan product number A: Package Version GH: Gold bump chip
1
A function that utilizes only part of the screen, thus reducing power consumption. *1
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
3
Applications
Mobile phone Small PDA
4
Pin Configurations
1 51 Figure 4-1 Pin Configuration 88 138 636
EM65570
159 169 179 NOTE The Elan logo at the left end (as shown in the figure) and Pin 1 is at the bottom-left corner. 222 265 271
Formatted: Font: (Default) Arial, 9 pt, Italic
2*
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
4.1
Alignment Key
Mark U-Left D-Left Coordinates (X,Y) -8899,534 -8898.95,-534.05 Mark U-Right D-Right Coordinates (X,Y) 8899,534 8898.95,-534.05
Coordinates Origin: Chip center D-Left and D-Right: U-Left and U-Right:
40 100um
20
40
100um
100um
40 20 40
Figure. 4-2 Pin Alignment Key
4.2
Pin Dimensions
Item Chip size 1 ~ 265 Bump Size 266 ~ 270, 637 ~ 641 271 ~ 636 1 ~ 265 Pad Pitch 266 ~ 270, 637 ~ 641 271 ~ 636 Min pitch Die thickness (excluding bumps) Bump Height Minimum Bump Gap Coordinate Origin 20 1 mil (500 25 um) 17 3 m 15 Chip center Pad No. X 18100 35 22 31.5 50 55 46.5 46.5 m Size Y 1370 76 127 84 Unit
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
*3
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
4.3
Recommended Cog Ito Traces Resistor
Interface V0~V4 CAP1+,CAP1-,CAP2+,CAP2-,CAP3+, CAP4+,CAP5+,Vout VDD,VEE VSS WRB,RDB,CSB,...,D0~D7 RESB Max=3K Max=5~10K Max=50 ITO Traces Resistances
4*
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
4.4
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PAD Coordinates Table
Pad Name NC1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TEST TEST TEST PS PS PS M86 M86 M86 CSB CSB CSB VSS VSS VSS VSS VDD VDD VDD VDD RESB RESB RESB RS RS RS CK CK CK VSS VSS VSS VSS Coordinates (X, Y) -8807.65, -554.0 -8757.65, -554.0 -8707.65, -554.0 -8657.65, -554.0 -8607.65, -554.0 -8557.65, -554.0 -8507.65, -554.0 -8457.65, -554.0 -8407.65, -554.0 -8357.65, -554.0 -8307.65, -554.0 -8257.65, -554.0 -8207.65, -554.0 -8157.65, -554.0 -8107.65, -554.0 -8057.65, -554.0 -8007.65, -554.0 -7957.65, -554.0 -7907.65, -554.0 -7857.65, -554.0 -7807.65, -554.0 -7757.65, -554.0 -7707.65, -554.0 -7657.65, -554.0 -7607.65, -554.0 -7557.65, -554.0 -7507.65, -554.0 -7457.65, -554.0 -7407.65, -554.0 -7357.65, -554.0 -7307.65, -554.0 -7257.65, -554.0 -7207.65, -554.0 -7157.65, -554.0 -7107.65, -554.0 -7057.65, -554.0 -7007.65, -554.0 -6957.65, -554.0 -6907.65, -554.0 -6857.65, -554.0 -6807.65, -554.0 -6757.65, -554.0 -6707.65, -554.0 -6657.65, -554.0 -6607.65, -554.0 -6557.65, -554.0 -6507.65, -554.0 -6457.65, -554.0 -6407.65, -554.0 -6357.65, -554.0 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name WRB WRB WRB RDB RDB RDB VDD VDD VDD VDD D0 D0 D0 D1 D1 D1 D2 D2 D2 D3 D3 D3 D4 D4 D4 D5 D5 D5 D6 D6 D6 D7 D7 D7 D8 D8 D8 D9 D9 D9 D10 D10 D10 D11 D11 D11 D12 D12 D12 D13 Coordinates (X, Y) -6079.75, -554.0 -6029.75, -554.0 -5979.75, -554.0 -5929.75, -554.0 -5879.75, -554.0 -5829.75, -554.0 -5779.75, -554.0 -5729.75, -554.0 -5679.75, -554.0 -5629.75, -554.0 -5577.25, -554.0 -5522.25, -554.0 -5467.25, -554.0 -5412.25, -554.0 -5357.25, -554.0 -5302.25, -554.0 -5247.25, -554.0 -5192.25, -554.0 -5137.25, -554.0 -5082.25, -554.0 -5027.25, -554.0 -4972.25, -554.0 -4917.25, -554.0 -4862.25, -554.0 -4807.25, -554.0 -4752.25, -554.0 -4697.25, -554.0 -4642.25, -554.0 -4587.25, -554.0 -4532.25, -554.0 -4477.25, -554.0 -4422.25, -554.0 -4367.25, -554.0 -4312.25, -554.0 -4257.25, -554.0 -4202.25, -554.0 -4147.25, -554.0 -3864.35, -554.0 -3809.35, -554.0 -3754.35, -554.0 -3699.35, -554.0 -3644.35, -554.0 -3589.35, -554.0 -3534.35, -554.0 -3479.35, -554.0 -3424.35, -554.0 -3369.35, -554.0 -3314.35, -554.0 -3259.35, -554.0 -3204.35, -554.0
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
*5
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name D13 D13 D14 D14 D14 D15 D15 D15 VSS VSS VSS VSS TEST1 TEST1 TEST1 CKS CKS CKS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC2 NC3 NC4 VBA VREF VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT
Coordinates (X, Y) -3149.35, -554.0 -3094.35, -554.0 -3039.35, -554.0 -2984.35, -554.0 -2929.35, -554.0 -2874.35, -554.0 -2819.35, -554.0 -2764.35, -554.0 -2711.85, -554.0 -2661.85, -554.0 -2611.85, -554.0 -2561.85, -554.0 -2511.85, -554.0 -2461.85, -554.0 -2411.85, -554.0 -2361.85, -554.0 -2311.85, -554.0 -2261.85, -554.0 -2211.85, -554.0 -2161.85, -554.0 -2111.85, -554.0 -2061.85, -554.0 -2011.85, -554.0 -1961.85, -554.0 -1911.85, -554.0 -1861.85, -554.0 -1811.85, -554.0 -1761.85, -554.0 -1711.85, -554.0 -1661.85, -554.0 -1611.85, -554.0 -1561.85, -554.0 -1511.85, -554.0 -1461.85, -554.0 -1137.05, -554.0 -1087.05, -554.0 -1037.05, -554.0 -281.0, -554.0 -231.0, -554.0 -181.0, -554.0 -131.0, -554.0 -81.0, -554.0 -31.0, -554.0 19.0, -554.0 69.0, -554.0 119.0, -554.0 169.0, -554.0 219.0, -554.0 269.0, -554.0 319.0, -554.0
Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name CAP5P CAP5P CAP5P CAP5P CAP3P CAP3P CAP1P CAP1P CAP1N CAP1N CAP1N CAP1N CAP1N CAP1N CAP1N CAP1N CAP1N CAP1N VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE CAP2N CAP2N CAP2N CAP2N CAP2N CAP2N CAP2N CAP2N CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP2P CAP4P CAP4P
Coordinates (X, Y) 377.7, -554.0 427.7, -554.0 477.7, -554.0 527.7, -554.0 1261.65, -554.0 1311.65, -554.0 2384.35, -554.0 2434.35, -554.0 2698.15, -554.0 2748.15, -554.0 2798.15, -554.0 2848.15, -554.0 2898.15, -554.0 2948.15, -554.0 2998.15, -554.0 3048.15, -554.0 3098.15, -554.0 3148.15, -554.0 3511.15, -554.0 3561.15, -554.0 3611.15, -554.0 3661.15, -554.0 3711.15, -554.0 3761.15, -554.0 3811.15, -554.0 3861.15, -554.0 3911.15, -554.0 3961.15, -554.0 4320.7, -554.0 4370.7, -554.0 4420.7, -554.0 4470.7, -554.0 4520.7, -554.0 4570.7, -554.0 4620.7, -554.0 4670.7, -554.0 4720.7, -554.0 4770.7, -554.0 4820.7, -554.0 4870.7, -554.0 4920.7, -554.0 4970.7, -554.0 5020.7, -554.0 5070.7, -554.0 5120.7, -554.0 5170.7, -554.0 5220.7, -554.0 5270.7, -554.0 5320.7, -554.0 5370.7, -554.0
6*
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name CAP4P CAP4P CAP4P CAP4P CAP4P CAP4P CAP4P CAP4P CAP4P CAP4P VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS V4 V4 V4 V4 V4 V4 V4 V4 V3 V3 V3 V3 V3 V3 V3 V2 V2 V2 V2 V2 V2 V2 V1 V1 V1
Coordinates (X, Y) 5420.7, -554.0 5470.7, -554.0 5520.7, -554.0 5570.7, -554.0 5620.7, -554.0 5670.7, -554.0 5720.7, -554.0 5770.7, -554.0 5820.7, -554.0 5870.7, -554.0 5920.7, -554.0 5970.7, -554.0 6020.7, -554.0 6070.7, -554.0 6120.7, -554.0 6170.7, -554.0 6220.7, -554.0 6270.7, -554.0 6320.7, -554.0 6370.7, -554.0 6607.6, -554.0 6657.6, -554.0 6707.6, -554.0 6757.6, -554.0 6807.6, -554.0 6857.6, -554.0 6907.6, -554.0 6957.6, -554.0 7007.6, -554.0 7057.6, -554.0 7107.6, -554.0 7157.6, -554.0 7207.6, -554.0 7257.6, -554.0 7307.6, -554.0 7357.6, -554.0 7407.6, -554.0 7457.6, -554.0 7507.6, -554.0 7557.6, -554.0 7607.6, -554.0 7657.6, -554.0 7707.6, -554.0 7757.6, -554.0 7807.6, -554.0 7857.6, -554.0 7907.6, -554.0 7957.6, -554.0 8007.6, -554.0 8057.6, -554.0
Pin No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name V1 V1 V1 V1 V1 V0 V0 V0 V0 V0 V0 V0 V0 V0 NC5 NC6 NC7 NC8 NC9 NC10 NC11 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10
Coordinates (X, Y) 8107.6, -554.0 8157.6, -554.0 8207.6, -554.0 8257.6, -554.0 8307.6, -554.0 8357.6, -554.0 8407.6, -554.0 8457.6, -554.0 8507.6, -554.0 8557.6, -554.0 8607.6, -554.0 8657.6, -554.0 8707.6, -554.0 8757.6, -554.0 8807.6, -554.0 8945.0, -400.5 8945.0, -200.25 8945.0, 0.0 8945.0, 200.25 8945.0, 400.5 8809.4, 550.0 8564.75, 550.0 8518.25, 550.0 8471.75, 550.0 8425.25, 550.0 8378.75, 550.0 8332.25, 550.0 8285.75, 550.0 8239.25, 550.0 8192.75, 550.0 8146.25, 550.0 8099.75, 550.0 8053.25, 550.0 8006.75, 550.0 7960.25, 550.0 7913.75, 550.0 7867.25, 550.0 7820.75, 550.0 7774.25, 550.0 7727.75, 550.0 7681.25, 550.0 7634.75, 550.0 7588.25, 550.0 7541.75, 550.0 7495.25, 550.0 7448.75, 550.0 7402.25, 550.0 7355.75, 550.0 7309.25, 550.0 7262.75, 550.0
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
*7
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Pad Name COM8 COM6 COM4 COM2 COM0 NC12 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14
Coordinates (X, Y) 7216.25, 550.0 7169.75, 550.0 7123.25, 550.0 7076.75, 550.0 7030.25, 550.0 6983.75, 550.0 6937.25, 550.0 6890.75, 550.0 6844.25, 550.0 6797.75, 550.0 6751.25, 550.0 6704.75, 550.0 6658.25, 550.0 6611.75, 550.0 6565.25, 550.0 6518.75, 550.0 6472.25, 550.0 6425.75, 550.0 6379.25, 550.0 6332.75, 550.0 6286.25, 550.0 6239.75, 550.0 6193.25, 550.0 6146.75, 550.0 6100.25, 550.0 6053.75, 550.0 6007.25, 550.0 5960.75, 550.0 5914.25, 550.0 5867.75, 550.0 5821.25, 550.0 5774.75, 550.0 5728.25, 550.0 5681.75, 550.0 5635.25, 550.0 5588.75, 550.0 5542.25, 550.0 5495.75, 550.0 5449.25, 550.0 5402.75, 550.0 5356.25, 550.0 5309.75, 550.0 5263.25, 550.0 5216.75, 550.0 5170.25, 550.0 5123.75, 550.0 5077.25, 550.0 5030.75, 550.0 4984.25, 550.0 4937.75, 550.0
Pin No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31
Coordinates (X, Y) 4891.25, 550.0 4844.75, 550.0 4798.25, 550.0 4751.75, 550.0 4705.25, 550.0 4658.75, 550.0 4612.25, 550.0 4565.75, 550.0 4519.25, 550.0 4472.75, 550.0 4426.25, 550.0 4379.75, 550.0 4333.25, 550.0 4286.75, 550.0 4240.25, 550.0 4193.75, 550.0 4147.25, 550.0 4100.75, 550.0 4054.25, 550.0 4007.75, 550.0 3961.25, 550.0 3914.75, 550.0 3868.25, 550.0 3821.75, 550.0 3775.25, 550.0 3728.75, 550.0 3682.25, 550.0 3635.75, 550.0 3589.25, 550.0 3542.75, 550.0 3496.25, 550.0 3449.75, 550.0 3403.25, 550.0 3356.75, 550.0 3310.25, 550.0 3263.75, 550.0 3217.25, 550.0 3170.75, 550.0 3124.25, 550.0 3077.75, 550.0 3031.25, 550.0 2984.75, 550.0 2938.25, 550.0 2891.75, 550.0 2845.25, 550.0 2798.75, 550.0 2752.25, 550.0 2705.75, 550.0 2659.25, 550.0 2612.75, 550.0
8*
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Pad Name SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47
Coordinates (X, Y) 2566.25, 550.0 2519.75, 550.0 2473.25, 550.0 2426.75, 550.0 2380.25, 550.0 2333.75, 550.0 2287.25, 550.0 2240.75, 550.0 2194.25, 550.0 2147.75, 550.0 2101.25, 550.0 2054.75, 550.0 2008.25, 550.0 1961.75, 550.0 1915.25, 550.0 1868.75, 550.0 1822.25, 550.0 1775.75, 550.0 1729.25, 550.0 1682.75, 550.0 1636.25, 550.0 1589.75, 550.0 1543.25, 550.0 1496.75, 550.0 1450.25, 550.0 1403.75, 550.0 1357.25, 550.0 1310.75, 550.0 1264.25, 550.0 1217.75, 550.0 1171.25, 550.0 1124.75, 550.0 1078.25, 550.0 1031.75, 550.0 985.25, 550.0 938.75, 550.0 892.25, 550.0 845.75, 550.0 799.25, 550.0 752.75, 550.0 706.25, 550.0 659.75, 550.0 613.25, 550.0 566.75, 550.0 520.25, 550.0 473.75, 550.0 427.25, 550.0 380.75, 550.0 334.25, 550.0 287.75, 550.0
Pin NO 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Pad Name SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64
Coordinates (X, Y) -8.75, 550.0 -55.25, 550.0 -101.75, 550.0 -148.25, 550.0 -194.75, 550.0 -241.25, 550.0 -287.75, 550.0 -334.25, 550.0 -380.75, 550.0 -427.25, 550.0 -473.75, 550.0 -520.25, 550.0 -566.75, 550.0 -613.25, 550.0 -659.75, 550.0 -706.25, 550.0 -752.75, 550.0 -799.25, 550.0 -845.75, 550.0 -892.25, 550.0 -938.75, 550.0 -985.25, 550.0 -1031.75, 550.0 -1078.25, 550.0 -1124.75, 550.0 -1171.25, 550.0 -1217.75, 550.0 -1264.25, 550.0 -1310.75, 550.0 -1357.25, 550.0 -1403.75, 550.0 -1450.25, 550.0 -1496.75, 550.0 -1543.25, 550.0 -1589.75, 550.0 -1636.25, 550.0 -1682.75, 550.0 -1729.25, 550.0 -1775.75, 550.0 -1822.25, 550.0 -1868.75, 550.0 -1915.25, 550.0 -1961.75, 550.0 -2008.25, 550.0 -2054.75, 550.0 -2101.25, 550.0 -2147.75, 550.0 -2194.25, 550.0 -2240.75, 550.0 -2287.25, 550.0
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
*9
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Pad Name SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81
Coordinates (X, Y) -2333.75, 550.0 -2380.25, 550.0 -2426.75, 550.0 -2473.25, 550.0 -2519.75, 550.0 -2566.25, 550.0 -2612.75, 550.0 -2659.25, 550.0 -2705.75, 550.0 -2752.25, 550.0 -2798.75, 550.0 -2845.25, 550.0 -2891.75, 550.0 -2938.25, 550.0 -2984.75, 550.0 -3031.25, 550.0 -3077.75, 550.0 -3124.25, 550.0 -3170.75, 550.0 -3217.25, 550.0 -3263.75, 550.0 -3310.25, 550.0 -3356.75, 550.0 -3403.25, 550.0 -3449.75, 550.0 -3496.25, 550.0 -3542.75, 550.0 -3589.25, 550.0 -3635.75, 550.0 -3682.25, 550.0 -3728.75, 550.0 -3775.25, 550.0 -3821.75, 550.0 -3868.25, 550.0 -3914.75, 550.0 -3961.25, 550.0 -4007.75, 550.0 -4054.25, 550.0 -4100.75, 550.0 -4147.25, 550.0 -4193.75, 550.0 -4240.25, 550.0 -4286.75, 550.0 -4333.25, 550.0 -4379.75, 550.0 -4426.25, 550.0 -4472.75, 550.0 -4519.25, 550.0 -4565.75, 550.0 -4612.25, 550.0
Pin No. 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
Pad Name SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97
Coordinates (X, Y) -4658.75, 550.0 -4705.25, 550.0 -4751.75, 550.0 -4798.25, 550.0 -4844.75, 550.0 -4891.25, 550.0 -4937.75, 550.0 -4984.25, 550.0 -5030.75, 550.0 -5077.25, 550.0 -5123.75, 550.0 -5170.25, 550.0 -5216.75, 550.0 -5263.25, 550.0 -5309.75, 550.0 -5356.25, 550.0 -5402.75, 550.0 -5449.25, 550.0 -5495.75, 550.0 -5542.25, 550.0 -5588.75, 550.0 -5635.25, 550.0 -5681.75, 550.0 -5728.25, 550.0 -5774.75, 550.0 -5821.25, 550.0 -5867.75, 550.0 -5914.25, 550.0 -5960.75, 550.0 -6007.25, 550.0 -6053.75, 550.0 -6100.25, 550.0 -6146.75, 550.0 -6193.25, 550.0 -6239.75, 550.0 -6286.25, 550.0 -6332.75, 550.0 -6379.25, 550.0 -6425.75, 550.0 -6472.25, 550.0 -6518.75, 550.0 -6565.25, 550.0 -6611.75, 550.0 -6658.25, 550.0 -6704.75, 550.0 -6751.25, 550.0 -6797.75, 550.0 -6844.25, 550.0 -6890.75, 550.0 -6937.25, 550.0
10 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Pin No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641
Pad Name NC13 COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 NC14 NC15 NC16 NC17 NC18 NC19
Coordinates (X, Y) -6983.75, 550.0 -7030.25, 550.0 -7076.75, 550.0 -7123.25, 550.0 -7169.75, 550.0 -7216.25, 550.0 -7262.75, 550.0 -7309.25, 550.0 -7355.75, 550.0 -7402.25, 550.0 -7448.75, 550.0 -7495.25, 550.0 -7541.75, 550.0 -7588.25, 550.0 -7634.75, 550.0 -7681.25, 550.0 -7727.75, 550.0 -7774.25, 550.0 -7820.75, 550.0 -7867.25, 550.0 -7913.75, 550.0 -7960.25, 550.0 -8006.75, 550.0 -8053.25, 550.0 -8099.75, 550.0 -8146.25, 550.0 -8192.75, 550.0 -8239.25, 550.0 -8285.75, 550.0 -8332.25, 550.0 -8378.75, 550.0 -8425.25, 550.0 -8471.75, 550.0 -8518.25, 550.0 -8564.75, 550.0 -8809.4, 550.0 -8945.0, 400.5 -8945.0, 200.25 -8945.0, 0.0 -8945.0, -200.25 -8945.0, -400.5
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 11
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
5
Functional Block Diagram
SEGC97 SEGB97 SEGA97 SEGC0 SEGB0 SEGA0 COM0 COM67
VDD V0 V1 V2 V3 V4 VSS
----
---------Segment Driver Gradation Selection Circuit Data Latch
Common Driver Shift Register
CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ CAP5+ VOUT VEE VREF VBA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL
Line Address Decoder
Display Line Register
Display Line Counter
Y Address Decoder
Y Address Register
Y Address Counter
Voltage Converter
Booster Circuit Input/Output Buffer
Display RAM (DDRAM) 98 X 68 X (5+6+5) bits
X Address Decoder RAM Interface X Address Counter
X Address Register
Alternation Circuit
Bus Holder
Instruction Decoder
Register Read
MPU Interface
OSC
Display Timing Gen.
TEST1 CSB RS RDB WRB P/S M86 RESB TEST (E) (R/WB)
CK CKS
Figure 5-1 System Block Diagram
12 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
6
Pin Descriptions
6.1 Power Supply Pins
Symbol VDD VSS V0 V1 V2 V3 V4 Power Supply I/O Power Supply Power Supply Description Power supply pin for logic circuit to +2.2 to 3.3V Ground pin for internal circuit, connect to 0V Bias power supply pin for the LCD drive voltage These voltages should have the following correlation: VSS6.2 LCD Power Supply Circuit Pins
Symbol CAP1+ CAP1- CAP2+ CAP2- CAP3+ CAP4+ CAP5+ I/O O O O O O O O Power Supply O O O Description Connecting pin for the built-in booster capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built-in booster capacitor - side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built-in booster capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built-in booster capacitor - side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built-in booster capacitor + side. The capacitor is connected between CAP1- and CAP3+. Connecting pin for the built-in booster capacitor + side. The capacitor is connected between CAP2- and CAP4+. Connecting pin for the built-in booster capacitor + side. The capacitor is connected between CAP1- and CAP5+. Voltage supply pin for the booster circuit. Usually the same voltage level as VDD. Output pin of the boosted voltage in the built-in booster. The capacitor must be connected between this pin and VSS. Output pin for the regulator voltage of VBA AMP. This pin should not be layed out on LCM ITO circuit. Output pin for the temperature compensation output voltage. This pin should not be layed out on LCM ITO circuit.
VEE
VOUT VBA VREF
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 13
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
6.3 System Bus Pins
Symbol RESB I/O I Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When the parallel interface is selected (P/S = "H"), D7-D0 are 8-bit bi-directional data buses connecting to the MPU data bus. D0/SCL D1/SDA D2 D3/SMODE D4.SPOL D5-D7 I/O When the serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for the data transfer clock SDA: Serial data input pin SMODE: Serial transfer mode select pin SPOL: RS pole select pin when the 3-wire serial interface is selected. SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of the 8th clock of SCL after the data conversion is completed or when making no access, be sure to set SCL to "L". D8-D15 I/O 8-bit bi-directional bus. Connected to the MPU data bus. Used as a data bus for the upper 8 pins in 16-bit access mode. Chip Select input pin. CSB I CSB = "L": accepts access from MPU CSB = "H": denies access from MPU RAM/Register select input pin. RS I RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin Select 80-family MPU type (M86 = "L") RDB (E) I RDB is a data read signal. When RDB is "L", D7-D0 are in output state. Select 68-family MPU type (M86 = "H") R/WB = "H": when E is "H", D7-D0 are in output state. R/WB = "L": data on D7-D0 is latched at the falling edge of the E signal. Read/Write control pin Select 80-family MPU type (M86 = "L") WRB (R/WB) I WRB is a data write signal. Data on D7-D0 is latched at the rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 I M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" 14 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
Description
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Symbol P/S
I/O I Parallel/Serial interface select pin. P/S Chip Select H CSB L CSB
Description
Data Identification RS RS
Data D0-D7 SDA
Read/Write RDB, WRB Write only
Serial Clock SCL
P/S = "H": For parallel interface. P/S = "L": For serial interface. Fixed D15-D5 pins are Hi-Z, RDB and WRB pins at either "H" or "L". TEST TEST1 I I For testing. Fixed at "L". For testing. Fixed at "L".
6.4 LCD Drive Circuit Signals
Symbol I/O Description Segment output pins for LCD drives. According to the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode); non-lighted at "1", lighted at "0" (Reverse Mode). Furthermore, with a combination of the M signal and display data, one signal level (among V0, V2, V3, and VSS signal levels) is selected. SEGA0-A97 SEGB0-B97 SEGC0-C97 O
M Signal (internal) Display RAM Data Normal Mode Reverse Mode V2 V0 V0 V2 V3 VSS VSS V3
Common output pins for LCD drivers. With a combination of the scanning data and M signal, one signal level (among V0, V1, V4 and VSS signal levels) is selected. COM0COM67 Data O H L H L M H H L L Output Level VSS V1 V0 V4
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 15
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
6.5 Oscillating Circuit Pin
Symbol CKS I/O I Description Display timing clock source select input pin. CKS = "H": Use external clock from the CK pin CKS = "L": Use the internal oscillated clock CK I/O The external clock input pin for display timing (CKS=1) or the internal clock output pin for display timing (CKS=0). When using the internal oscillator clock, CK must be floating (CKS=0)
7
Function Description
7.1 MPU Interface
7.1.1 Reset Pin Description (RESB)
Hold the RESB at low for at least 80s, after which the EM65101 accepts this reset command.
RESB
T > 80uS
Figure.7-1 RESB Timing
7.1.2 Selection of Interface Type
The EM65570 transfers data through the 8-bit parallel I/O (D7-D0), 16-bit parallel I/O (D15-D0), or serial data input (SDA, SCL). You can use the P/S pin to select the parallel or serial interface. When the serial interface is selected, you are allowed to write only as data reading is prohibited.
P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 (D15~D0) -
16 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.1.3 Parallel Input
When the parallel interface is selected with the P/S pin, the EM65570 allows data to be transferred in parallel to an 8-bit/16-bit MPU through the data bus. For the 8-bit/16-bit MPU, you can use the M86 pin to select either the 80-family or the 68-family MPU interface.
M86 H L MPU Type 68-family MPU 80-family MPU CSB CSB CSB RS RS RS RDB E RDB WRB R/WB WRB Data D7~D0 (D15~D0) D0~D7 (D15~D0)
7.1.4 Read/Write Functions of Register and Display RAM
The EM65570 have four read/write functions in parallel interface mode. Each read/write function is selected with the combinations of RS, RDB, and WRB signals.
RS 1 1 0 0 68-Family R/WB 1 0 1 0 0 1 0 1 80-Family RDB RDB 1 0 1 0 Read internal Register Write internal Register Read display data Write display data Function
7.1.5 Serial Interface
The EM65570 has two types of serial interfaces, i.e, 3-wire and 4-wire serial interfaces. Use the SMODE pin to select the serial interface type. SMODE = "L": 4-wire serial interface SMODE = "H": 3-wire serial interface
7.1.5.1 4-Wire Type Serial Interface
When the chip select is active (CSB = "L"), the 4-wire type serial interface works through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset to the initial condition. Serial data SDA are input sequentially in the order of D7 to D0 at the rising edge of the serial clock (SCL). The RS pin determines whether serial data input (SDA) is used as display RAM data or as control register data. RS = "L": display RAM data RS = "H": control register data
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 17
EM65570
68COM/ 98SEG 65K Color STN LCD Driver After completing the 8-bit data transfer or when making no access, be sure to set the serial clock input (SCL) to "L". Care should be taken during board wiring to avoid external noise from contaminating the SDA and SCL signals. To prevent transfer error due to external noise, release chip select (CSB = "H") after every complete 8-bit data transfer.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7-2 4-Wire Type Serial Interface
7.1.5.2 3-Wire Type Serial Interface
When the chip select is active (CSB = "L"), the 3-wire serial interface works through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset to the initial condition. Serial data SDA are input sequentially in the order of RS, D7 to D0 at the rising edge of the serial clock (SCL). The first serial input data (RS) and the SPOL pin determine whether serial data input (SDA) is used as display RAM data or as control register data.
SPOL = "0" RS 0 1 Display RAM/Register Display RAM Data Control Register Data RS 0 1 SPOL = "1" Display RAM/Register Control Register Data Display RAM Data
After completing the 9-bit data transfer or when making no access, be sure to set the serial clock input (SCL) to "L". Care should be taken during board wiring to avoid external noise from contaminating the SDA and SCL signals To prevent transfer error due to external noise, release chip select (CSB = "H") after every complete 9-bit data transfer.
CSB SDA SCL
1 2 3 4 5 6 7 8 9
RS
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7-3 3-Wire Type Serial Interface
18 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.2 Writing Data to Display RAM and Control Register
The procedure of writing data to the display RAM and Control Register is similar except for the RS selection which selects the accessed object. RS = "L": Display RAM data RS = "H": Control register data In the case of the 80-family MPU, data is written at the rising edge of WRB. In the case of the 68-family MPU, data is written at the falling edge of signal E.
7.2.1 Writing Data Operation
D7~D0 (D15~D0) WRB RS Write to control register Write to display RAM
Data0 Data1 Data2 Data3 Data4 Data5
Figure 7-4 Writing Data to Display RAM & Control Register Operation
7.3 Internal Display RAM and Register Read
7.3.1 Read Display RAM Operation
A one-time dummy read operation is required to perform the display RAM read operation. The designated address data are not output to read operation immediately after the address is set to AX or AY register, but are output when the second data read is performed. Dummy read is always required once after the address is set and the write cycle begins.
WRB D7~D0 (D15~D0) RDB RS n
Address set (AX,AY) Address = n
***
Dummy Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
Figure 7-5 Read Display RAM Operation
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 19
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.3.2 Register Read Operation
The EM65570 can read the control registers. When issuing a control register read operation, the upper data bus nibble (D7-D4) is used for the register address (0 to FH). Up to 16 registers can be accessed directly. However, more than 16 registers are provided. To solve this over supply problem, the EM65570 uses the register bank control to access the RE register with a bank number. You can access the RE register through any bank. The following lists the steps to be taken when accessing the specific register using the bank access control. 1. Set 01H to RE register for access to the RA register. 2. Set the specific register address to the RA register. 3. Set the specific register bank to the RE register. 4. Read the contents at the specific register.
WRB D0~D7 RDB RS
Figure 7-6 Register Read Operation
01H
Bank number write to RE for RA
addr
Address write to RA
bank
Bank number write to RE
data
read specific register
7.4 16-Bit Data Access to Display RAM
The EM65570 has both 8-bit and 16-bit data bus sizes. The data bus size can be selected by the WLS register. WLS = "0": 8-bits bus size WLS = "1": 16-bits bus size In 16-bit access mode, the Control Register Access uses the low-byte data bus (D7~D0) in the internal circuit and does not use the high-byte data bus (D15~D8). When reading control register using 16-bit bus, data exist at D3~D0 while D15~D4 is always 1 or "H".
20 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.5 Fast Burst RAM Write Function
The EM65570 has a built-in fast burst RAM write function. This function allows data transfer of 32 bits thus requiring only half of the access time needed for common standard RAM write function (16-bit data bus). The burst RAM write function is suitable for frequent data rewriting such as color animation display.
Microcontroller databus[0:15]
EM65570
Internal Buffer1 Internal buffer2 databus[0:31] 0x00H 0x01H 2 bytes 0x02H 0x03H 2 bytes .......
Display RAM
Figure 7-7 Fast Burst RAM Write Operation
NOTE Fast Burst RAM Write Function works more efficiently in horizontal RAM data writing mode, that is, RDWS[2]=0
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 21
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.6 Display RAM Access Using the Windows Function
The EM65570 has a window area setting command for accessing a specified display RAM area. To use the window function, you need to set up the X & Y address positions. In addition, you also need to enable the auto-increment mode (AXI="1", AYI="1"). These two positions represent the window start position and window end position. Set the X address (AX) and Y address (AY) registers to specify the window start position of X and Y respectively. Set the Window X End address (EX) and Window Y End address (AY) to specify the window end positions of X and Y respectively. When accessing the window function, you can set AIM to "1" to modify write access. You should set the following registers before accessing RAM when you use the window function. WIN = "1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address Moreover, the following address condition must be met: Window end X address (EX) Window start X address (AX) Window end Y address (EY) Window start Y address (AY) X Direction
The Window accessed area X,Y Start Address
7.7 Display RAM Data and LCD
One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by the REV register are set up as follows: Normal display (REV=0): RAM data = "0," light OFF RAM data = "1," light ON Reverse display (REV=1): RAM data = "0," light ON RAM data = "1" light OFF
Y Di rect i on
X,Y End Address
The entire RAM display area (shaded + Window accessed areas)
Figure 7-8 Window XY Address Location within RAM Display
22 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.8 Correlation between Display RAM and Address
The EM65570 executes the address conversion depending on the control register setting. In auto increment mode, usually the AX register is increased by one. For example, when REF and AXI are both "1", AX register is incremented by one, but effective X address seems to decrement because of address conversion. The effective Y address uses AY register values as it is.
7.8.1 Gradation Mode (65K Colors), (C256=0, 65K=1)
8-Bit Mode (WLS=0)
ABS WBS SWAP * 0 0 X=00H SEG A0
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=01H SEG B0 SEG C0 X=C2H SEG A97 SEG B97 X=C3H SEG C97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
X Address / Data Bus / Segment Assignment X=01H SEG A0 SEG B0 X=00H SEG C0 X=C3H SEG A97 SEG B97 X=C2H SEG C97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
*
1
0
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H SEG C0 SEG B0 X=01H SEG A0 X=C2H SEG C97 SEG B97 X=C3H SEG A97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
*
0
1
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=01H SEG C0 SEG B0 X=00H SEG A0 X=C3H SEG C97 SEG B97 X=C2H SEG A97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
*
1
1
16-Bit Mode (WLS=1)
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 D12 D13 D14 D15 1
*
*
0 SEG A0
X=61H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 D12 D13 D14 D15 1
SEG B0
SEG C0
SEG A97
SEG B97
SEG C97
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 D12 D13 D14 D15 1
*
*
1 SEG C0
X=61H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D1 D12 D13 D14 D15 1
SEG B0
SEG A0
SEG C97
SEG B97
SEG A97
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 23
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.8.2 Gradation Mode (4096 Colors), (C256=0, 65K=0)
8-Bit Mode (WLS="0")
ABS * WBS SWAP 0 0 X=00H SEG A0 X Address / Data Bus / Segment Assignment X=01H SEG B0 SEG C0 X=C2H SEG A97 X=C3H SEG B97 SEG C97 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7
ABS *
WBS SWAP 0 1 X=00H
X Address / Data Bus / Segment Assignment X=01H X=C2H X=C3H
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG C0 SEG B0 SEG A0
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG C97 SEG B97 SEG A97
ABS *
WBS SWAP 1 0 X=01H
X Address / Data Bus / Segment Assignment X=00H X=C3H X=C2H
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG A0 SEG B0 SEG C0
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG A97 SEG B97 SEG C97
ABS *
WBS SWAP 1 1 X=01H
X Address / Data Bus/ Segment Assignment X=00H X=C3H X=C2H
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG C0 SEG B0 SEG A0
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 SEG C97 SEG B97 SEG A97
16-Bit Mode (WLS="1")
ABS 0 WBS SWAP * 0 X Address / Data Bus / Segment Assignment X=00H
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15
X=61H
D1 D2 D3 D4 D7 D8 D9 D10 D12D13D14 D15
SEG A0
SEG B0
SEG C0
SEG A97
SEG B97
SEG C97
ABS 0
WBS SWAP * 1 SEG C0
X Address / Data Bus / Segment Assignment X=00H
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15
X=61H
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15
SEG B0
SEG A0
SEG C97
SEG B97
SEG A97
ABS WBS SWAP 1 * 0 SEG A0 24 *
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
X=61H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
SEG B0
SEG C0
SEG A97
SEG B97
SEG C97
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
1
*
1 SEG C0
X=61H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
SEG B0
SEG A0
SEG C97
SEG B97
SEG A97
7.8.3 Gradation Mode (256 Colors), (C256=1, 65K=0)
8-Bit Mode (WLS=0)
ABS WBS SWAP
X Address/ Data Bus / Segment Assignment X=00H D0 D1 D2 D3 SEG B0 D4 D5 D6 SEG C0 D7 D0 D1 D2 X=61H D3 D4 D5 D6 D7
*
*
0
SEG A0
ABS WBS SWAP
SEG A97
SEG B97
SEG C97
X Address / Data Bus / Segment Assignment X=00H D0 D1 D2 D3 SEG B0 D4 D5 D6 SEG A0 D7 D0 D1 D2 X=61H D3 D4 D5 D6 D7
*
*
1
SEG C0
SEG C97
SEG B97
SEG A97
16-Bit Mode (WLS=1)
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
*
*
0
X=30H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEG SEG SEG B0 SEG C0 A1 A0
SEG A1
SEG C1
SEG A96
SEG B96
SEG C96
SEG SEG B97 SEG C97 A97
ABS WBS SWAP
X Address / Data Bus / Segment Assignment X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
*
*
1
X=30H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEG SEG SEG B1 SEG C1 A1 A0
SEG B0
SEGC0
SEG A97
SEG B97
SEG C97
SEG SEG B96 A96
SEG C96
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 25
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.8.4 Data Read and Write Bit Assignment
16-Bit Data Bus Mode
ABS=0 65K=1 C256=0 Write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ABS=0 65K=0 C256=0 Write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read D15 D14 D13 D12 1 D10 D9 D8 D7 1 1 D4 D3 D2 D1 1
ABS=1 65K=0 C256=0 Write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read 1 1 1 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ABS=* 65K=0 C256=1 Write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
8-Bit Data Bus Mode
ABS=* 65K=1 C256=0 Address Write Read ABS=* 65K=0 C256=0 Address Write Read ABS=* 65K=0 C256=0 Address Write Read ABS=* 65K=0 C256=1 Address Write Read 00,02,04.........C0,C2H 01,03,05.........C1,C3H D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 00,02,04.........C0,C2H 01,03,05.........C1,C3H
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 00,02,04.........C0,C2H 01,03,05.........C1,C3H
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 D3 D2 D1 D0 00,01,02.........C1,C2,C3H D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
7.9 Display Data Structure and Gradation Control
For the purpose of the gradation control, one pixel requires multiple bits of display RAM. The EM65570 has 5-bit data per output to achieve gradation display. The three outputs of the segment driver are used for one pixel of RGB, and the EM65570 is connected to a color STN LCD panel. It can display 98*68 pixels with 65K colors (5 bits * 6 bits * 5 bits). In this case, since the gradation display data is processed by a single access to the memory, data can be rewritten fast and efficiently. The weighting for each data bit is dependent on the status of the SWAP bit that is selected when data is written to the display RAM.
26 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.1 Gradation Mode (65K Color)
7.9.1.1 8-Bit Mode
SWAP=0
SEGAi SEGBi SEGCi i=0 to 97
Gradation control
1
LSB
0
1
010
MSB LSB
0
1
0
0
1
0
0
10
0
MSB
Display RAM data
MSB LSB
1
01
01
0
0
1
0
0
1
0
0
1
0
0
D7
D0 D1 D2 D3 D4
D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
MPU write data X address: 2nH,2n+1H
Figure 7-9a Writing Data to Display RAM with SWAP=0 Selected under 8-Bit (65K Color) Mode
SWAP=1
SEGAi SEGBi SEGCi i=0 to 97
Gradation control 1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0 D7
D0 D1 D2 D3 D4
D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
MPU write data X Address: 2nH,2n+1H
Figure 7-9b Writing Data to Display RAM with SWAP=1 Selected under 8-Bit (65K Color) Mode
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 27
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.1.2
16-Bit Mode
In 16-bit access mode, the weighting for each data bit is dependent on the status of the SWAP bit that is selected when data is written to the display RAM, as in the case with the 8-bit access mode.
SWAP=0
SEGAi SEGBi SEGCi i=0 to 97
Gradation control 1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
MPU write data X address: 2nH,2n+1H
Figure 7-10a Writing Data to Display RAM with SWAP=0 Selected under 16-Bit (65K Color) Mode
SWAP=1
SEGAi SEGBi SEGCi i=0 to 97
Gradation control 1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
MPU write data X address: 2nH,2n+1H
Figure 7-10b Writing Data to Display RAM with SWAP=1 Selected under 16-Bit (65K Color) Mode
28 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.2 Gradation Mode (4096 Color)
7.9.2.1 8-Bit Mode
SWAP=0
SEGAi SEGBi SEGCi i=0 to 97
Gradation control Display RAM data
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
MSB LSB
MSB LSB
0
0
0
0
1
0
0
0
1
1
1
1
D0 D1 D2 D3
D0 D1 D2 D3 D4
D5 D6 D7
MPU write data X address: 2nH,2n+1H
Figure 7-11a Writing Data to Display RAM with SWAP=0 Selected under 8-Bit (4096 Color) Mode
SWAP=1
SEGAi
SEGBi
SEGCi
i=0 to 97
Gradation control Display RAM data
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
MSB LSB
MSB LSB
0
0
0
0
1
0
0
0
1
1
1
1
D0 D1 D2 D3
D0 D1 D2 D3 D4
D5 D6 D7
MPU write data X address: 2nH,2n+1H
Figure 7-11b Writing Data to Display RAM with SWAP=1 Selected under 8-Bit (4096 Color) Mode
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 29
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.2.2
16-Bit Mode
In 16-bit access mode, the weighting for each data bit is dependent on the status of the SWAP bit that is selected when data is written to the display RAM, as in the case with the 8-bit access mode. SWAP=0
SEGAi SEGBi SEGCi i=0 to 97
Gradation control Display RAM data
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
MSB LSB
MSB LSB
0 ABS=1
0
0
0
1
0
0
0
1
1
1
1
MPU write data X address: nH
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Figure 7-12a Writing Data to Display RAM with SWAP=0 Selected under 16-Bit (4096 Color) Mode
SWAP=1
SEGAi SEGBi SEGCi i=0 to 97
Gradation control display RAM data
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
MSB LSB
MSB LSB
0
0
0
0
1
0
0
0
1
1
1
1
MPU write data X address: nH
D1 D2 D3 D4 D0 D1 D2 D3 ABS=1
D7 D8 D4 D5
D9 D10 D12 D13 D14 D15 D6 D7 D8 D9 D10 D11
Figure 7-12b Writing Data to Display RAM with SWAP=1 Selected under 16-Bit (4096 Color) Mode 30 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.3 Gradation Mode (256 Color)
7.9.3.1 8-Bit Mode
SEGAi SEGBi SEGCi i=0 to 97
SWAP=0
Gradation control display RAM data
0 Gradation LSB circuit
0
0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU write data X address: nH
Figure 7-13a Writing Data to Display RAM with SWAP=0 Selected under 8-Bit (256 Color) Mode
SWAP=1
SEGAi SEGBi SEGCi i=0 to 97
Gradation Control Display RAM data 0 Gradation LSB circuit
1
MSB
1
1
LSB
0
MSB
0
1
LSB
0
MSB
0
MPU write data X address: nH
1 D0
1 D1
1 D2
0 D3
0 D4
1 D5
0 D6
0 D7
Figure 7-13b Writing Data to Display RAM with SWAP=1 Selected under 8-Bit (256 Color) Mode
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 31
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.9.3.2
16-Bit Mode (WLS=1)
SWAP=0
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1 i=0, 2, 4 to 96
0 Gradation LSB circuit 0 0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
0
0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
MPU write data X address: nH
Figure 7-14a Writing Data to Display RAM with SWAP=0 Selected under 16-Bit (256 Color) Mode
SWAP=1
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1 i=0, 2, 4 to 96
Gradation control 0 display RAM data 0
MSB
0
1
LSB
0
MSB
0
1
LSB
1
MSB
1
0
MSB
0
1
LSB
0
MSB
0
1
LSB
1
MSB
1
Gradation LSB circuit
MPU write data X address: nH
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
Figure 7-14b Writing Data to Display RAM with SWAP=1 Selected under 16-Bit (256 Color) Mode
32 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.10 Gradation LSB Control
In 256-color mode (C256=1), the EM65570 provides segment driver output for 8gradation display using 3 bits. For 4-gradation display, 2 bits are used. The segment driver output for the 4-gradation display uses 2 bits to write to the corresponding RAM area and additional 1 bit supplemented by the gradation LSB circuit, and then it selects 4-gradation from the 8-gradation. In 256-color mode (C256=1), the segment driver output for the 4-gradation display will result in a gradation level of "0" regardless of the gradation LSB when 2 bits of data on the display RAM are "00". When 2 bits of data on the display RAM is "11," a gradation level of 7/7 is selected regardless of the bit information of the gradation LSB. The other gradation levels are selected depending on 2 bits of data on the display RAM and the gradation LSB bits. One bit of data is supplemented by setting the gradation LSB register (GLSB). The Gradation LSB control bit applies to all 4-gradation segment drivers. Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment drivers. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment drivers.
7.11
Display Timing Circuit
The display timing circuit generates internal signals and timing pulses (internal LP, FLM, M) by clock. Symbol
LP (internal)
Description
The LP is latch clock signal. At the raising edge, count the display line counter. At the falling edge output the LCD drive signal. The signal for the LCD display synchronous signals (first line maker). When FLM is set to "H," the display start-line address is present. The signal for alternated signals of LCD drive output.
FLM (internal) M (internal)
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.11.1
Signal Generation to Display Line Counter and Data Latching Circuit
Clocks to the line counter and display data latching circuit from the display clock (internal LP) are generated. Synchronized with the display clock (internal LP), the line addresses of Display RAM are generated and the 384-bit display data is latched to the display data latching circuit to output to the LCD drive circuit (Segment outputs). Read-out of the display data to the LCD drive circuit is completely independent of MPU. Therefore, MPU has no relationship with the read-out operation that accesses the display data.
7.11.2
Generation of the Alternated Signal (internal M) and the Synchronous Signal (internal FLM)
LCD alternated signal (internal M) and synchronous signal (internal FLM) are generated by the display clock (internal LP). The FLM generates alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame (M-signal level is reversed every one frame). However, when setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1," the n-line reverse waveform is generated.
7.11.3
Display Data Latching Circuit
Display data latching circuit temporally latches the display data that is output to the LCD driver circuit from display RAM every one common period. Normal display/reverse display, display ON/OFF, and display ALL-ON functions are operated by controlling data in display data latch. Therefore, there is no change of data within the display RAM.
34 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.12
Output Timing of LCD Driver
Display timing at Normal mode (not Reverse mode), 1/68 DUTY.
67 68 1 2 3 68 1 2 3 68 1
LP FLM M V0 V1 COM0 V4 VSS V0 V1 COM1 V4 VSS V0 V2 SEG0 V3 VSS V3 V0 V4 V1 V1 V4 VSS
V0 V2 SEG1 V3 V2 V3 VSS Figure 7-15 LCD Driver Normal Mode Output Timing Diagram V3 V2
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.13
LCD Drive Circuit
This drive circuit generates four levels of LCD drive voltage. The circuit has 294 segment outputs and 68 common outputs; and outputs combined display data and internal signal M. The common drive circuit shifts register and sequentially outputs common scan signals.
7.14
Oscillator Circuit
The EM65570 has a CR oscillator. The output from this oscillator is used as the signal timing source of the display and the boosting clock to the booster. When the external clock is used, feed the clock source to the CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of the CR oscillator is programmable. When you change this ratio, you must also change the display frame frequency.
7.15
Power Supply Circuit
This circuit supplies voltages necessary to drive a LCD. The circuit consists of booster and voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3, and V4 which are in turn used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels. Otherwise, display quality will degrade considerably.
DCON 1 1 0 AMPON 1 0 0 Booster Circuit ENABLE ENABLE DISABLE Voltage Conversion Circuit ENABLE DISABLE DISABLE
7.16
Booster Circuit
Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, across CAP5+ and CAP1-, and across VOUT and VSS will boost the voltage coming from VEE and VSS n times and outputs the boosted voltage to the VOUT pin. Voltages that are boosted twice, three, four and five times respectively are output to the VOUT pin by the boost step register set. (1) To use the voltage that is boosted two times, place C1 only across CAP1+ and CAP1-; and open CAP2+, CAP2-, CAP3+, CAP1-, CAP4+, CAP2-, CAP5+, & CAP1(2) To use the voltage that is boosted three times, place C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-; and open CAP3+, CAP1-, CAP4+, CAP2-, CAP5+, & CAP1-
36 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver (3) To use the voltage that is boosted four times, place C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-; and open CAP4+, CAP2-, CAP5+, & CAP1(4) To use the voltage that is boosted five times, place C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1- across CAP4+ and CAP2-; and open CAP5+ & CAP1(5) To use the voltage that is boosted six times, place C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, across CAP5+ and CAP1When using the built-in booster circuit, output voltage (VOUT) must be less than the recommended operating voltage (20.0 Volt). If the output voltage (VOUT) is greater than the recommended operating voltage, normal operation of the chip cannot be guaranteed.
VOUT=18V VOUT=9V VEE=3V VSS=0V Boosted 3 times VEE=3V VSS=0V Boosted 6 times
Figure 7-16 Correlation between VEE and VOUT Boost-up Voltages NOTE The maximum voltage VOUT of 20V is automatically limited by hardware to avoid damage to the IC.
7.17
Electronic Volume
The voltage conversion circuit has a built-in electronic volume, which allows VBA to be controlled with the DV register setting. The relationship between VBA and DV is given in the following equation: VBA = (1+ (M+offset)/381) * VREF
Where: M: DV register value offset: CV register value VREF: temperature compensation output voltage
The VBA range is from 1.5V to 2V at 25C.
7.18
Voltage Regulator
The EM65570 has a built-in reference voltage regulator, which generates the voltage amplified by the input voltage from the internal temperature compensation output voltage VREF pin. The generated voltage is output at the V0 pin. Even if the boosted voltage level fluctuates, V0 will remain stable as long as VOUT is higher than V0. A stable power supply can be obtained using this constant voltage, even if the load fluctuates. The EM65570 uses the generated V0 level as the reference level of the electronic volume to generate the LCD drive voltage.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.19
Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0 (that is, V1, V2, V3 and V4) are obtained by dividing V0 through a resistor network. The LCD drive voltage from the EM65570 is biased at 1/4, 1/5, 1/6, 1/7, 1/8 , 1/9. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while selecting the LCD panel to be used.
Boosted 2 times Boosted 3 times
VDD VDD VEE
Boosted 4 times
VDD VDD VEE
VDD
VDD VEE
CAP5+ CAP3+ C1 CAP1+ CAP1C1
CAP5+ CAP3+ CAP1+ CAP1-
CAP5+ C1 C1 CAP3+ CAP1+ CAP1-
CAP2CAP2+ CAP4+
C1
CAP2CAP2+ CAP4+
C1
CAP2CAP2+ CAP4+
C1 vss C1 C1 C1 C1 C1
VOUT vss V0 V1 V2 V3 V4 vss
C1
VOUT
C1 vss
VOUT V0 V1 V2 V3 V4
C1 C1 C1 C1 C1
V0 V1 V2 V3 V4
C1 C1 C1 C1 C1
vss
vss
Figure 7-17a Internal Power Capacitor Connections Application Circuits (Voltage Boosted 2, 3, and 4 Times)
Recommended value:
C1 1.0 to 1.5 uF
NOTE The X5R type external capacitor must be used.
38 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Boosted 5 times
VDD VDD VEE
VDD
Boosted 6 times
VDD VEE
CAP5+ C1 C1 CAP3+ CAP1+ CAP1C1 C1 C1
CAP5+ CAP3+ CAP1+ CAP1-
C1 C1
CAP2CAP2+ CAP4+
C1
C1
CAP2CAP2+ CAP4+
C1 vss C1 C1 C1 C1 C1
C1
VOUT V0 V1 V2 V3 V4
VOUT V0 V1 V2 V3 V4
vss C1 C1 C1 C1 C1
vss
vss
Figure 7-17b Internal Power Capacitor Connections Application Circuits (Voltage Boosted 5 and 6 Times)
Recommended value:
C1 1.0 to 1.5 uF
NOTE The X5R type external capacitor must be used.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 39
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.20
EEPROM Function
The EM65570 provides EEPROM function to set the LCD operating voltage Vop. It can also select the EEPROM operating mode. In EEPROM select register (Bank 5[AH]), use (M1, M0) to select the operating mode for EEPROM.
(M1, M0) 00 01 10 11 EEPROM operating mode Read Program Erase Reserve Delay time 10 uS 4 mS 4 mS Needing VDD voltage 2.4V 2.8V 2.8V -
NOTE When using EEPROM function, different operating modes need different VDD voltage levels.
You can get the Vop calibration offset voltage by setting Vop calibration offset register (Bank 5[BH &EH]).
CV5~CV0 011111 011110 ... 000001 000000 100000 100001 ... 111111 Calibration Offset +31 +30 ... +1 0 -32 -31 ... -1
40 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.20.1 EEPROM Program, Read, and Erase Flow Charts
The following are the EEPROM Program, Read and Erase flow charts for achieving correct Vop offset voltage.
set CV 5~CV 4( up nibble register)
W R start : (M 1,M 0) set 01
select EEPROM address to read (N I B 1,N I B 0) set 00
set CV 3~CV 0(l ow nibble register)
delay > 4 ms
RD start : (M 1,M 0) set 00
select EEPROM address to program (N I B 1,N I B 0) set 01
W R end: (M 1,M 0) set 11
delay > 10 us
Reset W R start : (M 1,M 0) set 01 select EEPROM address to read (N I B 1,N I B 0) set 01 delay > 4 ms RD start : (M 1,M 0) set 00 W R end: (M 1,M 0) set 11 delay > 10 us select EEPROM address to program (N I B 1,N I B 0) set 00 RD end: (M 1,M 0) set 11
RD end: (M 1,M 0) set 11
Get correct V op of f set voltage
Figure 7-18a EEPROM Program Flow Chart
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 41
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
sel ect EEPR O M address to read (N I B 1,N I B 0) set 11
select EEP M RO addressto erase (NIB1,NIB0) set 01
delay > 4 ms
R D start : (M 1,M 0) set 00
RD end: (M1,M0) set 11
Erasestart : (M1,M0) set 10
del ay > 10 us
Eraseend: (M1,M0) set 11
select EEP ROM addressto read (NIB1,NIB0) set 00
R D end: (M 1,M 0) set 11
delay > 4 ms
Reset
RD start : (M1,M0) set 00
D EC (N I B 1,N I B 0)
Eraseend: (M1,M0) set 11
select EEP ROM addressto read (NIB1,NIB0) set 01
delay > 10 us
N I B 1,N I B 0 < 11
y
select EEP M RO addressto erase (NIB1,NIB0) set 00 RD start : (M1,M0) set 00
n
R ead Process end
RD end: (M1,M0) set 11
Erasestart : (M1,M0) set 10
delay > 10 us
7-18b EEPROM Read Flow Chart
7-18c EEPROM Erase Flow Chart
42 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.20.2 Vop Calibration Offset Examples
Program If the desired Vop calibration offset is +30, CV5~CV0 is set to 011110. The example code is shown below: WRITE WRITE WRITE WRITE WRITE #F4H #71H #6EH #A1H #52H // set RE FLAG 100 // set CV5~CV4=01 // set CV3~CV0=1110 // set NIB1~NIB0=01 program CV5~CV4 INSTRUCTION Bank 4
// set EEPROM operating mode programming; ROM power is from internal V0 // wait > 4 ms to finish programming // set EEPROM mode // set NIB1~NIB0=00 reserve (finish programming) program CV3~CV0
DELAY > 4 MS WRITE WRITE WRITE #56H #A0H #52H
// set EEPROM operating mode programming; EEPROM power is from internal V0 // wait > 4 ms to finish programming // set EEPROM mode // set RE FLAG 000 // EM65570 reset // set RE FLAG 100 // set NIB1~NIB0=01 INSTRUCTION Bank 4 read CV5~CV4 reading; read data reserve (finish programming) INSTRUCTION Bank 0
DELAY > 4 MS WRITE WRITE WRITE WRITE WRITE WRITE #56H #F0H #91H #F4H #A1H #50H
// set EEPROM operating mode
from EEPROM to the CV5~CV4 registers DELAY WRITE >10 uS #56H // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data from EEPROM to the CV5~CV4 registers) // set NIB1~NIB0=00 read CV3~CV0
WRITE WRITE
#A0H #50H
// set EEPROM operating mode reading; read data from EEPROM to the CV3~CV0 registers // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data
DELAY WRITE
>10 uS #56H
from EEPROM to the CV3~CV0 registers)
NOTE When setting CV5~CV0, you must set CV5~CV4 (upper nibble registers) first, then set CV3~CV0 (lower nibble registers), and then start to program. The programming sequence of CV5~CV4 and CV3~CV0 is not restricted.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Read WRITE WRITE WRITE #F4H #A3H #50H // set RE FLAG 100 // set NIB1~NIB0=11 INSTRUCTION Bank 4 read Extension Command reading; read data
// set EEPROM operating mode from EEPROM
DELAY WRITE
>10 uS #56H
// wait >10 uS to finish reading // set EEPROM mode from EEPROM reserve (finish reading data
WRITE WRITE
#A2H #50H
// set NIB1~NIB0=10
read Extension Command reading; read data
// set EEPROM operating mode from EEPROM
DELAY WRITE
>10 uS #56H
// wait >10 uS to finish reading // set EEPROM mode from EEPROM // set NIB1~NIB0=01 reserve (finish reading data
WRITE WRITE
#A1H #50H
read CV5~CV4 reading; read data
// set EEPROM operating mode
from EEPROM to the CV5~CV4 registers DELAY WRITE >10 uS #56H // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data from EEPROM to the CV5~CV4 registers) // set NIB1~NIB0=00 read CV3~CV0
WRITE WRITE
#A0H #50H
// set EEPROM operating mode reading; read data from EEPROM to the CV3~CV0 registers // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data
DELAY WRITE
>10 uS #56H
from EEPROM to the CV3~CV0 registers)
NOTE When reading from CV5~CV0, you must read the EEPROM data to CV5~CV4 (upper nibble register) first, then read the EEPROM data to CV3~CV0 (lower nibble registers).
44 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Erase WRITE WRITE WRITE #F4H #A1H #54H // set RE FLAG 100 // set NIB1~NIB0=01 INSTRUCTION Bank 4 erase CV5~CV4 erasing; EEPROM
// set EEPROM operating mode power is from internal V0
DELAY > 4 MS WRITE WRITE WRITE #56H #A0H #54H
// wait > 4 ms to finish erasing // set EEPROM mode // set NIB1~NIB0=00 reserve (finish erasing) erase CV3~CV0 erasing; EEPROM
// set EEPROM operating mode power is from internal V0
DELAY > 4 MS WRITE WRITE WRITE WRITE WRITE WRITE #56H #F0H #91H #F4H #A1H #50H
// wait > 4 ms to finish erasing // set EEPROM mode // set RE FLAG 000 // EM65570 reset // set RE FLAG 100 // set NIB1~NIB0=01 INSTRUCTION Bank 4 read CV5~CV4 reserve (finish erasing) INSTRUCTION Bank 0
// set EEPROM operating mode reading; read data from EEPROM to the CV5~CV4 registers // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data from EEPROM to the CV5~CV4 registers) // set NIB1~NIB0=00 read CV3~CV0 reading; read data
DELAY WRITE
>10 uS #56H
WRITE WRITE
#A0H #50H
// set EEPROM operating mode
from EEPROM to the CV3~CV0 registers DELAY WRITE >10 uS #56H // wait >10 uS to finish reading // set EEPROM mode reserve (finish reading data from EEPROM to the CV3~CV0 registers)
NOTE CV5~CV0 should be equal to 1111 after erasing
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 45
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.21
Partial Display Function
The EM65570 has the partial display function, which can display a part of the graphic display area. This function is used to set lower bias ratio, lower boost step, and lower LCD drive voltage. When setting the partial display function, the EM65570 consumes less power. Partial display function is most suitable for clock indication or calendar indication when portable equipment is on stand-by. ELAN LCD DRIVER Low Power and Low Voltage Normal Display
LCD DRIVER
Partial Display
Figure 7-19 Partial Display Block Diagram
When using the partial display function, it is necessary to keep the following sequence.
Any display condition Display off (ON/OFF= "0") Power circuit off (DCON= "0", AMPON= "0") WAIT
Setting Power Function * Boost step set * Electronic volume set * Bias Ratio set
Power circuit on (DCON= "1", AMPON= "1") WAIT
Setting Display Function * Duty Ratio set * Display start common
Display on (ON/OFF= "1") Partial Display
Figure 7-20 Partial Display Function Sequential Flow Diagram
46 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver Select a display duty ratio for the partial display from 1/10 to 1/68 using the DS (LCD duty ratio) register. Set the most suitable values for the LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and others according to the actual LCD panel and the selected duty ratio in use.
7.22
Discharge Circuit
The EM65570 has a built-in the discharge circuit, which discharges electricity from capacitors to obtain stable power sources (V0~V4). The discharge circuit is valid when the DIS register is set to "1." When the built-in power supply is used, be sure to set DIS="1" after the power source is turned off (DCON, AMPON)=(0, 0).
CAUTION!!! Do NOT turn on both the built-in power source and the external power source (V0~V4, VOUT) while DIS ="1."
7.23
Scroll Function
This function specifies the section of screen for scrolling. It sets the scroll top address, scroll bottom address, scroll specified address, scroll mode of the area scrolling, and scroll start address. Note that the scroll top address should be smaller than the scroll bottom address, i.e.; 0 <= scroll top address, scroll bottom address, scroll specified address <= 67; scroll top address <= scroll start address <= scroll bottom address.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 47
EM65570
68COM/ 98SEG 65K Color STN LCD Driver Example:
98RGB X 68 Line display RAM Top fixed area 2004/11/18 Scroll area Bottom fixed area Menu
Phone book 65
98RGB X 68 Line Panel Scroll address
0 1 2004/11/18 2 3 . . . 64 65 66 67 Menu 0 1 2004/11/18 2 3 . . . 64 65 66 67 Menu 0 1 2004/11/18 2 3 . . . 64 65 66 67 Menu 0 1 2004/11/18 2 3 . . . 64 65 66 67 Menu 0 1 2004/11/18 2 3 . . . 64 65 66 67 Menu AM 8:00 COM 0 COM 1
RAM address
AM 8:00 2
Scroll start address=2
Phone book AM 8:00
COM 66 COM 67 COM 0 COM 1
Scroll specified address=65 Scroll start address=3
Phone book AM 8:00
COM 66 COM 67 COM 0 COM 1
Scroll start address=4
Phone book AM 8:00
COM 66 COM 67 COM 0 COM 1
Scroll start address=33
Phone book AM 8:00
COM 66 COM 67 COM 0 COM 1
Scroll start address=64
Phone book
COM 66 COM 67
Figure 7-21 An Example of Scroll Function Display vs. Address Values
Sample Code: ------------set duty ratio=1/68-------------------------------------------WRITE 0xF0 //Bank 0 WRITE 0xAF //duty=1/68 ------------scroll function setting---------------------------------------WRITE 0xF5 //Bank 5 WRITE 0x10 //Scroll top address(up nibble) WRITE 0x02 //Scroll top address(low nibble) WRITE 0x34 //Scroll bottom address(up nibble)
48 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver WRITE 0x21 //Scroll bottom address(low nibble) WRITE 0x54 //Scroll specified address(up nibble) WRITE 0x41 //Scroll specified address(low nibble) WRITE 0x80 //Center scroll mode ------------scroll start------------------------------------------------MOV A, #2 MOV INDEX1, A LOOP1: WRITE 0x70 WRITE 0x60 + INDEX1 INC_INDEX_1: INC INDEX1 MOV A, INDEX1 JLE A, #15, LOOP1 MOV A, #1 MOV INDEX2, A LOOP2: MOV A, #0 MOV INDEX1, A LOOP3: WRITE 0x70 + INDEX2 WRITE 0x60 + INDEX1 INC_INDEX_2: INC INDEX1 MOV A, INDEX1 JLE A, #15, LOOP3 INC INDEX2 MOV A, INDEX2 JLE A, #3, LOOP2 MOV A, #0 MOV INDEX1, A LOOP4: WRITE 0x74 WRITE 0x60 + INDEX1 INC_INDEX_3: INC INDEX1 MOV A, INDEX1 JLE A, #1, LOOP4
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 49
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.23.1 Settings Scrolling Data Area in RAM
Set the scroll top address and scroll bottom address to define an area of scrolling data in RAM Example:
98RGB X 68 Line display RAM RAM address Scroll top address
2 2004/11/18 AM 8:00
Top fixed area Scroll data area
Scroll bottom address
65 Menu Phone book
Bottom fixed area
Figure 7-22a An Example of Setting Scrolling Data Area in RAM
Next, set the scroll specified address according to the panel size and duty selection to specify the address to which to jump relative to the scroll bottom address. Then display the fixed bottom data area. Note that the scroll specified address = scroll top address + panel scroll area - 1. Example (160 x 128 Line panel; 1/32 duty, partial display):
98RGB X 68 Line display RAM RAM address
COM 0
1/32 duty partial display
Scroll top address
Scroll specified address 29
2
COM 2 COM 29
Scroll bottom address
65
jump to bottom address
COM 31
(setting specified address=29)
COM 0
2
COM 2 COM 29
Scroll specified address
31 65
jump to bottom address
COM 31
(setting specified address=31)
Figure 7-22b An Example of Scroll Bottom Address Settings in an Scrolling Area
50 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
NOTE You must set the scroll top address, the scroll bottom address, the scroll specified address, and the scroll start address carefully when using the scroll function. If there is any error, the scrolling result will be inaccurate. Follow the guidelines shown below: Scroll top address <= Scroll bottom address Scroll specified address = Scroll top address + panel scroll area - 1 Scroll top address <= Scroll start address <= Scroll bottom address
7.24
Initialization
Set the RESB pin to "L" to initialize the EM65570. Normally, the RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power ON, set RESB="L". 65K color mode
ITEM Display RAM X Address Y Address Display starting common Display ON/OFF Display Normal/Reverse Display duty n-line alternated (BF1,BF0) Common shift direction Increment mode Data SWAP Mode Register in electronic volume Power Supply Display mode Bias ratio Booster Gradation LSB RAM access data length Discharge Register Not fixed 00H set 00H set Set at the first common (0H) Display OFF Normal 1/68 Every frame unit (0,0) COM0 COM67 Initial Value
Increment OFF OFF (0,0,0,0,0,0,0) OFF 65K color mode 1/9 bias 6 times 0 8-bits mode 0
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.25
Safety Measures when Switching Power ON and OFF
The high current that may occur when a voltage is supplied to the LCD driver power supply while the system power supply is floating, could permanently damage the LSI. Hence, the precautionary actions as detailed below should be taken into considerations seriously when switching power on and off.
7.25.1 When Using the External Power Supply
Power ON Proper Sequence: 1) Logic system (VDD) power ON, perform a reset operation 2) Supply the external LCD drive voltage to the corresponding pins (V0, V1, V2, V3 and V4) Power OFF Proper Sequence: 1) Set the HALT register to "1" or perform a reset operation 2) Cut off external LCD drive voltage 3) Logic system (VDD) power OFF
NOTE Connect the serial resistor (50 to 100) or fuse to the LCD drive power V0 or VOUT (when using the internal voltage conversion circuit) of the system as a current limiter. In addition, set a suitable resister value of the resistor depending on the quality of the LCD display.
7.25.2 When Using the Built-in Power Supply
Power ON Proper Sequence: 1) Logic system (VDD) power ON 2) Booster circuit system (VEE) power ON 3) Perform a reset operation and enable the booster and voltage conversion circuit.
NOTE If the VDD and VEE voltages do NOT have the same potential, the logic system (VDD) is automatically powered on first.
Power OFF Proper Sequence: 1) Set the HALT register to "1" or perform a reset operation 2) Booster circuit system (VEE) power OFF 3) Logic system (VDD) power OFF If VDD and VEE do NOT have the same potential, cut off VEE first. After the VEE, VOUT, V0, V1, V2, V3, and V4 voltages are below the LCD ON voltage (threshold voltage when the Liquid Crystal is turned on), power off the logic system (VDD).
52 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.25.3 Power Supply Rising Time
Although there is no constraint on the rising time of the power supply, the Tr (rising time) as illustrated below is recommended for practical applications.
90%
VDD,VEE
10%
Tr
Applicable Power
VDD, VEE
Item
Tr
Recommended Rising Time (Tr)
30S ~ 10ms*
* The rising time is the time between 10% adnd 90% of VDD, VEE
Figure 7-23 Recommended Rising Time (Tr) for Practical Application
7.26
Example of Setting Registers
7.26.1 Initialization
Power ON (VDD,VEE-VSS) Power will stable RESET WAIT
Setting Operational Functions * Electrical volume set * Bias Ratio set
Setting Operational Functions * Setting power control (DCON= "1", AMPON= "1")
End of initialization
Figure 7-24a Initialization Register Setting Sequential Flow
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.26.2 Display Data
End of initialization
Setting Operational Functions * Setting display start common * Setting address increment control * Setting X address * Setting Y address
Setting Operational Functions * Write dsiplay data
Setting Operational Functions * Setting display on/off control (ON/OFF= "1")
End of display data setting
Figure 7-24b Display Data Register Setting Sequential Flow
7.26.3 Power OFF
Any condition
Setting Operational Functions * Setting HALT=1 or make reset operation (LCD driver output VSS level) * Setting DIS= "1" (Discharge V0-V4 capacitor)
WAIT
Power OFF ( VEE,VDD)
Figure 7-24c Power Off Register Setting Sequential Flow 54 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8
Control Registers
8.1 Control Register
8.1.1 Control Register Table (Bank 0)
Control Register
X Address (Lower nibble) X Address (Upper Nibble) Y Address (Lower Nibble) Y Address (Upper Nibble) [0H] [1H] [2H] [3H] 0 0 0 0 0 0
Pins (for 80-Family) & Bank
CSB RS WRB RDB RE2 RE1 RE0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 D6 0 0 0 0 1 1
Address & Code
D5 0 0 1 1 0 0 D4 0 1 0 1 0 1 D3 D2 D1 D0
Function
AX3 AX2 AX1 AX0 AX7 AX6 AX5 AX4 AY3 AY2 AY1 AY0
Set of X direction Address in display RAM
*
N3
AY6 AY5 AY4 N2 N6 N1 N5 N0 N4
Set of Y direction Address in display RAM
n-line Alternation [4H] (Lower Nibble) n-line Alternation [5H] (Upper Nibble)
*
Set the number of alternated reverse line SHIFT: Select common shift direction
Display Control (1) [6H]
0
1
0
1
0
0
0
0
1
1
0
65K: Select 65K gradation SHI ALL ON/ 65K ON OFF ALLON: All display ON FT ON/OFF: Display ON/OFF control REV: Display normal/reverse NLIN: n line reverse control
Display Control (2) [7H]
0
1
0
1
0
0
0
0
1
1
1
*
REV NLIN
Increment Control [8H]
0
1
0
1
0
0
0
1
0
0
0
Power Control LCD Duty Ratio Booster
[9H] [AH] [BH]
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 1
0 1 1 0
1 0 1 0
SWAP: Display data swapping WIN: Select window. AIM: Select increment mode WIN AIM AYI AXI AYI: Y increment, AXI: X increment AMPON: Internal AMP. ON AMP HA DC HALT: Power saving ACL DCON: Boosting circuit ON ON LT ON ACL: Resetting DS3 DS2 DS1 DS0 Set LCD drive duty ratio 0 VU2 VU1 VU0 B2 B1 B0 Set number of boosting step for booster circuit
SW AP
Bias Ratio Control [CH] Register Access [FH] Control
0
1
0
1
0/1
0/1
0/1
1
1
1
1
Set bias ratio for LCD driving voltage TST0: for LS1 test, must be TS set to "0" RE2 RE1 RE0 RE: set register bank T0 number
*
NOTE: Address for the control register are enclosed in brackets [ ].
* Don't Care
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 55
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.1.2 Control Register Table (Bank 1)
Control Register
Display Start Common (Lower Nibble) Display Start Common (Upper Nibble) Temperature Compensation RAM Data Length Set
Pins (for 80-Family) & Bank
CSB RS WRB RDB RE2 RE1 RE0 D7 0 D6 0
Address & Code
D5 0 D4 0 D3 D2 D1 D0
Function
[0H]
0
1
0
1
1
0
1
SC3 SC2 SC1 SC0 Set Common Driver Start Line
[1H] [2H] [3H]
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1
0 0 0 1 1 1 1 0 0
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1
* *
* *
*
SC4 Temperature compensation set
TCS1TCS0
Set data length on RAM C256GLSB ABS WLS access 8-bit access or 16-bit access WBS RD RD RD Set RAM data writing mode WS2 WS1 WS0 Set electronic volume register
RAM Data Writing [4H] Select Control Electronic Volume [5H] (Lower Nibble) Electronic Volume [6H] (Upper Nibble) Register Read Control Select RF Extended Power Control Window X end address (Lower nibble) Window X End Address (Upper Nibble) Window Y End Address (Lower Nibble) Window Y End Address (Upper Nibble) [7H] [8H] [9H]
DV3 DV2 DV1 DV0
*
DV6 DV5 DV4
RA3 RA2 RA1 RA0 RF3 RF2 RF1 RF0 BF1 BF0 1 DIS
Set register address for read Select RF ratio of OSC circuit Set booster frequency Discharge capacitances of V0~V4
[AH]
0
1
0
1
1
0
1
1
0
1
0
EX3 EX2 EX1 EX0 Set X end address for window function
[BH]
0
1
0
1
1
0
1
1
0
1
1
EX7 EX6 EX5 EX4
[CH]
0
1
0
1
1
0
1
1
1
0
0
EY3 EY2 EY1 EY0 Set Y end address for window function
[DH]
0
1
0
1
1
0
1
1
1
0
1
* *
EY6 EY5 EY4
Regulator Multiple [EH] Ratio Control Register Access [FH] Control
0
1
0
1
1
0
1
1
1
1
0
RM2 RM1 RM0 Set regulator multiple ratio TST0: for LS1 test, Must set to "0" RE: set register bank number
0
1
0
1
0/1
0/1
0/1
1
1
1
1
TS RE2 RE1 RE0 T0
NOTE: Address for the control register are enclosed in brackets [ ].
* Don't Care
NOTE Use of Bank 2 and Bank 3 is prohibited.
56 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.1.3 Control Register Table (Bank 4)
Control Register
Start Address for [0H] Line Reverse (Lower Nibble) Start Address for Line Reverse [1H] (Upper Nibble) End Address for Line Reverse (Lower Nibble) End Address for Line Reverse (Upper Nibble) Line Reverse & Burst RAM Write Control EEPROM Mode Select Vop Calibration Offset (Lower Nibble) Vop calibration offset (Upper Nibble) [2H]
Pins (for 80-Family) & Bank
CSB RS WRB RDB RE2 RE1 RE0 0 1 0 1 1 0 1 D7 0 D6 0
Address & Code
D5 0 D4 0 D3 D2 D1 D0
Function
LS3 LS2 LS1 LS0 Set start line for line reverse display
0
1
0
1
1
0
1
0
0
0
1
*
LS6 LS5 LS4
0
1
0
1
1
0
1
0
0
1
0
LE3 LE2 LE1 LE0 Set end line for line reverse display
[3H]
0
1
0
1
1
0
1
0
0
1
1
* * *
LE6 LE5 LE4 Line reverse & burst RAM write control EEPROM mode select
[4H] [5H] [6H]
0 0 0
1 1 1
0 0 0
1 1 1
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 1
0 1 0
BST BT LREV M1 M0 0
CV3 CV2 CV1 CV0 Vop calibration offset select
[7H]
0 0
1 1
0 0
1 1
1 1
0 0
1 1
0 1
1 0
1 1
1 0
* *
* *
CV5 CV4 NIB1 NIB0 Select EEPROM address TST0: for LS1 test, Must set to "0" RE: set register bank number
EEPROM address [AH] Select Register Access Control
[FH]
0
1
0
1
0/1
0/1
0/1
1
1
1
1
TS RE2 RE1 RE0 T0
NOTE: Address for the control register are enclosed in brackets [ ].
* Don't Care
NOTE Use of Control Registers [8H], [9H], [BH] ~ [EH] is prohibited.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.1.4 Control Register Table (Bank 5)
Control Register
Scroll top address [0H] (Lower nibble) Scroll top address [1H] (Upper nibble) Scroll bottom address (Lower nibble) Scroll bottom address (Upper nibble) Scroll specified address (Lower nibble) Scroll specified address (Upper nibble) [2H] 0 0 0
Pins (for 80-Family) & Bank
CSB RS WRB RDB RE2 RE1 RE0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 D7 0 0 0 D6 0 0 0
Address & Code
D5 0 0 1 D4 0 1 D3 D2 D1 D0
Function
STA3 STA2 STA1 STA0 Set scroll top address
*
STA6 STA5 STA4
0 SBA3SBA2SBA1SBA0 Set scroll bottom address
[3H]
0
1
0
1
1
0
1
0
0
1
1
*
SBA6SBA5SBA4
[4H]
0
1
0
1
1
0
1
0
1
0
0 SSA3SSA2SSA1SSA0 Set scroll specified address
[5H]
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 1
1 1 1 0
0 1 1 0
1 0 1 0
*
SSA6SSA5SSA4
Scroll start address [6H] (Lower nibble) Scroll start address [7H] (Upper nibble) Scroll mode select [8H]
SAY3SAY2SAY1SAY0 Set scroll start address
* *
SAY6SAY5SAY4
*
SM1 SN0
Scroll mode select TST0: for LS1 test, Must set to "0" RE: set register bank number
Register Access Control
[FH]
0
1
0
1
0/1
0/1
0/1
1
1
1
1
TS RE2 RE1 RE0 T0
NOTE: Address for the control register are enclosed in brackets [ ].
* Don't Care
8.2
Functions of Control Registers
The EM65570 has many control registers. When accessing the control registers, the upper nibble of the data bus (D7~D4) represents the register address while the lower nibble of the data bus (D3~D0) represents data. The following figure shows an access example. The Pins CSB, RS, RDB, & WRB) settings are for the 80-family MPU interface. Only the setting of the terminals RDB & WRB are different when it is accessed by the 68-family MPU. Example (X Address):
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 0 RE0 0
Register address
Data
Pins setting
Register Bank
Figure 8-1 An Example of Accessing the Control Registers
58 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
When writing to the control register, it is used directly by addressing D7~D4 of the data bus. When reading, you must first set the RA register for the specific register address before you can read specific register. Therefore, a 2-step procedure is required to perform a read register operation. After reading, the specific register will output to D3~D0 of the data bus. All nibbles, except D3~D0, of the data bus are all "H." Access to undefined register address area is prohibited. When RS is "L," all read/write operations are accessed to display RAM. Then the data bus does not include the register address. When writing, D3~D0 data is written to the register designated at D7~D4 on the rising edge of the WRB signal. When reading, the register can output to data bus during RDB active period. The control register and display RAM have equal access sequence
8.2.1 X Address Register (AX)
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 AX3 AX2 AX1 AX0
(At the time of reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
AX7 AX6 AX5 AX4
(At the time of reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H) The AX register is set to the X-direction address of display RAM. In data setting, command is divided into lower and upper sections at 4-bit of data each in order to accommodate the required 8-bit of total data.
8.2.2 Y Address Register (AY)
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 AY3 AX2 AY1 AY0
(At the time of reset: {AY3, AY2, AY1, AY0} =0H, read address: 2H)
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
*
AY6 AY5 AY4
* Don't Care
(At the time of reset: {AY6, AY5, AY4} =0H, read address: 3H) The AY register is set to the Y-direction address of display RAM. In data setting, command is divided into lower and upper sections at 4-bit and 3-bit of data respectively in order to accommodate the required 7-bit total data. 00H to 43H are applicable to the values for AY6 to AY0, but 44H to FFH are not applicable.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 59
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.3 n Line Alternate Register (N)
D7 0 D6 1 D5 0 D4 0 D3 N3 D2 N2 D1 N1 D0 N0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {N3, N2, N1, N0} =0H, read address: 4H)
D7 0 D6 1 D5 0 D4 1 D3 D2 N6 D1 N5 D0 N4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
*
* Don't Care
(At the time of reset: {N6, N5, N4} =0H, read address: 5H) A number of the reverse lines in the LCD alternate drive is required in setting the register. This number of lines is limited to between 2 and 67 lines. The values set up by the alternate register will be enabled when the NLIN control bit is "1." When the NLIN control bit is "0," the alternate drive waveform reverses when each frame is generated.
N6 0 0 N5 0 0 N4 0 0 N3 0 0 1 0 0 0 0 1 1 N2 0 0 N1 0 0 N0 0 1 Line Address 2 67
NLIN = "0" (with 1/68 DUTY Display):
1st Line 2nd Line 3rd Line 67st Line 68th Line 1st Line
LP
FLM M
Figure 8-2a NLINE = "0" Alternate Timing Diagram
60 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
NLIN = "1"
nth line Cycle
1st Line 2nd Line 3rd Line
nth Line
1st Line 2nd Line
LP
M
Figure 8-2b NLINE = "1" Alternate Timing Diagram
8.2.4 Display Control (1) Register
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 ALL ON/ SHIFT 65K ON OFF
(At the time of reset: {SHIFT, 65K, ALLON, ON/OFF} = 4H, read address: 6H) Various display control is set up as follows: ON/OFF To turn ON/OFF the display control- ON/OFF = "0": Display OFF ON/OFF = "1": Display ON ALLON Regardless of the display data, all is ON. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display are lit 65K Select 65K gradation display 65K="0": 4096 or 256 gradation display, decided by C256 control bit. 65K="1": 65K gradation display mode. SHIFT Select the shift direction of the display scanning data in the common driver output. SHIFT = "0": COM0 COM67 shift-scan SHIFT = "1": COM67 COM0 shift-scan
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
8.2.5 Display Control (2) Register
D7 0 D6 1 D5 1 D4 1 D3 * D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 REV NLIN SWAP
(At the time of reset: {REV, NLIN, SWAP} = 0H, read address: 7H) Various display control is set up as follows: REV Sets LCD light ON/OFF control in combination with the display RAM data high/low status. REV ="0": When the RAM data is at "H," When the RAM data is at "L," REV ="1": When the RAM data is at "H," When the RAM data is at "L," NLIN The NLIN controls the n-line alternate drive ON/OFF. NLIN = "0": n-line alternate drive OFF. In each frame, the alternated signals (M) are reversed. NLIN = "1": n-line alternate drive ON. According to data set up in the n-line alternated register, the alternation is made. SWAP Swap the write data bit mode when writing data to display RAM. SWAP = "0": Normal mode. SWAP = "1": During data writing, exchange the R and B definitions of Segment outputs. LCD is at ON voltage (normal) LCD is at OFF voltage (normal) LCD is at OFF voltage (reverse) LCD is at ON voltage (reverse)
8.2.6 Increment Control Register Set
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 AXI CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 WIN AIM AYI
(At the tine of reset: {WIN, AIM, AYI, AXI} = 0H, read address: 8H) This register controls the increment mode and window function when accessing display RAM. The increment operation of the AX and AY registers is controlled by the AIM, AYI and AXI registers setting and by every write or every read access to display RAM. The AY register directly connects to display RAM as the Y address. The AX register connects to the address converter and the resulting output to display RAM as the X address in the auto increment mode. The AX and AY register are incremented, but the X and Y addresses are not incremented directly. To set this control register, the increment operation of the address can be made without setting successive addresses for writing or reading data to display RAM from MPU. The WIN register is used for window function control. WIN="0": Normal RAM access WIN="1": Window function access
62 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver When using the window function to access RAM, you should set the following registers before accessing. WIN="1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address Moreover, the following address condition must be met. Window end X address Window start X address Window end Y address Window start Y address The increment control of the X and Y addresses by AIM, AYI, and AXI registers are as follows.
AIM 0 1 Address Increment Timing When writing to display RAM or reading from display RAM This is effective when accessing successive address area Only when writing to display RAM This is used in the case of Read Modify Write AXI 0 1 0 1 Select Address Increment Operation Address is not incremented X-Address is incremented Y-Address is incremented X and Y both are incremented Remarks (1) (2) (3) (4)
AYI 0 0 1 1
NOTES: 1. Regardless of AIM value, the AX and AY registers do not increment 2. The X address automatically changes according to the AIM setting
Transition of AX Register 00H 01H ....... maxH* Transition of X Address Same as AX register
3. The Y address automatically changes according to the AIM setting
Transition of AY Register 00H 01H ....... 43H Transition of Y Address Same as AY register
4. Change the X and Y address accordingly to the AIM setting. When the X address exceed maxH*, Y address increment occurs
Transition of AX and AY Register AX: 00H 00H maxH* AY: When each AX exceeds maxH,* AY increments 00H 00H 43H Same as AX and AY register Transition of X and Y Address
*maxH: The maximum internal X-address in each access mode
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
5. The following shows address increment in window function access.
Transition of AX and AY Register AX: START Address START Address+1 END Address Same as AX and AY register Transition of X and Y Address
AY: When each AX exceed AE, increment AY START Address START Address+1 END Address
Under each operation mode, the following increment operation is performed: When gradation display mode and 8-bit access are selected, address is incremented as described above. When gradation display mode and 16-bit access are selected, the following increment processing occurs: 1) Accessing the RAM after every two bytes are accessed. 2) The X-addresses increments in the order of 00H, 01H,...2FH, and 30H.
8.2.7 Power Control Register
D7 1 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 AMPON HALT DCON ACL
(At the time of reset: {AMPON, HALT, DCON, ACL} = 0H, read address: 9H) ACL The internal circuit can be initialized as follows: ACL = "0": Normal operation ACL = "1": Initialization ON When the reset operation begins internally after the ACL register is set to "1," the ACL register is automatically cleared to "0." The internal reset signal is generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install at least two cycles for the WAIT period for the clock display. After the WAIT period elapsed, the next operation is processed. DCON Sets ON/OFF the internal booster circuit: DCON = "0": Booster circuit OFF DCON = "1": Booster circuit ON
64 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver HALT The power saving operating condition is set ON/OFF with this command. HALT = "0": Normal operation HALT = "1": Power-saving operation When the power-saving state is set, the power consumption can be decreased to almost equal the standby power consumption. The internal condition during power saving are as follows: 1) The oscillating circuit and power supply circuit are stopped. 2) The LCD drive is stopped, and output of the segment and common drivers are at VSS level. 3) The clock input from CK pin is forbidden. 4) The contents of Display RAM data are stored. 5) The operational mode stores the state of command executed before executing the power saving command. AMPON Sets the internal OP-AMP circuit block ON/OFF (voltage regulator, electronic volume, and voltage conversion circuit). AMPON = "0": The internal OP-AMP circuit is OFF AMPON = "1": The internal OP-AMP circuit is ON
8.2.8 LCD Duty (DS)
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 DS3 DS2 DS1 DS0
(At the time of reset: {DS3, DS2, DS1, DS0} = FH, read address: AH) The DS register set and its corresponding LCD display width and duty:
DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display Width and Duty 1/8 duty 1/12 duty 1/16 duty 1/20 duty 1/24 duty 1/28 duty 1/32 duty 1/36 duty 1/40 duty 1/44 duty 1/48 duty 1/52 duty 1/56 duty 1/60 duty 1/64 duty 1/68 duty
Partial display can be made possible by setting an arbitrary duty ratio.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
8.2.9 Booster Setup (VU)
D7 1 D6 0 D5 1 D4 1 D3 0 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 VU2 VU1 VU0
(At the time of reset: {0,VU2,VU1,VU0} = 5H, read address: BH) The booster steps set to VU register
VU2 0 0 0 0 1 1 1 1 VU1 0 0 1 1 0 0 1 1 VU0 0 1 0 1 0 1 0 1 Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output 5 times voltage output 6 times voltage output Prohibit code Prohibit code
8.2.10 Bias Sett ing Register (B)
D7 1 D6 1 D5 0 D4 0 D3 D2 B2 D1 B1 D0 B0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0
*
* Don'tCare
(At the time of reset: {B2, B1, B0} = 5H, read address: CH) This register is used to set a bias ratio. A bias ratio can be selected from 1/4 to 1/9 by setting B2, B1, and B0.
B2 0 0 0 0 1 1 B1 0 0 1 1 0 0 B0 0 1 0 1 0 1 Bias 1/4 Bias 1/5 Bias 1/6 Bias 1/7 Bias 1/8 Bias 1/9 Bias
66 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.11 Register Access Control
D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0/1 0/1 0/1 TST0 RE2 RE1 RE0
(At the time of reset: {TST0, RE2, RE1, RE0} = 0H, read address: FH) Set the RE register to select the register bank number. To access each control register, set the RE register first. The TST0 register is used to test LSI. Therefore this register must be set to "0"
8.2.12 Display Start Common
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1 SC3 SC2 SC1 SC0
(Read address=0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 SC4 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
*
*
*
* Don't Care
(Read address=1H) (At the time of reset:{SC4,SC3,SC2,SC1,SC0} = 0H) The SC register sets the scanning start output of the common driver.
SC4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 SC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Display Starting Common When SHIFT=0 When SHIFT=1 COM0~ COM67~ COM4~ COM63~ COM8~ COM59~ COM12~ COM55~ COM16~ COM51~ COM20~ COM47~ COM24~ COM43~ COM28~ COM39~ COM32~ COM35~ COM36~ COM31~ COM40~ COM27~ COM44~ COM23~ COM48~ COM19~ COM52~ COM15~ COM56~ COM11~ COM60~ COM7~ COM64~ COM3~
SHIFT="0": COM0 to COM67 shift-scan SHIFT="1": COM67 down to COM0 shift-scan
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
8.2.13 Temperature Compensation Set
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
*
*
TCS1 TCS0
* Don'tCare
(At the time of reset:{ TCS1,TCS0 } = 0H, read address: 2H)
TCS1 0 0 1 1 TCS0 0 1 0 1 Temperature Compensation Slope -0.05% per C -0.1% per C -0.15% per C -0.2% per C
VREF (T) (Temperature compensation output voltage) is controlled by TCS1, TCS0, and previous environment temperature T.
VREF (T ) = V REF 0 [(1 + TCS (T - 25 0 C )]
TCS is selected by TCS1 and TCS0 VREF0 = 1.5V at 25C
LCD driving voltage
TCS: 00 -0.05% / C TCS: 01 -0.1% / C TCS: 10 -0.15% / C TCS: 11 -0.2% / C
Temperature
Figure 8-3 Temperature Compensation Slope
68 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.14 RAM Data Length Set
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 1 C256 GLSB ABS WLS
(At the time of reset: {C256, GLSB, ABS, WLS} = 0H, read address: 3H) The WLS register selects data bus size for accessing from MPU. WLS = "0": The data bus size is 8-bit in width WLS = "1": The data bus size is 16-bit in width When MPU accesses the control register using the 16-bit bus, high byte data is ignored. ABS ABS= "0": normal mode ABS= "1": change corresponding bit from the input data bus GLSB In 256-color mode for segment driver of 4-gradation display, select 4 gradations from 8 gradations using the 2 bits written to the corresponding RAM area and the 1 bit supplemented by the gradation LSB circuit. Supplement the 1 bit of data by setting the gradation LSB register (GLSB). Gradation LSB = "0": Selects 0 as the LSB information on the RAM for the 4-gradation segment driver. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment driver. C256 C256= "0": 4096-color mode C256= "1": 256-color mode
NOTE When you use C256, you can NOT set 65K to 1.
8.2.15 RAM Data Writing Select Control
D7 D6 D5 D4 0 1 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 1 0 WBS RDWS2 RDWS1 RDWS0
(At the time of reset: {WBS, RDWS2, RDWS1, RDWS0} = 0H, read address: 4H) The WBS bit selects the byte writing sequence while displaying RAM data. WBS= 0: Write low byte first WBS= 1: Write high byte first The RDWS[2:0] selects the RAM data writing mode shown in the following figure.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
Column 0 -> 97
Column 0 -> 97
Row 0 -> 67
Row 0 -> 67
RDWS[2:0]=(0,0,0)
Column 0 -> 97
RDWS[2:0]=(0,0,1)
Column 0 -> 97
Row 0 -> 67
Row 0 -> 67
RDWS[2:0]=(0,1,0)
Column 0 -> 97
RDWS[2:0]=(0,1,1)
Column 0 -> 97
Row 0 -> 67
Row 0 -> 67
RDWS[2:0]=(1,0,0)
Column 0 -> 97
RDWS[2:0]=(1,0,1)
Column 0 -> 97
Row 0 -> 67
Row 0 -> 67
RDWS[2:0]=(1,1,0)
RDWS[2:0]=(1,1,1)
Figure 8-4 The RAM Data Writing Mode Selection by RDWS[2:0] 70 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.16 Electronic Volume Register
D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 DV3 DV2 DV1 DV0
(Read address: 5H)
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
*
DV6 DV5 DV4
* Don'tCare
(Read address: 6H) (At the time of reset: {DV6~DV0} = 00H) The DV register controls the VBA voltage.
DV6 0 0 DV5 1 1 DV4 0 0 DV3 0 0 1 0 DV2 0 0 DV1 0 0 DV0 0 1 Output Voltage 32 33 95 96
1 1
0 1
1 0
1 0
1 0
1 0
The output voltage at VBA is specified by the following equation: VBA = (1+ (M+offset)/381) * VREF
Where: M: DV register value offset: CV register value VREF: temperature compensation output voltage
The VBA range is from 1.5V to 2V at 25C. The LCD drive voltage V0 is determined by the VBA level and the RM register value as shown in the following equation: V0 = VBA * N
N: RM register value NOTE When using EEPROM function (CV) to tune VBA offset, limit DV value to 32~96 to prevent getting incorrect VBA value due to (M+offset) overflow or underflow.
In order to prevent transient voltage generation when an electronic volume code is set, design the circuit in such a way that the set value is not reflected as a level immediately after the upper bits (DV6-DV4) of the set electronic code. The set value becomes valid only when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
NOTE When writing code to set the electronic volume register, you must set DV6~DV4 first, then followed by DV3~DV0 setting.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
8.2.17 Internal Register Read Address
D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 RA3 RA2 RA1 RA0
(At the time of reset: {RA3, RA2, RA1, RA0} = 7H) Use the RA register to specify the address for the register read operation. The EM65570 has many registers and register banks. Therefore, a 4-step operation is required to read the specific register. 1) Write 01H to the RE register for accessing the RA register 2) Write specific register address to the RA register 3) Write the specific register bank to the RE register 4) Read specific contents
8.2.18 Resistance Ratio of CR Oscillator
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 RF3 RF2 RF1 RF0
(At the time of reset: {RF3, RF2, RF1, RF0} = 0H, read address: 8H) The RF registers control the resistance ratio of the CR oscillator. Therefore, the frame frequency will change the RF register settings. When changing the RF register values, you need to check the LCD display quality.
RF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Initial Resistance Ratio 0.72 times of initial Resistance Ratio 0.76 times of initial Resistance Ratio 0.8 times of initial Resistance Ratio 0.84 times of initial Resistance Ratio 0.88 times of initial Resistance Ratio 0.92 times of initial Resistance Ratio 0.96 times of initial Resistance Ratio 1.04 times of initial Resistance Ratio 1.08 times of initial Resistance Ratio 1.12 times of initial Resistance Ratio 1.16 times of initial Resistance Ratio 1.2 times of initial Resistance Ratio 1.24 times of initial Resistance Ratio 1.28 times of initial Resistance Ratio Prohibit Code
72 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.19 Extended Power Control
D7 1 D6 0 D5 0 D4 1 D3 D2 D1 1 D0 DIS CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 BF1 BF0
(At the time of reset: {DIS} = 0H, {BF1, BF0}=0H; read address: 9H) The DIS register controls the capacitors (connected between the power supply V0-V4 for LCD drive voltage and VSS) discharge. When using this register, refer to Section 7-22 (Discharge Circuit). DIS = "0": Discharge OFF DIS = "1": Discharge start BF1~BF0: Select the operating frequency in the booster. When the boosting frequency is high, the driving ability of the booster becomes high, and the power consumption is increased. When you adjust the boosting frequency, you must take into considerations the external capacitors and the current consumption.
BF1 0 0 1 1 BF0 0 1 0 1 Operating Clock Frequency in the Booster 1.5K Hz * 8 1.5K Hz * 4 1.5K Hz * 2 1.5 K Hz
8.2.20 Window End X Address
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 EX3 EX2 EX1 EX0
(At the time of reset: {EX3, EX2, EX1, EX0} = 0H, read address: AH)
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
EX7 EX6 EX5 EX4
(At the time of reset: {EX7, EX6, EX5, EX4} = 0H, read address: BH) The EX registers set the X direction end address for the window function.
8.2.21 Window End Y Address
D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 EY3 EY2 EY1 EY0
(At the time of reset: {EY3, EY2, EY1, EY0} = 0H, read address: CH)
D7 1 D6 1 D5 0 D4 1 D3 * D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
EY6 EY5 EY4
(At the time of reset: {EY6, EY5, EY4} = 0H, read address: DH) The EY registers set the Y direction end address for the window function.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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8.2.22 Regulator Multiple Ratio Control
D7 1 D6 1 D5 1 D4 0 D3 * D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1 RM2 RM1 RM0
(At the time of reset: {RM2, RM1, RM0} = 5H, read address: EH) Set the RM register to specify the booster step.
RM2 0 0 0 0 1 1 1 1 RM1 0 0 1 1 0 0 1 1 RM0 0 1 0 1 0 1 0 1 Regulator Multiple Ratio Control 3.0 times voltage output 3.6 times voltage output 4.5 times voltage output 5.0 times voltage output 5.5 times voltage output 6.0 times voltage output 7.0 times voltage output 8.0 times voltage output
8.2.23 Line Reverse Start Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 LS3 LS2 LS1 LS0
(At the time of reset: {LS3, LS2, LS1, LS0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
*
LS6 LS5 LS4
* Don'tCare
(At the time of reset: {LS6, LS5, LS4} = 0H, read address: 1H) The LS registers set the line reverse start address under the following conditions: 00H LS 43H LS LE
LE: Line reverse end address
8.2.24 Line Reverse End Address
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 LE3 LE2 LE1 LE0
(At the time of reset: {LE3, LE2, LE1, LE0} = 0H, read address: 2H)
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
*
LE6 LE5 LE4
* Don't Care
(At the time of reset: {LE6, LE5, LE4} = 0H, read address: 3H)
74 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver The LE registers set the line reverse end address under the following conditions: 00H LS 43H LS LE
LS: Line reverse start address
8.2.25 Line Reverse Control
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
*
BST BT LREV
* Don't Care
(At the time of reset: {BST, BT, LREV} = 0H, read address: 4H) The BST register controls the Fast Burst RAM write function BST = "0": Burst RAM write function OFF BST = "1": Burst RAM write function ON The LREV registers control the line reverse display function. LREV = "0": Normal display (not reversed) LREV = "1": Line reverse display enabled The area specified by the Line Reverse Start/End Register reverses the display. The reverse type is selected by the BT register. When using the Line Reverse Display function, LS and LE registers must meet the following condition: LS LE The BT register controls the line reverse type. This is an option of the line reverse display function. This BT setting is only available when LREV="1" BT = "0": Reverse display BT = "1": Reverse display at each 32 frame.
Display change each 32 frame
Figure 8-5a Blink Example (LREV = 1, BT = 1)
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
ELAN LCD DRIVER Low Power and Low Voltage
Display change each 32 frame
ELAN LCD DRIVER Low Power and Low Voltage
Line reverse start add Line reverse end add
Figure 8-5b Blink Example (LREV = 1, BT = 1) Indicating Line Reverse Start/End Address Positions
8.2.26 EEPROM Mode Select Register
D7 0 D6 1 D5 0 D4 1 D3 * D2 M1 D1 M0 D0 0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0
(At the time of reset: {M1, M0} = 3H, read address: 5H) The (M1, M0) register controls the EEPROM operating mode as summarized below.
(M1,M0) 00 01 10 11 EEPROM Operating Mode Read Program Erase Reserve Delay Time 10 uS 4 mS 4 mS VDD Voltage Required 2.4V 2.8V 2.8V -
8.2.27 Vop Calibration Offset Register
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 CV3 CV2 CV1 CV0
(At the time of reset: {CV4, CV3, CV2, CV1} = 0H, read address: 6H)
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
CV5 CV4
(At the time of reset: {CV5, CV4} = 0H, read address: 7H)
76 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver The CV5~CV0 registers control the Vop calibration offset voltage selection. VBA = (1+ (M + offset) / 381)* VREF
M: DV register setting offset: CV5~CV0 setting CV5~CV0 011111 011110 ... 000001 000000 100000 100001 ... 111111 Calibration Offset +31 +30 ... +1 0 -32 -31 ... -1
8.2.28 EEPROM Address Select Register
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0
*
*
NIB1 NIB0
* Don't Care
(At the time of reset: {NIB1, NIB0} = 0H, read address: AH) The NIB register selects low nibble or high nibble data to access from EEPROM.
NIB1 0 0 NIB0 0 1 EEPROM Address Bank 4[6H] (CV3~CV0) Bank 4[7H] (CV5~CV4)
NOTE 1: When setting CV5~CV0, you must set CV5~CV4 (upper nibble register) first, then set CV3~CV0 (lower nibble register), and then start to program. 2: The programming sequence of CV5~CV4 and CV3~CV0 is not restricted. 3: When reading from CV5~CV0, you must read EEPROM data to CV5~CV4 (upper nibble register) first, then read the EEPROM data to CV3~CV0 (lower nibble register).
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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68COM/ 98SEG 65K Color STN LCD Driver
8.2.29 Scroll Top Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 STA3 STA2 STA1 STA0
(At the time of reset: {STA3, STA2, STA1, STA0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
*
STA6 STA5 STA4
* Don't Care
(At the time of reset: {STA6, STA5, STA4} = 0H, read address: 1H) Sets the top address of scroll data area in RAM under the following condition: 0 <= Scroll top address <= 67 Scroll top address < Scroll bottom address
8.2.30 Scroll Bottom Address
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 SBA3 SBA2 SBA1 SBA0
(At the time of reset: {SBA3, SBA2, SBA1, SBA0} = 3H, read address: 2H)
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1
*
SBA6 SBA5 SBA4
* Don't Care
(At the time of reset: {SBA6, SBA5, SBA4} = 4H, read address: 3H) Set the bottom address of scroll data area in RAM under the following condition: 0 <= Scroll bottom address <= 67 Scroll top address < Scroll bottom address
8.2.31 Scroll Specified Address
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 SSA3 SSA2 SSA1 SSA0
(At the time of reset: {SSA3, SSA2, SSA1, SSA0} = 0H, read address: 4H)
D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1
* SSA6 SSA5 SSA4
* Don't Care
(At the time of reset: {SSA6, SSA5, SSA4} = 0H, read address: 5H) Depending on the size of the display panel or of the duty ratio selection, set the specified address in RAM to jump to the scroll bottom address and then show the fixed data area. Scroll specified address = scroll top address + panel scroll area - 1
78 * Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
8.2.32 Scroll Start Address
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 SAY3 SAY2 SAY1 SAY0
(At the time of reset: {SAY3, SAY2, SAY1, SAY0} = 0H, read address: 6H)
D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
* SAY6 SAY5 SAY4
* Don't Care
(At the time of reset: {SAY6, SAY5, SAY4} = 0H, read address: 7H) Set the starting address of the area scrolling and then execute the area scroll operation. The scroll start address must be in the scrolling area. Scroll top address <= Scroll start address <= Scroll bottom address
NOTE To avoid any errors when setting the Scroll start address registers, set SAY[6:4] (Bank 5[7H]) first, then set SAY[3:0] (Bank 5[6H].
8.2.33 Scroll Mode Select
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
*
*
SM1 SM0
* Don't Care
(At the time of reset: {SM1, SM0} = 0H, read address: 8H)
SM1 0 0 1 1
SM[1:0]=00
SM0 0 1 0 1
SM[1:0]=01
Type of Area Scroll Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
SM[1:0]=10 SM[1:0]=11
Center screen
Top screen
Bottom screen
Whole screen
: Fixed area
: Scroll area
Figure 8-6 Types of Area Scroll Modes Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
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9
Absolute Maximum Rating
9.1 Absolute Maximum Ratings
Item Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Supply voltage (5) Supply voltage (6) Input voltage Storage temperature Symbol VDD VEE VOUT VBA V0 V1,V2,V3,V4 VI Tstg Ta=25 Condition Pin Used VDD VEE VOUT VBA V0 V1,V2,V3,V4 * Rating -0.3 ~ + 4.0 -0.3 ~ + 4.0 -0.3 ~ + 18.0 1.5 ~ + 2.0 -0.3 ~ + 16.0 -0.3 ~ V0+ 0.3 -0.3 ~ VDD+ 0.3 -45 ~ +125 C V Unit
* CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST, and D0 ~ D15 pins
9.2 Recommended Operating Conditions
Item Symbol VDD1 Supply Voltage VDD2 VEE V0 Operating Voltage VOUT VBA VREF Operating Temperature
1
Pin VDD VDD VEE V0 VOUT VBA VREF -
Min. 2.2 2.4 2.4 4.5
Type -
Max. 3.3 3.3 3.3 16 20 2.0 85
Unit Remarks V V V V V V V C
*1 *2 *3 *4 *5
-
1.5 -30
1.5 -
Topr
* Power supply for logic circuit *2 Power supply for analog circuit *3 Power supply for internal boosting circuit. If you applied the same voltage as
VDD, connect to VDD
*4 Voltage V0>V1>V2>V3>V4>VSS must always be satisfied *5 Voltage VOUT > V0 must always be satisfied
80 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
10 DC Electrical Characteristics
VSS=0V, VDD = 2.2 ~3.3V, Ta = -30 ~85 C
Item High level input voltage Low level input voltage High level output current Low level output current High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance Standby current through VDD pin Oscillator frequency (65k color mode) Oscillator frequency (4k color mode) Oscillator frequency (256 color mode) Symbol VIH VIL IOH1 IOL1 IOH2 IOL2 ILI1 ILO RON ISTB Fosc1 Condition VOH = VDD-0.4V VOL= 0.4V VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VDD |Von| = 0.5V V0=10V V0=6V CK=0, CSB=VDD, Ta=25 C, VDD=3V VDD=3V, Ta=25 C, Rf setting = (Rf3, Rf2, Rf1, Rf0) = (0000) VDD=3V, Ta=25 C, Rf setting = (Rf3, Rf2, Rf1, Rf0) = (0000) VDD=3V , Ta=25 C, Rf setting = (Rf3, Rf2, Rf1, Rf0) = (0000) Six times boosting RL= 500K (VOUT-VSS) Five times boosting RL= 500K (VOUT-VSS) Four times boosting RL= 500K (VOUT-VSS) Three times boosting RL= 500K (VOUT-VSS) Two times boosting RL= 500K(VOUT-VSS) VDD= 3V, 6 times booster All ON pattern VDD= 3V, 6 times booster Checker pattern Minimum 0.8VDD 0 -2.7 2.7 -0.8 0.8 -2 -2 1.0 1.2 Typical 0.9VDD 0.1VDD -3.2 3.2 -1.0 1.0 0 0 1.3 1.7 5 281 290 Maximum Unit VDD 0.2VDD -3.5 3.5 -1.2 1.2 2 2 1.6 2.2 15 299 V V mA mA mA mA A A K A KHz Pin Used
*1 *1 *2 *2 *3 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 *16 *17
Fosc2
138
140
144
KHz
Fosc3 VOUT1 VOUT2
63 6*VEE *0.95 5*VEE *0.95 4*VEE *0.95 3*VEE *0.95 2*VEE *0.95
65 6*VEE *0.98 5*VEE *0.98 4*VEE *0.98 3*VEE *0.98 2*VEE *0.98 300 350
67 6*VEE *0.99 5*VEE *0.99 4*VEE *0.99 3*VEE *0.99 2*VEE *0.99
KHz V V V V V A A
Booster output voltage on VOUT VOUT3 pin VOUT4 VOUT5 IDD1 IDD2
Current consumption
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 81
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
Item VBA output voltage VREF output voltage V0 output voltage
Symbol VBA VREF V0
*1 *2 *3 *4 *5 *6
Condition VDD =2.4V~3.3V VDD = 2.4 ~ 3.3V VDD = 2.4 ~ 3.3V
Minimum 1.5 0.99*V0
Typical 1.5 V0
Maximum Unit 2.0 1.01*V0 V V
Pin Used
*18 *19
-
D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, & TEST pins. D0 ~ D15 pins CLK pins CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, & TEST pins Applied when D0 ~ D15 are in the state of high impedance. SEGA0 ~ SEGA97, SEGB0 ~ SEGB97, SEGC0 ~ SEGC97, COM0 ~ COM67 pin resistance when 0.5V is applied between each output pin and to each power supply (V0, V1, V2, V3, V4) and when applied 1/9 bias. VDD pin. VDD pin current is without load when the original oscillating clock is stopped and when CSB=VDD. Oscillator frequency, when using the built-in oscillating circuit (65k-color mode) Oscillator frequency, when using the built-in oscillating circuit (4k-color mode) Oscillator frequency, when using the built-in oscillating circuit (256-color mode) VOUT pin. This pin applies when the following conditions are met: The built-in oscillator circuit is used; the built-in power supply is used; the voltage (boosted 6 times) is used; VEE = 2.4 ~ 3.3; and the electronic control is preset (with code "1 1 1 1 1 1 1"). Measuring conditions: bias=1/4~1/9; 1/68 duty; LCD driver pin is without load; RL=500 K (between VOUT and VSS); C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; BF="11". VOUT pin. This pin applies when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; the voltage (boosted 5 times) is used; VEE = 2.4 ~ 3.3; and the electronic control is preset (with code "1 1 1 1 1 1 1"). Measuring conditions: bias=1/4~1/9; 1/68 duty; LCD driver pin is without load; RL=500 K (between VOUT and VSS); C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; BF="11". VOUT pin. This pin applies when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; the voltage (boosted 4 times) is used; VEE = 2.4 ~ 3.3; and the electronic control is preset (with code "1 1 1 1 1 1 1"). Measuring conditions: bias=1/4~1/9; 1/68 duty; without load; RL=500 K (between VOUT and VSS); C1=C2=1.0F; C3=0.1F; DCON=AMPON="1," BF="11". VOUT pin. This pin applies when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; the voltage (boosted 3 times) is used; VEE = 2.4 ~ 3.3; and the electronic control is preset (with code "1 1 1 1 1 1 1"). Measuring conditions: bias=1/4~1/9; 1/68 duty; LCD driver pin is without load; RL=500 K (between VOUT and VSS); C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; BF="11".
*7
*8 *9 *10 *11
*12
*13
*14
82 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
*15
VOUT pin. This pin applies when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; the voltage (boosted 2 times) is used; VEE = 2.4 ~ 3.3; and the electronic control is preset (with code "1 1 1 1 1 1 1"). Measuring conditions: bias=1/4~1/9; 1/68 duty; LCD driver pin is without load; RL=500 K (between VOUT and VSS); C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; BF="11". VDD, VEE pins. These pins apply when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; there is no access from MPU; voltage (boosted 6 times) is used; and the electronic control is preset (with code "1 1 1 1 1 1 1"); Display is ALL ON pattern {Rf3, Rf2, Rf1, Rf0 = ("0 0 0 0 ") }; and the LCD driver pin is without load. Measuring conditions: VDD=VEE; VBA=VREF; C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; NLIN="0"; (BF1,BF0)=(1,1); 1/68 duty; 1/9 bias; BF="11". VDD, VEE pins. These pins apply when the following conditions are met: The built-in oscillator circuit and built-in power supply are used; there is no access from MPU; voltage (boosted 6 times) is used; and the electronic control is preset (with code "1 1 1 1 1 1 1"); Display is ALL ON pattern {Rf3, Rf2, Rf1, Rf0 = ("0 0 0 0 ") }; and the LCD driver pin is without load. Measuring conditions: VDD=VEE; C1=C2=1.0F; C3=0.1F; DCON=AMPON="1"; NLIN="0"; (BF1,BF0)=(1,1); 1/68 duty; 1/9 bias; BF="11". VBA pin. Measuring conditions: N times boosting (N=2~6); electronic control = "1 1 1 1 1 1 1"; DCON=AMPON="1"; NLIN="0"; 1/68 duty; VDD=VEE; VBA=VREF; C1=C2=1.0F; C3=0.1F; and the LCD driver pin is without load. VREF pin. Measuring conditions: VDD = 3 volt; N times boosting (N=2 ~ 6); electronic control = "1 1 1 1 1 1 1"; DCON=AMPON="1"; NLIN="0"; 1/68 duty.
*16
*17
*18
*19
The following shows the relationship of the oscillator frequency (fosc) and external clock frequency (fCK) with the LCD frame frequency (fFLM) under each display mode.
Original Oscillating Clock When using built-in oscillator circuit (fosc) Display Mode 1/68 to 1/44 Simple gradation (65K color) Simple gradation (256 color)
fosc/(2*31*D)
Ratio of Display Duty Cycle (1/D) 1/40 to 1/24
fosc/(4*31*D) fosc /(4*15*D) fosc /(4*7*D) fCK /(4*31*D) fCK /(4*15*D) fCK /(4*7*D)
1/20 to 1/12
fosc/(8*31*D) fosc /(8*15*D) fosc /(8*7*D) fCK /(8*31*D) fCK /(8*15*D) fCK /(8*7*D)
1/8
fosc /(16*31*D) fosc /(16*15*D) fosc /(16*7*D) fCK /(16*31*D) fCK /(16*15*D) fCK /(16*7*D)
Simple gradation (4096 color) fosc /(2*15*D)
fosc /(2*7*D)
Simple gradation (65K color) fCK /(2*31*D) When using external clock Simple gradation (4096 color) fCK /(2*15*D) from CK pin (fCK) Simple gradation (256 color) fCK /(2*7*D)
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 83
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
11 AC Electrical Characteristics
NOTE All the timings must be specified relative to 20% and 80% of theVDD voltage.
11.1 80-Family MCU Write Timing
tAS8 tAH8
CSB RS
tWRLW8 WRB tDS8 tWRHW8 tDH8
D0-D15
tCYCWR8
Figure 11-1 80-Family MCU Write Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 200 30 135 60 5 Typical Max. Unit ns ns ns ns ns ns ns Pin Used CSB RS WRB (R/WB) D0~D15
Write system cycle time tCYCWR8
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time Write pulse "L" width Write pulse "H" width Data setup time Data hold time 84 * Symbol tAH8 tAS8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 250 50 160 80 10 Typical Max. Unit ns ns ns ns ns ns ns Pin Used CSB RS WRB (R/WB) D0~D15
Write system cycle time tCYCWR8
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH8 tAS8 Condition Min. 0 0 500 100 350 100 20 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 WRB (R/WB) Pin Used CSB RS
Write system cycle time tCYCWR8 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tWRLW8 tWRHW8 tDS8 tDH8
11.2 80-Family MCU Read Timing
tAS8 CSB RS tAH8
RDB
tRDLW8 tRDHW8 tRDD8 tRDH8
D0-D15
tCYCRD8
Figure 11-2 80-Family MCU Read Timing Diagram
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH8 tAS8 Condition Min. 0 0 380 200 170 CL = 80 pF 10 210 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Read system cycle time tCYCRD8 Read pulse "L" width Read pulse "H" width Data setup time Data hold time tRDLW8 tRDHW8 tRDD8 tRDH8
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 85
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH8 tAS8 Condition Min. 0 0 540 290 230 CL = 80 pF 10 300 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Read system cycle time tCYCRD8 Read pulse "L" width Read pulse "H" width Data setup time Data hold time tRDLW8 tRDHW8 tRDD8 tRDH8
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85
Item Address hold time Address setup time Symbol tAH8 tAS8 Condition Min. 0 0 840 440 380 CL = 80 pF 10 450 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Read system cycle time tCYCRD8 Read pulse "L" width Read pulse "H" width Data setup time Data hold time tRDLW8 tRDHW8 tRDD8 tRDH8
11.3 68-Family MCU Write Timing
tAS6 CSB RS tAH6
R/WB (WRB)
E (RDB)
tEHW6
tELW6
tDS6
tDH6
D0-D15 tCYCWR6
Figure 11-3 68-Family MCU Write Timing Diagram
86 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
VSS=0V, VDD = 2.7 ~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 200 30 135 60 5 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Write system cycle time tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
VSS=0V, VDD = 2.4 ~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 250 50 160 80 10 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Write system cycle time tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
VSS=0V, VDD = 2.2 ~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 500 100 350 100 20 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Write system cycle time tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 87
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
11.4 68-Family MCU Read Timing
tAS6 CSB RS tAH6
R/WB (WRB)
E (RDB)
tEHW6
tELW6
tRDD6 D0-D15
tRDH6
tCYCRD 6
Figure 11-4 68-Family MCU Read Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 380 200 170 CL=50pF 210 10 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Read system cycle time tCYCRD6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tRDD6 tRDH6
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 540 290 230 CL=50pF 300 10 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Read system cycle time tCYCRD6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tRDD6 tRDH6
88 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 1000 450 500 CL=50pF 650 10 Typical Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSBRS
Read system cycle time tCYCRD6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tRDD6 tRDH6
11.5 Serial Interface Timing Diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS tAHS tSHW tDHS
D0-D15
tCYCS
Figure 11-5 Serial Interface Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40 Typical Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin Used
SDA
CSB
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 89
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 50 50 80 80 50 60 Typical Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin Used
SDA
CSB
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 230 100 100 80 80 100 100 80 100 Typical Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin Used
SDA
CSB
90 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
11.6 Clock Input Timing
tCKLW CK tCKHW
Figure 11-6 Clock Input Timing Diagram
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85 C
Item CK pulse "H" width CK pulse "L" width CK pulse "H" width CK pulse "L" width CK pulse "H" width CK pulse "L" width Symbol tTCKHW tCKLW tTCKHW tCKLW tTCKHW tCKLW Min. 1.5 Typical Max. 1.6 Unit s Pin Used CK
1
2.9
-
3.5
s
CK
2
6.3
-
7.6
s
CK
3
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item CK pulse "H" width CK pulse "L" width CK pulse "H" width CK pulse "L" width CK pulse "H" width CK pulse "L" width
1 2 3
Symbol tTCKHW tCKLW tTCKHW tCKLW tTCKHW tCKLW
Min. 1.5
Typical -
Max. 1.6
Unit s
Pin Used CK
1
2.9
-
3.5
s
CK
2
6.3
-
7.6
s
CK
3
Applicable only when the simple gradation 65K color mode is used. Applicable only when the simple gradation 4096 color mode is used. Applicable only when the simple gradation 256 color mode is used.
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 91
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
11.7 Reset Timing
tR W tR
RESB
internal state
reset m ode
norm al dsiplay
Figure 11-7 Reset Timing Diagram
VSS=0V, VDD = 2.2~3.3V, Ta = -30~+85 C
Item Reset time Reset pulse "L" width Symbol tR tRW 80 Condition Min. Typ. Max. 1 Unit s s RESB Pin Used
12
Application Circuit
12.1 Connected to 80-Family MCU
VCC A0 A1 to A7 80 family MPU Decoder /IORQ D0 to D15 /RD /WR /RES GND CSB RS
VDD
D0 to D15 RDB WRB RESB VSS
Figure 12-1 Connected to 80-Family MCU Application Circuit Diagram
92 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
EM65570
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
12.2 Connected to 68-Family MCU
VCC A0 A1 to A15 68 family MPU Decoder VMA D0 to D15 E R/W /RES GND CSB RS
VDD
D0 to D15 RDB(E) WRB(R/W) RESB VSS
Figure 12-2 Connected to 68-Family MCU Application Circuit Diagram
12.3 Connected to Serial Interface MCU
VCC A0 A1 to A7 MPU RS CSB
VDD
Decoder
PORT1 PORT2 /RES GND
SDA SCL RESB VSS
Figure 12-3 Connected to Serial Interface MCU Application Circuit Diagram
EM65570
EM65570
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
* 93
EM65570
68COM/ 98SEG 65K Color STN LCD Driver
13 Packing Tray Dimensions
Figure 13-1 EM65570 Packing Tray Dimensional Diagram
Tray Dimensions (Unit: mm)
Symbol L1 L2 L3 T X Y Z Dimensions 50.80 45.50 45.80 4.00 18.21 0.05 1.47 0.05 0.64 0.05 Symbol Px Py Dx Dy TPy N Dimensions 18.71 1.97 6.94 5.94 41.37 44 -
94 *
Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)

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