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250 kSPS, 12-Bit Impedance Converter, Network Analyzer AD5934
FEATURES
Programmable output peak-to-peak excitation voltage to a max frequency of 100 kHz Programmable frequency sweep capability with serial I2C(R) interface Frequency resolution of 27 bits (<0.1 Hz) Impedance measurement range from 100 to 10 M Phase measurement capability System accuracy of 0.5% 2.7 V to 5.5 V power supply operation Temperature range -40C to +125C 16-lead SSOP package
GENERAL DESCRIPTION
The AD5934 is a high precision impedance converter system solution which combines an on-board frequency generator with a 12-bit, 250 kSPS, analog-to-digital converter (ADC). The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and a discrete Fourier transform (DFT) is processed by an on-board DSP engine. The DFT algorithm returns a real (R) and imaginary (I) data-word at each output frequency. The magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated using the following two equations:
APPLICATIONS
Electrochemical analysis Bioelectrical impedance analysis Impedance spectroscopy Complex impedance measurement Corrosion monitoring and protection equipment Biomedical and automotive sensors Proximity sensing Nondestructive testing Material property analysis Fuel/battery cell condition monitoring
Magnitude =
R2 + I 2
Phase = Tan -1 (I / R)
Table 1. Related Devices
Part No. AD5933 Description 2.7 V to 5.5 V. 1 MSPS, 12-bit impedance, with internal temperature sensor, 16-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
MCLK AVDD DVDD
DDS CORE (27 BITS)
DAC ROUT VOUT
SCL SDA
I2C INTERFACE Z()
AD5934
REAL REGISTER IMAGINARY REGISTER RFB 1024-POINT DFT
VIN ADC (12 BITS) GAIN LPF VDD/2
05325-001
AGND
DGND
Figure 1. Rev. 0
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AD5934 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 I2C Serial Interface Timing Characteristics .................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Descriptions.............................................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 10 System Description......................................................................... 11 Transmit Stage............................................................................. 12 Frequency Sweep Command Sequence................................... 13 Receive Stage ............................................................................... 13 DFT Operation ........................................................................... 13 Impedance Calculation.................................................................. 14 Magnitude Calculation .............................................................. 14 Gain Factor Calculation ............................................................ 14 Impedance Calculation Using Gain Factor............................. 14 Gain Factor Variation with Frequency .................................... 14 Two-Point Calibration ............................................................... 15 Two-Point Gain Factor Calculation ......................................... 15 Gain Factor Setup Configuration............................................. 15 Gain Factor Recalculation......................................................... 15 Gain Factor Temperature Variation......................................... 16 Impedance Error ........................................................................ 16 Performing a Frequency Sweep .................................................... 18 Register Map ................................................................................... 19 Control Register ......................................................................... 19 Start Frequency Register ........................................................... 20 Frequency Increment Register.................................................. 20 Number of Increments Register ............................................... 21 Number of Settling Time Cycles Register ............................... 21 Status Register............................................................................. 22 Real and Imaginary Data Registers (16 Bits).......................... 22 Serial Bus Interface......................................................................... 23 General I2C Timing.................................................................... 23 Writing/Reading to the AD5934 .............................................. 24 Block Write.................................................................................. 24 AD5934 Read Operations ......................................................... 25 Typical Applications....................................................................... 26 Biomedical: Noninvasive Blood impedance Measurement .. 26 Sensor/Complex Impedance Measurement............................ 26 Electro-Impedance Spectroscopy............................................. 27 Choosing a Reference for the AD5934 ........................................ 28 Layout and Configuration............................................................. 29 Power Supply Bypassing and Grounding................................ 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
6/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5934 SPECIFICATIONS
Test conditions unless otherwise stated: VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 k connected between Pin 5 and Pin 6. Feedback resistor = 200 k connected between Pin 4 and Pin 5. PGA gain = x1.
Table 2.
Parameter SYSTEM Impedance Range Total System Accuracy System Impedance Error Drift TRANSMIT STAGE Output Frequency Range 2 Output Frequency Resolution MCLK Frequency TRANSMIT OUTPUT VOLTAGE Range 1 AC Output Excitation Voltage 3 DC Bias 4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 2 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 3 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 4 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT Short-Circuit Current to Ground SYSTEM AC CHARACTERISTICS Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Wide Band (0 MHz to 1 MHz) Narrowband (5 kHz) Min 0.001 0.5 30 1 0.1 16.776 100 Y Version 1 Typ Max 10 Unit M % ppm/C kHz Hz MHz Test Conditions/Comments
<0.1 Hz resolution achievable using DDS techniques. Maximum system clock frequency.
1.98 1.48 200 5.8
V p-p V mA
Refer to Figure 4 for output voltage distribution. DC bias of the AC excitation signal. See Figure 5. TA = 25C. TA = 25C.
0.97 0.76 2.4 0.25
V p-p V k mA
See Figure 6. DC bias of output excitation signal. See Figure 7.
0.383 0.31 1 0.20
V p-p V k mA
See Figure 8. DC bias of output excitation signal. See Figure 9.
0.198 0.173 600 0.15 0.15 60 -52 -56 -85
V p-p V mA mA dB dB dB dB
See Figure 10. DC bias of output excitation signal. See Figure 11.
Rev. 0 | Page 3 of 32
AD5934
Parameter RECEIVE STAGE Input Leakage Current Input Capacitance 5 Feedback Capacitance CFB Min Y Version 1 Typ Max 1 0.01 3 Unit nA fF pF Test Conditions/Comments To VIN pin. Pin capacitance between VOUT and GND. Feedback capacitance around currentto-voltage amplifier; appears in parallel with feedback resistor.
ANALOG-TO-DIGITAL CONVERTER5 Resolution Sampling Rate LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current 6 Input Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode ) IDD (Standby Mode)
12 250 0.7 x VDD 0.3 x VDD 1 7 2.7 10 17 7 9 0.7 1 5.5 15 25
bits kSPS
ADC throughput rate.
A pF V mA mA mA mA A A
TA =25C. TA = 25C.
IDD (Power-Down Mode)
5 8
VDD = 3.3 V. VDD = 5.5 V. VDD = 3.3 V; see the Control Register section. VDD = 5.5 V. VDD = 3.3 V. VDD = 5.5 V.
1 2
Temperature range for Y version = -40C to +125C, typical at 25C. The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934. 3 The peak-to-peak value of the AC output excitation voltage scales with supply voltage according to the formula given below. VDD is the supply voltage. 2 Output Excitation Voltage (V p - p) = x VDD 3.3 4 The DC bias value of the Output excitation voltage scales with supply voltage according to the formula given below. VDD is the supply voltage. 2 Output Excitation Bias Voltage (V) = x VDD 3.3 5 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of currentto-voltage amplifier. 6 The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
Rev. 0 | Page 4 of 32
AD5934 I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. 1
Table 3.
Parameter 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2. 5 0. 6 1. 3 0. 6 100 0. 9 0 0. 6 0. 6 1. 3 300 0 300 0 250 20 + 0.1 CB 4 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus free time between a stop and a start condition tF, rise time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
CB
1 2 3
See Figure 2. Guaranteed by design and characterization, not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) in order to bridge the undefined SCL's falling edge. 4 CB is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START CONDITION
t6
t2
t5
t7
REPEATED START CONDITION
t1
t8
05325-002
STOP CONDITION
Figure 2. I2C Interface Timing Diagram
Rev. 0 | Page 5 of 32
AD5934 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise note
Table 4.
Parameter DVDD to GND AVDD1 to GND AVDD2 to GND SDA/SCL to GND VOUT to GND VIN to GND MCLK to GND Operating Temperature Range Extended Industrial (Y Grade) Storage Temperature Range Maximum Junction Temperature SSOP Package JA Thermal Impedance JC Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating -0.3 V to + 7. 0 V -0.3 V to + 7. 0 V -0.3 V to + 7. 0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +160C 150C 139C/W 136C/W 260C 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 32
AD5934 PIN CONFIGURATION AND DESCRIPTIONS
NC 1 NC 2 NC 3 RFB 4 VIN 5 VOUT 6 NC 7 MCLK 8 NC = NO CONNECT
16 SCL 15 SDA
AD5934
TOP VIEW (Not to Scale)
14 AGND2 13 AGND1 12 DGND 11 AVDD2 10 AVDD1 9
05325-003
DVDD
Figure 3. Pin Configuration
It is recommended to tie all supply connections (Pin 9, Pin 10, and Pin 11) and run from a single supply between 2.7 V and 5.5 V. It is also recommended to connect all ground signals together (Pin 12, Pin 13, and Pin 14).
Table 5. Pin Function Descriptions
Pin No. 1, 2, 3, 7 4 5 6 8 9 10 11 12 13 14 15 16 Mnemonic NC RFB VIN VOUT MCLK DVDD AVDD1 AVDD2 DGND AGND1 AGND2 SDA SCL Description/comment No Connect. External Feedback Resistor. Connected from Pin 4 to Pin 5 and used to set the gain of the current-to-voltage amplifier on the receive side. Input to Receive Transimpedance Amplifier. Presents a virtual earth voltage of VDD/2. Excitation Voltage Signal Output. Master Clock for the System. Supplied by user. Digital Supply Voltage. Analog Supply Voltage 1. Analog Supply Voltage 2. Digital Ground. Analog Ground 1. Analog Ground 2. I2C Data Input. I2C Clock Input.
Rev. 0 | Page 7 of 32
AD5934 TYPICAL PERFORMANCE CHARACTERISTICS
35 MEAN = 1.9824 SIGMA = 0.0072 30
30 MEAN = 0.7543 SIGMA = 0.0099 25
NUMBER OF DEVICES
NUMBER OF DEVICES
25 20
20
15
15
10
10
05325-064
0 1.92
1.94
1.96
1.98
2.00
2.02
2.04
2.06
0 0.68
0.70
0.72
0.74
0.76
0.78
0.80
0.82
0.84
0.86
VOLTAGE (V)
VOLTAGE (V)
Figure 4. Range 1: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 7. Range 2: DC Bias Distribution VDD = 3.3 V
30
30 MEAN = 1.4807 SIGMA = 0.0252 25
MEAN = 0.3827 SIGMA = 0.00167 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20
20
15
15
10
10
5
05325-072
5
05325-077
0 1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
0 0.370
0.375
0.380
0.385 VOLTAGE (V)
0.390
0.395
0.400
VOLTAGE (V)
Figure 5. Range 1: DC Bias Distribution VDD = 3.3 V
30 MEAN = 0.9862 SIGMA = 0.0041 25
Figure 8. Range 3: Output Excitation Voltage Distribution VDD = 3.3 V
30 MEAN = 0.3092 SIGMA = 0.0014 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20
20
15
15
10
10
5
05325-066
5
05325-074
0 0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
0 0.290
0.295
0.300
0.305 VOLTAGE (V)
0.310
0.315
0.320
VOLTAGE (V)
Figure 6. Range 2: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 9. Range 3: DC Bias Distribution VDD = 3.3 V
Rev. 0 | Page 8 of 32
05325-073
5
5
AD5934
30 MEAN = 0.1982 SIGMA = 0.0008 25
15.8 15.3 14.8 14.3
IDD (mA)
AVDD1, AVDD2, DVDD CONNECTED TOGETHER. OUTPUT EXCITATION FREQUENCY = 30kHz RFB, ZCALIBRATION = 100k
NUMBER OF DEVICES
20
13.8 13.3 12.8 12.3 11.8
15
10
5
05325-070
11.3 10.8 0 2 4 6 8 10 12 14 16 18 MCLK FREQUENCY (MHz)
0 0.192
0.194
0.196
0.198
0.200
0.202
0.204
0.206
VOLTAGE (V)
Figure 10. Range 4: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 12. Typical Supply Current vs. AD5934 Clock Frequency
0.4
30 MEAN = 0.1792 SIGMA = 0.0024 25
0.2
PHASE ERROR (Degrees)
VDD = 3.3V TA = 25C f = 32kHz
NUMBER OF DEVICES
0
20
-0.2
15
-0.4
10
-0.6
5
05325-075
0 0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205 VOLTAGE (V)
-1.0 0 50 100 150 200 250 300 350 PHASE (Degrees)
400
Figure 11. Range 4: DC Bias Distribution VDD = 3.3 V
Figure 13. Typical AD5934 Phase Error
Rev. 0 | Page 9 of 32
05325-028
-0.8
05325-088
AD5934 TERMINOLOGY
Total System Accuracy The AD5934 can accurately measure a range of impedance values to less than 0.5% of the correct impedance value for supply voltages between 2.7 V to 5.5 V. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The spurious-free dynamic range refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 200 kHz, about the fundamental frequency. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental, where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. For the AD5934, THD is defined as
THD (db) = 20 log
V2 2 + V3 2 + V4 2 + V5 2 + V 2 6 V1
Rev. 0 | Page 10 of 32
AD5934 SYSTEM DESCRIPTION
MCLK
DDS CORE (27 BITS) COS SCL MICROCONTROLLER SDA I2C INTERFACE SIN
DAC ROUT VOUT
Z()
AD5934
REAL REGISTER IMAGINARY REGISTER RFB MAC CORE (1024 DFT) WINDOWING OF DATA MCLK ADC (12 BITS) PROGRAMMABLE GAIN AMPLIFIER VIN LPF X5 X1 VDD/2
05325-078
Figure 14. AD5934 Block Overview
The AD5934 is a high precision impedance converter system solution which combines an on-board frequency generator with a 12-bit, 250 kSPS ADC. The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and DFT processed by an on-board DSP engine. The DFT algorithm returns both a real (R) and imaginary (I) data-word at each frequency point along the sweep. The impedance magnitude and phase is easily calculated using the following equations:
Magnitude =
-1
The AD5934 permits the user to perform a frequency sweep with a user-defined start frequency, frequency resolution, and number of points in the sweep. In addition, the device allows the user to program the peak-to-peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the VOUT and VIN pins. Table 6 gives the four possible output peak-to-peak voltages and the corresponding dc bias levels for each range.
Table 6.
Output Excitation Voltage Amplitude Range 1: 1.98 V p-p Range 2: 0.99 V p-p Range 3: 383 mV p-p Range 4: 198 mV p-p Output DC Bias Level 1.48 V 0.74V 0.31 V 0.179 V
R2 + I 2
Phase = Tan ( I / R)
To characterize an impedance profile Z(), generally a frequency sweep is required like that shown in Figure 15.
The excitation signal for the transmit stage is provided on-chip using DDS techniques which permit subhertz resolution. The receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. The clock for the DDS is generated from an external reference clock which is provided by the user at MCLK.
IMPEDANCE
FREQUENCY
Figure 15.
05325-033
Rev. 0 | Page 11 of 32
AD5934
TRANSMIT STAGE
As shown in Figure 16, the transmit stage of the AD5934 is made up of a 27-bit phase accumulator DDS core which provides the output excitation signal at a particular frequency. The input to the phase accumulator is taken from the contents of the START FREQUENCY register (see RAM Locations 82h, 83h, and 84h). Although the phase accumulator offers 27 bits of resolution, the START FREQUENCY register has the 3 most significant bits (MSBs) set to 0 internally; therefore the user has the ability to program only the lower 24 bits of the START FREQUENCY register. The AD5934 offers a frequency resolution programmable by the user down to 0.1 Hz. The frequency resolution is programmed via a 24-bit word loaded serially over the I2C interface to the FREQUENCY INCREMENT register. The frequency sweep is fully described by the programming of three parameters: the START FREQUENCY, the FREQUENCY INCREMENT, and the NUMBER OF INCREMENTS. Equation 2, based on the master clock frequency and the required increment frequency output from the DDS.
(2) Required Frequency Increment x 227 Frequency Increment Code = MCLK 16
For example, if the user requires the sweep to have a resolution of 10 Hz and has a 16 MHz clock signal connected to MCLK, the code that needs to be programmed is given by
10 Hz 00053E hexidecimal Frequency Increment Code = 16 MHz 16
The user programs 00 hex to Register 85 h, 05 hex to Register 86 h, and finally 3E hex to Register 87 h.
START FREQUENCY
This is a 24-bit word that is programmed to the on-board RAM at Address 82h, Address 83h, and Address 84h (see the Register Map section). The required code loaded to the START FREQUENCY register is the result of the formula shown in Equation 1, based on the master clock frequency and the required start frequency output from the DDS.
(1) Required Output Start Frequency x 227 Start Frequency Code = MCLK 16
NUMBER OF INCREMENTS
This is a 9-bit word that represents the number of frequency points in the sweep. The number is programmed to the on-board RAM at Address 88 h and Address 89 h (see the Register Map section). The maximum number of points that can be programmed is 511. For example, if the sweep needs 150 points, the user programs 00 hex to Register 88 h and 96 hex to Register 89 h. Once the three parameter values have been programmed, the sweep is initiated by issuing a Start Frequency Sweep command to the CONTROL register at Address 80 h and Address 81 h (see the Register Map section). Bit 2 in the STATUS register (Register 8F h) indicates the completion of the frequency measurement for each sweep point. Incrementing to the next frequency sweep point is under the control of the user. The measured result is stored in two registers (94 h, 95 h and 96 h, 97 h) which should be read before issuing an Increment Frequency command to the CONTROL register to move to the next sweep point. There is the facility to repeat the current frequency point measurement by issuing a Repeat Frequency command to the CONTROL register. This has the benefit of allowing the user to average successive readings. When the frequency sweep has completed all frequency points, Bit 3 in the STATUS register is set, indicating completion of the sweep. Once this bit is set further increments are disabled.
For example, if the user requires the sweep to begin at 30 kHz and has a 16 MHz clock signal connected to MCLK. The code that needs to be programmed is given by
30 kHz x 227 3D70A3 hexidecimal Start Frequency Code = 16 MHz 16
The user programs 3D hex to Register 82 h, 70 hex to Register 83 h, and A3 hex to Register 84 h.
FREQUENCY INCREMENT
This is a 24-bit word that is programmed to the on-board RAM at Address 85 h, Address 86 h, and Address 87 h (see the Register Map section). The required code loaded to the frequency increment register is the result of the formula shown in
Rev. 0 | Page 12 of 32
AD5934
FREQUENCY SWEEP COMMAND SEQUENCE
The following sequence must be followed to implement a frequency sweep. 1. Enter standby mode. Prior to issuing a Start Frequency Sweep command, the device must be placed in a standby mode by issuing an Enter Standby Mode command to the CONTROL register (Register 80 h). In this mode, the VOUT and VIN pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and ground. Enter initialize mode. In general, high Q complex circuits require a long time to reach steady state. To facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start frequency sweep mode where the impedance measurement takes place. An Initialize with Start Frequency Command to the CONTROL register enters initialize mode. In this mode the impedance is excited with the programmed start frequency but no measurement takes place. The user times out the required settling time before issuing a Start Frequency Sweep command to the CONTROL register to enter the start frequency sweep mode. 3. Enter start frequency sweep mode. The user enters this mode by issuing a Start Frequency Sweep command to the control register. In this mode, the ADC starts measuring after the programmed Number of Settling Time Cycles has elapsed. The user can program an integer number of output frequency cycles (settling time cycles) to Register 8A h and Register 8B h before beginning the measurement at each frequency point (see Figure 28).
RECEIVE STAGE
The receive stage comprises a current-to-voltage amplifier, followed by a programmable gain amplifier (PGA), antialiasing filter, and ADC. The receive stage schematic is shown in Figure 17. The unknown impedance is connected between the VOUT and VIN pins. The first stage current-to-voltage amplifier configuration means that a voltage present at the VIN pin is a virtual ground with a dc value set at VDD/2. The signal current that is developed across the unknown impedance flows into the VIN pin and develops a voltage signal at the output of the currentto-voltage converter. The gain of the current-to voltage amplifier is determined by a user-selectable feedback resistor connected between Pins 4 (RFB) and Pin 5 (VIN). It is important for the user to choose a feedback resistance value which, in conjunction with the selected gain of the PGA stage, maintains the signal within the linear range of the ADC (0 V to VDD). The PGA allows the user to gain the output of the current-tovoltage amplifier by a factor of 5 or 1 depending upon the status of Bit D8 in the CONTROL register (see the Register Map section Register 81h). The signal is then low-pass filtered and presented to the input of the 12-bit, 250 kSPS ADC.
R C RFB 5xR R VIN VDD/2 LPF R
05325-038
2.
ADC
Figure 17. AD5934 Receive Stage
The digital data from the ADC is passed directly to the DSP core of the AD5934 which performs a DFT on the sampled data.
The DDS output signal is passed through a programmable gain stage in order to generate the four ranges of peak-to-peak output excitation signals listed in Table 6. The peak-to-peak output excitation voltage is selected by setting Bit D10 and Bit D9 in the CONTROL register--see the Control Register section-- and is made available at the VOUT pin.
R(GAIN) PHASE ACCUMULATOR (27 BITS)
DFT OPERATION
A DFT is calculated for each frequency point in the sweep. The AD5934 DFT algorithm is represented by
X( f ) =
1023 n=0
(x(n)(cos(n) - j sin(n)))
DAC VOUT VBIAS
05325-034
where X(f) is the power in the signal at the frequency point f, x(n) is the ADC output, with the cos(n) and sin(n) the sampled test vectors provided by the DDS core at the frequency f. The multiplication is accumulated over 1024 samples for each frequency point. The result is stored in two, 16-bit registers representing the real and imaginary components of the result. The data is stored in twos complement format.
Figure 16. AD5934 Transmit Stage
Rev. 0 | Page 13 of 32
AD5934 IMPEDANCE CALCULATION
MAGNITUDE CALCULATION
The first step in impedance calculation for each frequency point is to calculate the magnitude of the DFT at that point. The DFT magnitude is given by Magnitude = R2 + I 2
IMPEDANCE CALCULATION USING GAIN FACTOR
The next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. For this example, assume that the unknown impedance = 510 k. After measuring the unknown impedance at a frequency of 30 kHz, assume that the real and imaginary registers contain the following data: Real register: = 0AEB hex = -1473 decimal Imaginary register: = 0DB3 hex = 3507 decimal Magnitude = ((-1473)2 + (3507)2 ) = 3802.863
Then the measured impedance at the frequency point is given by 1 Impedance = GAIN FACTOR x Magnitude 1 = 515.819273 E - 12 x 3802.863
where R is the real number stored at Register Address 94 h and Register Address 95 h and I is the imaginary number stored at Register Address 96 h and Register Address 97 h. For example, assume the results in the real and imaginary registers are as follows at a frequency point: Real register: = 038B hex = 907 decimal Imaginary register: = 0204 hex = 516 decimal
Magnitude = (9072 + 5162 ) = 1043.506
To convert this number into an impedance, it must be multiplied by a scaling factor called the gain factor. The gain factor is calculated during the calibration of the system with a known impedance connected between the VOUT and VIN pins. Once the gain factor has been calculated, it can be used in the calculation of any unknown impedance between the VOUT and VIN pins.
= 509.791 k
GAIN FACTOR VARIATION WITH FREQUENCY
Because the AD5934 has a finite frequency response, the gain factor also shows a variation with frequency. This results in an error in the impedance calculation over a frequency range. Figure 18 shows an impedance profile based on a single-point gain factor calculation. To minimize this error, the frequency sweep should be limited to as small a frequency range as possible.
101.5 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25C MEASURED CALIBRATION IMPEDANCE = 100k
GAIN FACTOR CALCULATION
An example of a gain factor calculation follows, with these assumptions: Output excitation voltage = 2 V (p-p) Calibration impedance value, ZCALIBRATION = 200 k PGA gain = x1 Current to voltage amplifier gain resistor = 200 k Calibration frequency = 30 kHz Then typical contents of the real and imaginary register after a frequency point conversion would be Real register: = F9C hex = -3996 decimal Imaginary register: = 227E hex = 8830 decimal
Magnitude = (-39962 + (8830)2 = 9692.106
1 ADMITTANCE Impedance GAIN FACTOR = = Magnitude Code 1 200 k GAIN FACTOR = = 515 .819 E - 12 9692 .106
101.0
IMPEDANCE (k)
100.5
100.0
99.5
99.0
05325-085
98.5 54
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 18. Impedance Profile Using a Single-Point Gain Factor Calculation
Rev. 0 | Page 14 of 32
AD5934
TWO-POINT CALIBRATION
Alternatively it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a 2-point calibration. Figure 19 shows an impedance profile based on a 2-point GAIN FACTOR calculation.
101.5 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25C MEASURED CALIBRATION IMPEDANCE = 100k
GAIN FACTOR SETUP CONFIGURATION
When calculating the GAIN FACTOR, it is important that the receive stage is operating in its linear region. This requires careful selection of the excitation signal range, current-to-voltage gain resistor and PGA gain. The gain through the system shown in Figure 20 is given by
101.0
Output Excitation Voltage Range x
Gain Setting Resistor x PGA Gain ZUNKNOWN
IMPEDANCE (k)
100.5
100.0
CURRENT TO VOLTAGE GAIN SETTING RESISTOR RFB
99.5
VOUT
99.0
05325-086
ZUNKNOWN LPF
05325-089
VIN VDD PGA (X1 OR X5)
ADC
98.5 54
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 20. AD5934 System Voltage Gain
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation
TWO-POINT GAIN FACTOR CALCULATION
This is an example of a 2-point GAIN FACTOR calculation assuming the following: Output excitation voltage = 2 V (p-p) Calibration impedance value, ZUNKNOWN = 100.0 k PGA gain = x1 Supply voltage = 3.3 V Current to voltage amplifier gain resistor = 100 k Calibration frequencies at = 55 kHz and 65 kHz Typical values of the GAIN FACTOR calculated at the two calibration frequencies read Gain factor calculated at 55 kHz = 1.031224E-09 Gain factor calculated at 65 kHz = 1.035682E-09 Difference in gain factor (GF) = 1.035682E-09 - 1.031224E-09 = 4.458000E-12 Frequency span of sweep (F) = 10 kHz Therefore the GAIN FACTOR required at 60 kHz is given by
For this example, assume the following system settings: VDD = 3.3 V Gain setting resistor = 200 k ZUNKNOWN = 200 k PGA setting = x1 The peak-to-peak voltage presented to the ADC input is 2 V p-p. However had the user chosen a PGA gain of x5, the voltage would saturate the ADC.
GAIN FACTOR RECALCULATION
The GAIN FACTOR must be recalculated for a change in any of the following parameters: * * * Current-to-voltage gain setting resistor Output excitation voltage PGA gain
4.458000E - 12 x 5 kHz + 1.031224E - 09 10 kHz Required gain factor = 1.033453E-9 The impedance is calculated as previously described in the Impedance Calculation section.
Rev. 0 | Page 15 of 32
AD5934
GAIN FACTOR TEMPERATURE VARIATION
The typical impedance error variation with temperature is in the order of 30 ppm/C. Figure 21 shows an impedance profile with a variation in temperature for 100 k impedance using a 2-point gain factor calibration.
101.5
Range 2 (1 k to 10 k)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 1 k PGA gain = x1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 1 k
2.0 RFB = 1k CALIBRATION IMPEDANCE = 1k TA = 25C 5k 10k
101.0
+125C
IMPEDANCE (k)
100.5 +25C 100.0 -40C 99.5
% IMPEDANCE ERROR
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
99.0
98.5 54
56
58
60
62
64
66
05325-087
VDD = 3.3V CALIBRATION FREQUENCY = 60kHz MEASURED CALIBRATION IMPEDANCE = 100k
FREQUENCY (kHz)
Figure 21. Impedance Profile Variation with Temperature Using a 2-Point Gain Factor Calculation
10
35
60
100
FREQUENCY (kHz)
IMPEDANCE ERROR
Minimizing the impedance range under test optimizes the AD5934 measurement performance. Below are examples of the AD5934 performance when operating in the six different impedance ranges. The gain factor is calculated with a precision resistor in each case.
Figure 23. Range 2: Typical % Impedance Error over Frequency
Range 3 (10 k to 100 k)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 10 k PGA gain = x1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 10 k
0.3 RFB = 10k CALIBRATION IMPEDANCE = 10k TA = 25C
Range 1 (0.1 k to 1 k)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 100 PGA gain = x1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 100
7 RFB = 0.1k CALIBRATION IMPEDANCE = 0.1k TA = 25C
0.2
50k 100k
% IMPEDANCE ERROR
0.1
0
6
-0.1
% IMPEDANCE ERROR
5 0.5k 1k
3
-0.3 10 35 60 100 FREQUENCY (kHz)
2 1 0 10 35 60 100 FREQUENCY (kHz)
Figure 24. Range 3: Typical % Impedance Error over Frequency
05325-079
Figure 22. Range 1: Typical % Impedance Error over Frequency
Rev. 0 | Page 16 of 32
05325-081
4
-0.2
05325-080
AD5934
Range 4 (100 k to 1 M)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 100 k PGA gain = x1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 100 k
1.0 0.5 0 500k 1M
Range 6 (9 M to 10 M)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 9 M PGA gain = x1 Supply voltage = 3.3 V Current to voltage amplifier gain resistor = 9 M
4 RFB = 10M CALIBRATION IMPEDANCE = 10M TA = 25C
2
% IMPEDANCE ERROR
% IMPEDANCE ERROR
0
-0.5 -1.0 -1.5 -2.0 -2.5
05325-082
-2 9.5M 10M
-4
-6 -8 -10 10 35 60 100 FREQUENCY (kHz)
-3.0 -3.5
10
35
60
100
FREQUENCY (kHz)
Figure 25. Range 4: Typical % Impedance Error over Frequency
Figure 27. Range 6: Typical % Impedance Error over Frequency
Range 5 (1 M to 2 M)
Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 100 k PGA gain = x1 Supply voltage = 3.3 V Current to voltage amplifier gain resistor = 100 k
3 RFB = 1M CALIBRATION IMPEDANCE = 1M TA = 25C
1
% IMPEDANCE ERROR
-1
-3
-5 1.5M 2M
-7
-9 10 35 60 100 FREQUENCY (kHz)
Figure 26. Range 5: Typical % Impedance Error over Frequency
Rev. 0 | Page 17 of 32
05325-083
05325-084
RFB = 100k CALIBRATION IMPEDANCE = 100k TA = 25C
AD5934 PERFORMING A FREQUENCY SWEEP
PROGRAM FREQUENCY SWEEP PARAMETERS INTO RELEVANT REGISTERS (1) START FREQUENCY REGISTER (2) NUMBER OF INCREMENTS REGISTER (3) FREQUENCY INCREMENT REGISTER
PLACE THE AD5934 INTO STANDBY MODE. RESET: BY ISSUING A RESET COMMAND TO CONTROL REGISTER THE DEVICE IS PLACED IN STANDBY MODE. PROGRAM INITIALIZE WITH START FREQUENCY COMMAND TO THE CONTROL REGISTER.
PROGRAM START FREQUENCY SWEEP COMMAND IN THE CONTROL REGISTER, AFTER A SUFFICIENT AMOUNT OF SETTLING TIME HAS ELAPSED.
POLL STATUS REGISTER TO CHECK IF THE DFT CONVERSION IS COMPLETE. N Y PROGRAM THE INCREMENT FREQUENCY OR THE REPEAT FREQUENCY COMMAND TO THE CONTROL REGISTER.
READ VALUES FROM REAL AND IMAGINARY DATA REGISTER.
Y
POLL STATUS REGISTER TO CHECK IF FREQUENCY SWEEP IS COMPLETE.
N
Y
05325-047
PROGRAM THE AD5934 INTO POWER-DOWN MODE.
Figure 28. Frequency Sweep Flow Chart
Rev. 0 | Page 18 of 32
AD5934 REGISTER MAP
Table 7.
Register Name CONTROL START FREQUENCY Register Address 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8A h 8B h 8F h 94 h 95 h 96 h 97 h Register Data D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read/Write Register Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only Read Only Read Only Read Only
FREQUENCY INCREMENT
NUMBER OF INCREMENTS NUMBER OF SETTLING TIME CYCLES STATUS REAL DATA IMAGINARY DATA
CONTROL REGISTER
Table 8. 16-Bit Register
80 h 81 h D15 to D8 D7 to D0 Read or Write Read or Write
Table 9. Control Register Map
Bit D15 0 0 0 0 0 1 1 1 1 1 1 D11 D10 0 0 1 1 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev. 0 | Page 19 of 32
The CONTROL register is a 16-bit register that sets the AD5934 control modes. The 4 MSBs of the CONTROL register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and various other control functions defined in the CONTROL register map. The user may choose to write only to Register Location 80 h and not to alter the contents of 81 h. Note that the CONTROL register should not be written to as part of a Block Write command. The CONTROL register also allows the user to program the excitation voltage and set the system clock. A Reset command to the CONTROL register does not reset any programmed values associated with the sweep (that is, Start frequency, number of increments, frequency increment). After a Reset command, an Initialize with Start Frequency command must be issued to the CONTROL register to restart the frequency sweep sequence (see Figure 28). Default value upon reset: D15 to D0 reset to A0 00H upon power-up. The AD5934 contains a 16-bit control register (Address 80h and 81h) that sets the AD5934 control modes.
D14 0 0 0 0 1 0 0 0 0 1 1
D13 0 0 1 1 0 0 0 1 1 0 0 D9 0 1 0 1
D12 0 1 0 1 0 0 1 0 1 0 1
1 0
No operation Initialize with Start Frequency Start Frequency Sweep Increment Frequency Repeat Frequency No operation No operation Power down mode Standby mode No operation No operation No operation Output voltage range Range 1 ( 2.0 V p-p typ) Range 3 (200 mV p-p typ) Range 4 (400 mV p-p typ) Range 2 (1.0 V p-p typ) PGA gain 0 = x5, 1 = x1 Reserved. Set to 0. Reserved. Set to 0. Reserved. Set to 0. Reset External System clock. Must be set to 1. Must be Set to 0. Reserved. Set to 0. Reserved. Set to 0.
AD5934
CONTROL Register Decode
Initialize with Start Frequency This command enables the DDS to output the programmed start frequency for an indefinite time. It is used is to excite the unknown impedance initially. When the output unknown impedance has settled after a time determined by the user, the user must initiate a Start Frequency Sweep command to begin the frequency sweep. Start Frequency Sweep In this mode the ADC starts measuring after the programmed number of settling time cycles has elapsed. The user has the ability to program an integer number of output frequency cycles (settling time cycles) to Register 8A h and Register 8B h before the commencement of the measurement at each frequency point. See Figure 28. Increment Frequency The Increment Frequency command is used to step to the next frequency point in the sweep. This usually happens after data from the previous step has been transferred and verified by the DSP. When the AD5934 receives this command, it waits for the programmed number of settling time cycles before beginning the ADC conversion process. Repeat Frequency There is the facility to repeat the current frequency point measurement by issuing a Repeat Frequency command to the CONTROL register. This has the benefit of allowing the user to average successive readings. Power-Down The default state on power-up of the AD5934 is power-down mode. The CONTROL register contains the code 1010000000000000 (A000h). In this mode both the output and input VOUT and VIN pins are connected internally to GND. Standby Mode Powers up the part for general operation; in standby mode the VIN and VOUT pins are internally connected to ground. Reset A Reset command allows the user to interrupt a sweep. The START FREQUENCY, NUMBER OF INCREMENTS, and FREQUENCY INCREMENT register contents are not overwritten. An Initialize with Start Frequency command is required to restart the Frequency Sweep command sequence. Output Voltage Range This allows the user to program the excitation voltage range at VOUT. PGA Gain This allows the user to amplify the response signal into the ADC by a multiplication factor of x5 or x1.
START FREQUENCY REGISTER
Table 10. 24-Bit Register
82 h 83 h 84 h D23 to D16 D15 to D8 D7 to D0 Read or Write Read or Write Read or Write
The START FREQUENCY register contains the 24-bit digital representation of the frequency from where the subsequent frequency sweep is initiated. For example, if the user requires the sweep to start from frequency 30 kHz (using a 16.00 MHz clock), then the user programs 3D hex to Register Location 82 h, 70 hex to Register Location 83h, and A3 hex to Register Location 84 h. This ensures the output frequency starts at 30 kHz. The code to be programmed to the START FREQUENCY register is 30 kHz x 227 3D70A3 hexidecimal Start Frequency Code = 16 MHz 16 Default value upon reset: D23 to D0 are not reset on power-up. After a Reset command the contents of this register are not reset.
FREQUENCY INCREMENT REGISTER
Table 11.
85 h 86 h 87 h D23 to D16 D15 to D8 D7 to D0 Read or Write Read or Write Read or Write
The FREQUENCY INCREMENT register contains a 24-bit representation of the frequency increment between consecutive frequency points along the sweep. For example, if the user requires an increment step of 30 Hz using a 16.0 MHz clock, the user should program 00 hex to Register Location 85 h, 0F hex to Register Location 86 h and BA hex to Register Location 87 h. The formula for calculating the increment frequency is given by 10 Hz x 227 00053E hexidecimal Frequency Increment Code = 16 MHz 16 The user programs 00 hex to Register 85 h, 05 hex to Register 86 h, and 3E hex to Register 87 h. Default value upon reset: D23 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
Rev. 0 | Page 20 of 32
AD5934
NUMBER OF INCREMENTS REGISTER
Table 12. 16-Bit Register
Bits D15 to D9 = Don't care Bits D8 to D0 = Number of frequency increments 88 h 89 h D15 to D8 D7 to D0 Read or Write Read or Write Integer number stored in binary format
This register determines the number of frequency points in the frequency sweep. The number of points is represented by a 9-bit word, D8 to D0. D9 to D15 are don't care bits. This register in conjunction with the START FREQUENCY register and the INCREMENT FREQUENCY registers determine the frequency sweep range for the sweep operation. The maximum number of increments which can be programmed is 511. Default value upon reset: D8 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
NUMBER OF SETTLING TIME CYCLES REGISTER
Table 13. 16-Bit Register
D15 to D11 = Don't Care D10 to D9 = 2-Bit Decode D8 = MSB Number of Settling Time Cycles D10 D9 0 0 Default 0 1 Number Cycles x 2 1 0 Reserved 1 1 Number Cycles x 4 Number of Settling Time Cycles 8A h D15 to D8 Read or Write
Integer number stored in binary format
8B h
D7 to D0
Read or Write
This register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after receipt of a Start, Increment, or Repeat Frequency command, before the ADC is triggered to perform a conversion of the response signal. The SETTLING TIME CYCLES register value determines the delay between a Frequency Start/Increment/Repeat command and the time an ADC conversion commences. The number of cycles is represented by a 9-bit word, D8 to D0. The value programmed into the SETTLING TIME CYCLES register can be increased by a factor of 2 or 4 depending upon the status of bits D10 to D9. The 5 most significant bits, D15 to D11, are don't care bits. The maximum number of output cycles that can be programmed is 511 x 4 = 2044 cycles. For example, consider an excitation signal of 30 kHz. The maximum delay between the programming of this frequency and the time that this signal is first sampled by the ADC is 511 x 4 x 33.33 s = 68.126 ms. The ADC takes 1024 samples, and the result is stored as real and imaginary data in Register 94 h to Register 97 h. The conversion process takes approximately 1 ms using a 16.777 MHz clock. Default value upon reset: D10 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
Rev. 0 | Page 21 of 32
AD5934
STATUS REGISTER
Table 14. 8-Bit Register
8F h D7 to D0 Read Only Bits
Valid Real/Imaginary Data
Set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. Reset when a DDS Start/Increment/Repeat command is issued. Also this bit is reset to 0 when a Reset command is issued to the CONTROL register.
The STATUS register is used to confirm that particular measurement tests have been successfully completed. Each of the bits from D7 to D0 indicates the status of specific functionality of the AD5934. D0, and Bit D4 to Bit D7 are treated as don't care bits, these bits do not indicate the status of any measurement The status of bit D1 indicates the status of a frequency point impedance measurement. This bit is set when the AD5934 has completed the current frequency point impedance measurement. This indicates that there is valid real and imaginary data in Register 93 h to Register 97 h. This bit is reset on receipt of a Start, Increment, Repeat Frequency, or Reset command. This bit is also reset on power-up. The status of bit D2 indicates the status of the programmed frequency sweep. This bit is set when all programmed increments to the NUMBER of INCREMENTS register are complete. This bit is reset on power-up and on receipt of a Reset command.
Table 15. STATUS Register
STATUS Register Address 8F h 8F h 8F h 8F h 8F h 8F h 8F h 8F h Control Word 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Function Reserved Valid real/imaginary data Frequency sweep complete Reserved Reserved Reserved Reserved Reserved
Frequency Sweep Complete
Set when data processing for the last frequency point in the sweep is complete. Reset when a Start Frequency Sweep command is issued to the CONTROL register. This bit is also reset when a Reset command is issued to the CONTROL register.
REAL AND IMAGINARY DATA REGISTERS (16 BITS)
Table 16. Real Data
94 h 95 h D15 to D8 D7 to D0 Read Only Read Only Twos complement data
Table 17. Imaginary Data
96 h 97 h D15 to D8 D7 to D0 Read Only Read Only Twos complement data
These registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. The values are stored in 16-bit, twos complement format. To convert this number to an actual impedance value, the magnitude-- (Real 2 and Imaginary 2 ) -- must be multiplied by an admittance/code number (called a gain factor) to give the admittance, and the result inverted to give impedance. The gain factor varies for each ac excitation voltage/gain combination. Default value upon reset: These registers are not reset on power-up or on receipt of a Reset command. Note that the data in these registers is only valid if Bit D1 in the STATUS register is set, indicating that the processing at the current frequency point is complete.
Rev. 0 | Page 22 of 32
AD5934 SERIAL BUS INTERFACE
Control of the AD5934 is carried out via the 12C-compliant serial interface protocol. The AD5934 is connected to this bus as a slave device under the control of a master device. The AD5934 has a 7-bit serial bus slave address. When the device is powered up, it has a default serial bus address, 0001101 (0D hex) Data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge (NACK). The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
GENERAL I2C TIMING
The general I2C protocol operates as described in this section. Figure 29 shows the timing diagram for general read and write operations using the I2C-compliant interface. The master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that a data stream follows. The slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit, which determines the direction of the data transfer--that is, whether data is written to or read from the slave device (0 = write, 1 = read). The slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, then the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device.
SCL
SDA START COND BY MASTER
0
0
0
1
1
0
1
R/W ACK. BY AD5934
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY MASTER/SLAVE
05325-048
SLAVE ADDRESS BYTE
REGISTER ADDRESS
Figure 29.
Rev. 0 | Page 23 of 32
AD5934
WRITING/READING TO THE AD5934
The interface specification defines several different protocols for different types of read and write operations. This section describes the protocols used in the AD5934. The figures in this section use the following abbreviations: S P R W A A Start Stop Read Write Acknowledge No acknowledge write byte/command byte In the AD5934, the write byte protocol is also used to set a pointer to a register location. This is used for a subsequent single-byte read from the same address or block read or write starting at that address. To set a register pointer, the following sequence is applied: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a pointer command code (see Table 18, a pointer command = 1011 0000). The slave asserts ACK on SDA. The master sends a data byte (a register location where pointer is to point). The slave asserts ACK on SDA. The master asserts a stop condition on SDA to end the transaction.
SLAVE ADDRESS W A POINTER COMMAND 1011 0000 A REGISTER LOCATION TO POINT TO A P
05325-050
05325-051
User Command Codes
The command codes in Table 18 are used for reading/writing to the interface. They are further explained in this section, but are grouped here for easy reference.
Table 18.
Command Code 1010 0000 Code Name Block Write Block Read Address Pointer Code Description This command is used when writing multiple bytes to the RAM. See the Block Write section. This command is used when reading multiple bytes from RAM/memory. See the Block Read section. This command enables the user to set the address pointer to any location in the memory. The data contains the address of the register where the pointer should be pointing.
1010 0001
S
1011 0000
Figure 31. Setting Pointer to Register Address
BLOCK WRITE
In this operation, the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the AD5934 this is done by setting a pointer to set the register address. 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. The slave asserts ACK on SDA. The master sends a data byte that tells the slave device the number of data bytes to be sent to it. The slave asserts ACK on SDA. The master sends the data bytes. The slave asserts ACK on SDA after each data byte.
Write Byte/Command Byte
In this operation the master device sends a byte of data to the slave device. The write byte can either be a data byte write to a RAM location or can be a command operation. To write data to a register the command sequence is as follows: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a register address. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master asserts a stop condition on SDA to end the transaction.
05325-049
10. The master asserts a stop condition on SDA to end the transaction.
S SLAVE ADDRESS W A BLOCK WRITE A NUMBER BYTES WRITE A BYTE 0 A BYTE 1 A BYTE 2 A P
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
REGISTER DATA
A
P
Figure 32. Writing a Block Write
Figure 30. Writing Register Data to Register Address
Rev. 0 | Page 24 of 32
AD5934
AD5934 READ OPERATIONS
The AD5934 uses the following I2C read protocols:
Block Read
In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set by setting a pointer. 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code (1010 0001) that tells the slave device to expect a block read. The slave asserts ACK on SDA. The master sends a byte count data byte that tells the slave how many data bytes to expect. The slave asserts ACK on SDA. The master asserts a repeat start condition on SDA. This is required to set the read bit high. The master sends the 7-bit slave address followed by the read bit (high).
Receive Byte
In the AD5934, the receive byte protocol is used to read a single byte of data from a register location whose address has previously been set by setting the address pointer. In this operation, the master device receives a single byte from a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NACK on SDA (slave needs to check that master has received data). The master asserts a stop condition on SDA and the transaction ends.
S SLAVE ADDRESS R A REGISTER DATA
05325-052
A
P
10. The slave asserts ACK on SDA. 11. The master receives the data bytes. 12. The master asserts ACK on SDA after each data byte. 13. A NACK is generated after the last byte to signal the end of the read. 14. The master asserts a stop condition on SDA to end the transaction.
S SLAVE ADDRESS W A BLOCK READ A NUMBER BYTES READ A S
Figure 33. Reading Register Data
SLAVE ADDRESS
R
A
BYTE 0
A
BYTE 1
A
BYTE 2
A
P
Figure 34. Performing a Block Read
Rev. 0 | Page 25 of 32
05325-053
AD5934 TYPICAL APPLICATIONS
This section describes typical applications for the AD5934.
BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE MEASUREMENT
When a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby the impedance of the blood under certain conditions changes. By characterizing this effect across different frequencies it is possible to detect a specific strain of virus. For example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another, therefore the requirement to sweep different frequencies to check for different viruses. The AD5934, with its 27-bit phase accumulator, allows for sub-Hz frequency tuning. The AD5934 can be used to inject a stimulus signal through the blood sample via a probe. The response signal is analyzed and the effective impedance of the blood is tabulated. The AD5934 is ideal for this application because it allows the user to tune to the specific frequency required for each test.
1 2 3 16 15
SENSOR/COMPLEX IMPEDANCE MEASUREMENT
The operational principle of a capacitive proximity sensor is based on the change of a capacitance in a RLC resonant circuit. This leads to changes in the resonant frequency of the RLC circuit, which can be evaluated as shown Figure 36. It is first required to tune the RLC circuit to the area of resonance. At the resonant frequency, the impedance of the RLC circuit is at a maximum. Therefore, a programmable frequency sweep and tuning capability is required, which is provided by the AD5934.
RESONANT FREQUENCY CHANGE IN RESONANCE DUE TO APPROACHING OBJECT
ADuC702x
TOP VIEW (Not to Scale)
RFB
4 5 6 7
TOP VIEW 14 (Not to Scale)
05325-058
AD5934
PROXIMITY IMPEDANCE ()
13 12 11 10 9
FO FREQUENCY (Hz)
Figure 36. Detecting a Change in Resonant Frequency
PROBE
8
7V
2
ADR43x
4
6
05325-057
An example of the use of this type of sensor is for a train proximity measurement system. The magnetic fields of the train approaching on the track change the resonant frequency to an extent that can be characterized. This information can be sent back to a mainframe system to show the train location on the network. Another application for the AD5934 is in parked vehicle detection. The AD5934 is placed in an embedded unit connected to a coil of wire underneath the parking location. The AD5934 outputs a single frequency within the 80 kHz to 100 kHz frequency range, depending upon the wire composition. The wire can be modeled as a resonant circuit. The coil is calibrated with a known impedance value and at a known frequency. The impedance of the loop is monitored constantly. If a car is parked over the coil, the impedance of the coil changes and the AD5934 detects the presence of the car.
0.1F
10F
Figure 35. Measuring a Blood Sample for a Strain of Virus
Rev. 0 | Page 26 of 32
AD5934
ELECTRO-IMPEDANCE SPECTROSCOPY
The AD5934 has found use in the area of corrosion monitoring. Corrosion in a metal such as aluminum, which is used in air craft and ships, requires continuous assessment because the metal is exposed to a wide variety of conditions such as temperature and moisture. The AD5934 offers an accurate and compact solution for this type of measurement compared to the large and expensive existing units on the market. Mathematically the corrosion of a metal is modeled using a RC network which consists of a resistance,Rs, in series with a parallel resistor and capacitor, Rp and Cp. A system metal would typically have values as follows: Rs 10 to 10 k, Rp 1 k to 1 M, and Cp 5 f to 70 f. The frequency range of interest when monitoring corrosion is 0.1 Hz to 100 kHz. To ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 200 mV region which the AD5934 is capable of outputting. A nearby processor or control unit like the ADuc702x would log a single impedance sweep from 0.1 kHz to 100 kHz every 10 minutes and download the results back to a control unit. In order to achieve system accuracy from the 0.1 kHz to 1 kHz region, the system clock needs to be scaled down from the 16.776 MHz nominal clock frequency to 500 kHz, typically. The clock scaling can be achieved digitally using an external direct digital synthesizer like the AD9834 as a programmable divider, which supplies a clock signal to MCLK and which can be controlled digitally by the nearby microprocessor.
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AD5934 CHOOSING A REFERENCE FOR THE AD5934
To achieve the best performance from the AD5934, thought should be given to the choice of a precision voltage reference. The AD5934 has three reference inputs: (AVDD1, AVDD2, and DVDD). It is recommended that the voltage on these reference inputs be run from the same voltage supply. There are four possible sources of error that should be considered when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as a device in the ADR43X family, allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Because the supply current required by the AD5934 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case. This requires less than 100 A of quiescent current. It also provides very good noise performance at 8 V p-p in the 0.1 Hz to 10 Hz range. Long-term drift is a measure of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains stable during its entire lifetime. A reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the system output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference with as low an output noise voltage as practical for the system noise resolution required is important. Precision voltage references such as the ADR433 produce low output noise in the 0.1 Hz to 10 Hz region. Examples of some recommended precision references for use as supply to the AD5934 are shown in Table 19.
Table 19. List of Precision References for theAD5934
Part No. ADR433B ADR433A ADR434B ADR434A ADR435B ADR435A ADR439B ADR439A Initial Accuracy (mV max) 1.4 4.0 1.5 5 2 6 2 5.4 Output Voltage (V) 3. 0 3. 0 4. 096 4. 096 5.0 5.0 4.5 4.5 Temp. Drift (ppm/C max) 3 10 3 10 3 10 3 10 0.1 Hz to 10 Hz Noise (V p-p typ) 3.75 3.75 6.25 6.25 8 8 7.5 7.5
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AD5934 LAYOUT AND CONFIGURATION
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5934 should have separate analog and digital sections, each having its own area of the board. If the AD5934 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5934. The power supply to the AD5934 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI); common ceramic types of capacitors are suitable. The 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
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AD5934 OUTLINE DIMENSIONS
6.50 6.20 5.90
16
9
5.60 5.30 5.00
1 8
8.20 7.80 7.40
PIN 1 1.85 1.75 1.65
2.00 MAX
0.25 0.09 8 4 0 0.95 0.75 0.55
0.05 MIN 0.65 BSC COPLANARITY 0.10
0.38 0.22
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-150-AC
Figure 37. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5934YRSZ 1 AD5934YRSZ-REEL71 EVAL-AD5934EB
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Shrink Small Outline Package (SSOP) 16-Lead Shrink Small Outline Package (SSOP) Evaluation Board
Package Option RS-16 RS-16
Z = Pb-free part.
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AD5934 NOTES
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AD5934 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05325-0-6/05(0)
T T
Rev. 0 | Page 32 of 32

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