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| FDD26AN06A0 August 2004 FDD26AN06A0 N-Channel PowerTrench(R) MOSFET 60V, 36A, 26m Features * rDS(ON) = 20m (Typ.), VGS = 10V, ID = 36A * Qg(tot) = 13nC (Typ.), VGS = 10V * Low Miller Charge * Low QRR Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101 Formerly developmental type 82544 Applications * Motor / Body Load Control * ABS Systems * Powertrain Management * Injection Systems * DC-DC converters and Off-line UPS * Distributed Power Architectures and VRMs * Primary Switch for 12V and 24V systems DRAIN (FLANGE) GATE D G SOURCE TO-252AA FDD SERIES S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, RJA = 52oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy ( Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 36 25 7 Figure 4 35 75 0.5 -55 to 175 A A A A mJ W W/oC oC Ratings 60 20 Units V V Thermal Characteristics RJC RJA RJA Thermal Resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 2.0 100 52 o o C/W C/W oC/W This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Package Marking and Ordering Information Device Marking FDD26AN06A0 Device FDD26AN06A0 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 50V VGS = 0V VGS = 20V TC = 150oC 60 1 250 100 V A nA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 36A, VGS = 10V ID = 36A, VGS = 10V, TJ = 175oC 2 0.020 0.045 4 0.026 0.058 V Dynamic Characteristics CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge (VGS = 10V) VDD = 30V, ID = 36A VGS = 10V, RGS = 25 9 72 23 35 123 88 ns ns ns ns ns ns VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 30V ID = 36A Ig = 1.0mA 800 155 55 13 1.7 4.3 2.6 4.6 17 2.2 pF pF pF nC nC nC nC nC Switching Characteristics tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 36A ISD = 18A ISD = 36A, dISD/dt = 100A/s ISD = 36A, dISD/dt = 100A/s 1.25 1.0 43 50 V V ns nC Notes: 1: Starting TJ = 25C, L = 83H, IAS = 29A, VDD = 54V, VGS = 10V. (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Typical Characteristics TC = 25C unless otherwise noted 1.2 40 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 150 175 30 0.8 0.6 20 0.4 10 0.2 0 125 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Case Temperature ZJC, NORMALIZED THERMAL IMPEDANCE PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.01 10-5 10-4 Figure 3. Normalized Maximum Transient Thermal Impedance 500 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 100 175 - TC 150 30 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Typical Characteristics TC = 25C unless otherwise noted 1000 10s IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) 100 10ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 1ms 100s 300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 10 DC STARTING TJ = 150oC 1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 100 VGS = 20V ID, DRAIN CURRENT (A) 80 VGS = 10V VGS = 7V 100 80 ID , DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = 25oC 60 TJ = 40 -55oC TJ = 175oC 60 40 VGS = 6V TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 20 20 VGS = 5V 0 3 4 5 6 7 8 9 VGS , GATE TO SOURCE VOLTAGE (V) 0 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) 4 Figure 7. Transfer Characteristics 20.0 DRAIN TO SOURCE ON RESISTANCE(m) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 19.5 2.5 Figure 8. Saturation Characteristics PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 19.0 1.5 18.5 1.0 VGS = 10V 18.0 0 10 20 30 ID, DRAIN CURRENT (A) 40 0.5 -80 -40 VGS = 10V, ID = 36A 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 9. Drain to Source On Resistance vs Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Typical Characteristics TC = 25C unless otherwise noted 1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 1.0 1.15 ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.05 0.8 1.00 0.6 0.95 0.4 -80 -40 0 40 80 12 (oC) 160 200 0.90 -80 -40 0 40 80 120 (oC) 160 200 TJ, JUNCTION TEMPERATURE TJ , JUNCTION TEMPERATURE Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 2000 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD 1000 C, CAPACITANCE (pF) VDD = 30V 8 COSS CDS + CGD CRSS = CGD 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 36A ID = 7A 0 2 4 6 8 10 12 14 100 2 VGS = 0V, f = 1MHz 30 0.1 1 10 60 0 VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Current (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS + IAS 0.01 0 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS RL VDD Qg(TOT) VDS VGS VGS VGS = 10V + VDD DUT Ig(REF) VGS = 2V 0 Qgs2 Qg(TH) Qgs Ig(REF) 0 Qgd Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 90% 50% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. P (T -T ) JM A = ----------------------------RJA 125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 100 RJA (oC/W) RJA = 33.32+ 154/(1.73+Area) EQ.3 75 DM (EQ. 1) 50 In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 25 0.01 (0.0645) 0.1 (0.645) 1 (6.45) 10 (64.5) AREA, TOP COPPER AREA in2 (cm2) Figure 21. Thermal Resistance vs Mounting Pad Area R JA = 33.32 + -----------------------------------154 ( 1.73 + Area ) 23.84 ( 0.268 + Area ) (EQ. 2) Area in Inches Squared R JA = 33.32 + --------------------------------- (EQ. 3) Area in Centimeters Squared (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 PSPICE Electrical Model .SUBCKT FDD26AN06A0 2 1 3 ; rev July 2004 Ca 12 8 3.2e-10 Cb 15 14 3.2e-10 Cin 6 8 7.7e-10 10 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 21 16 RSLC2 ESG + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 6 8 It 8 17 1 Lgate 1 9 4.9e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.5e-9 RLgate 1 9 49 RLdrain 2 5 10 RLsource 3 7 25 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 4e-3 Rgate 9 20 3.8 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 7e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),2.7))} .MODEL DbodyMOD D (IS=3.8E-12 N=1.06 RS=4.2e-3 TRS1=2e-3 TRS2=1.1e-6 + CJO=5.8e-10 M=0.53 TT=2.5e-8 XTI=3.9) .MODEL DbreakMOD D (RS=1.8 TRS1=1e-4 TRS2=-1e-6) .MODEL DplcapMOD D (CJO=2.13e-10 IS=1e-30 N=10 M=0.43) .MODEL MmedMOD NMOS (VTO=3.4 KP=2.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.8) .MODEL MstroMOD NMOS (VTO=4.1 KP=21 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.96 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=38 RS=0.1) .MODEL RbreakMOD RES (TC1=9e-4 TC2=-6e-7) .MODEL RdrainMOD RES (TC1=7e-4 TC2=3.3e-5) .MODEL RSLCMOD RES (TC1=2.5e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=9e-3 TC2=9e-6) .MODEL RvthresMOD RES (TC1=-4e-3 TC2=-1e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.0) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2004 Fairchild Semiconductor Corporation - Ebreak 11 7 17 18 65.4 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 5 51 + Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD DBODY FDD26AN06A0 Rev. A FDD26AN06A0 SABER Electrical Model rev July 2004 template FDD26AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=3.8e-12,nl=1.06,rs=4.2e-3,trs1=2e-3,trs2=1.1e-6,cjo=5.8e-10,m=0.53,tt=2.5e-8,xti=3.9) dp..model dbreakmod = (rs=1.8,trs1=1e-4,trs2=-1e-6) dp..model dplcapmod = (cjo=2.13e-10,isl=10e-30,nl=10,m=0.43) m..model mmedmod = (type=_n,vto=3.4,kp=2.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.1,kp=21,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.96,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.0,voff=-0.5) 10 RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2.0) RSLC1 c.ca n12 n8 = 3.2e-10 51 RSLC2 c.cb n15 n14 = 3.2e-10 ISCL c.cin n6 n8 = 7.7e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 65.4 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 S1A S2A 13 8 S1B CA 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY DRAIN 2 RLGATE LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE RBREAK 18 RVTEMP 19 l.lgate n1 n9 = 4.9e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.5e-9 res.rlgate n1 n9 = 49 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 25 12 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-6e-7 res.rdrain n50 n16 = 4e-3, tc1=7e-4,tc2=3.3e-5 res.rgate n9 n20 = 3.8 res.rslc1 n5 n51 = 1e-6, tc1=2.5e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 7e-3, tc1=9e-3,tc2=9e-6 res.rvthres n22 n8 = 1, tc1=-4e-3,tc2=-1e-5 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/110))** 2.7)) } } (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A FDD26AN06A0 PSPICE Thermal Model REV 23 July 2004 FDD26AN06A0T CTHERM1 TH 6 2.0e-3 CTHERM2 6 5 7.0e-3 CTHERM3 5 4 8.0e-3 CTHERM4 4 3 8.7e-3 CTHERM5 3 2 1.0e-2 CTHERM6 2 TL 4.0e-2 RTHERM1 TH 6 5.0e-2 RTHERM2 6 5 1.5e-1 RTHERM3 5 4 1.9e-1 RTHERM4 4 3 2.8e-1 RTHERM5 3 2 4.6e-1 RTHERM6 2 TL 4.7e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD26AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =2.0e-3 ctherm.ctherm2 6 5 =7.0e-3 ctherm.ctherm3 5 4 =8.0e-3 ctherm.ctherm4 4 3 =8.7e-3 ctherm.ctherm5 3 2 =1.0e-2 ctherm.ctherm6 2 tl =4.0e-2 rtherm.rtherm1 th 6 =5.0e-2 rtherm.rtherm2 6 5 =1.5e-1 rtherm.rtherm3 5 4 =1.9e-1 rtherm.rtherm4 4 3 =2.8e-1 rtherm.rtherm5 3 2 =4.6e-1 rtherm.rtherm6 2 tl =4.7e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE (c)2004 Fairchild Semiconductor Corporation FDD26AN06A0 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM ImpliedDisconnectTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I11 |
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