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FIN3385 * FIN3383 * FIN3384 * FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
October 2003 Revised April 2005
FIN3385 * FIN3383 * FIN3384 * FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and transmitted. The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces.
Features
s Low power consumption s 20 MHz to 85 MHz shift clock support s r1V common-mode range around 1.2V s Narrow bus reduces cable size and cost s High throughput (up to 2.38 Gbps throughput) s Internal PLL with no external component s Compatible with TIA/EIA-644 specification s Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number FIN3383MTD FIN3384MTD FIN3385MTD FIN3386MTD Package Number MTD56 MTD56 MTD56 MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix Part FIN3385 FIN3383 FIN3386 FIN3384 CLK Frequency 85 66 85 66 LVTTL IN 28 28 LVDS OUT 4 4 4 4 28 28 LVDS IN LVTTL OUT Package 56 TSSOP 56 TSSOP 56 TSSOP 56 TSSOP
(c) 2005 Fairchild Semiconductor Corporation
DS500864
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FIN3385 * FIN3383 * FIN3384 * FIN3386
Block Diagrams
Functional Diagram for FIN3385 and FIN3383
Receiver Functional Diagram for FIN3386 and FIN3384
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TRANSMITTERS Pin Descriptions
Pin Names TxIn TxCLKIn TxOut TxOut TxCLKOut TxCLKOut R_FB PwrDn PLL VCC PLL GND LVDS VCC LVDS GND VCC GND NC I/O Type Number of Pins I I O O O O I I I I I I I I 28/21 1 4/3 4/3 1 1 1 1 1 2 1 3 3 5 Description of Signals LVTTL Level Input LVTTL Level Clock Input The rising edge is for data strobe. Positive LVDS Differential Data Output Negative LVDS Differential Data Output Positive LVDS Differential Clock Output Negative LVDS Differential Clock Output Rising Edge Clock (HIGH), Falling Edge Clock (LOW) LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in High Impedance state. Power Supply Pin for PLL Ground Pins for PLL Power Supply Pin for LVDS Output Ground Pins for LVDS Output Power Supply Pins for LVTTL Input Ground pins for LVTTL Input No Connect
Connection Diagram
FIN3383 and FIN3385 (28:4 Transmitter) Pin Assignment for TSSOP
Truth Table
Inputs TxIn Active Active F F X TxCLKIn Active L/H/Z Active F X PwrDn (Note 1) H H H H L Outputs TxOutr L/H L/H L L Z TxCLKOutr L/H X (Note 2) L/H X (Note 2) Z
H HIGH Logic Level L LOW Logic Level X Don't Care Z High Impedance F Floating Note 1: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V. Note 2: TxCLKOutr will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z).
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RECEIVERS Pin Descriptions
Pin Names I/O Type RxIn RxIn RxCLKIn RxCLKIn RxOut RxCLKOut PwrDn PLL VCC PLL GND LVDS VCC LVDS GND VCC GND NC I I I I O O I I I I I I I Number of Pins 4/3 4/3 1 1 28/21 1 1 1 2 1 3 4 5 Description of Signals Negative LVDS Differential Data Input Positive LVDS Differential Data Input Negative LVDS Differential Clock Input Positive LVDS Differential Clock Input LVTTL Level Data Output Goes HIGH for PwrDn LOW LVTTL Clock Output LVTTL Level Input Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table Power Supply Pin for PLL Ground Pins for PLL Power Supply Pin for LVDS Input Ground Pins for LVDS Input Power Supply for LVTTL Output Ground Pin for LVTTL Output No Connect
Connection Diagram
FIN3386 and FIN3384 (4:28 Receiver) Pin Assignment for TSSOP
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Transmitter and Receiver Power-Up/Power-Down Operation Truth Table
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin. Transmitter VCC TxIn TxOut TxCLKIn TxCLKOutr PwrDn Receiver RxInr RxOut RxCLKInr RxCLKOut PwrDn VCC
H HIGH Logic Level L LOW Logic Level P Last Valid State X Don't Care Z High-Impedance
PwrDn
Normal
2V
X Z X Z L X Z X Z L
!2V
X Z X Z L PwrDn X L X (Note 5) L
!2V
Active Active Active Active H Active L/H Active Active H
!2V
Active X H/L/Z (Note 3) H Active P (Note 4) (Note 5) H
!2V
!2V
H (Note 4) H Active (Note 5) H
H (Note 4) P (Note 4) (Note 5) H
2V
2V
2V
2V
2V
2V
Note 3: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a known low frequency and stay until the clock starts normal operation again. Note 4: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition) Note 5: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices. Note 6: Shorted here means (r inputs are shorted to each other, or r inputs are shorted to each other and Ground or VCC, or either r inputs are shorted to Ground or VCC) with no other Current/Voltage sources (noise) applied. If the VID is still in the valid range (greater than 100mV) and VCM is in the valid range (0V to 2.4V) then the input signal is still recognized and the part will respond normally.
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Absolute Maximum Ratings(Note 7)
Power Supply Voltage (VCC) TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Maximum Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 4 seconds) ESD Rating (HBM, 1.5 k:, 100 pF) I/O to GND All Pins ESD Rating (MM, 0:, 200 pF) 260qC -0.3V to +4.6V
Recommended Operating Conditions
Supply Voltage (VCC) Operating Temperature (TA)(Note 7) Maximum Supply Noise Voltage (VCCNPP) 100 mVP-P (Note 8) 3.0V to 3.6V
0.5V to 4.6V
-0.3V to +4.6V Continuous
10C to 70C
65qC to 150qC
150qC
!10.0 kV !6.5 kV !400V
Note 7: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. Note 8: 100mV VCC noise should be tested for frequency at least up to 2 MHz. All the specification below should be met under such a noise.
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9)
Symbol VIH VIL VIK IIN Input High Voltage Input Low Voltage Input Clamp Voltage Input Current IIK VIN VIN Transmitter LVDS Output Characteristics (Note 10) VOD Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Short Circuit Output Current Disabled Output Leakage Current 28:4 Transmitter Power Supply Current for Worst Case Pattern (With Load) (Note 11) RL 100 :, See Figure 3 VOUT DO 0V 0V to 4.6V, PwrDn 0V RL 100 :, See Figure 1 250 1.125 TBD 1.25 450 35.0 1.375 mV mV V mV mA Parameter Test Conditions Min 2.0 GND Typ Max VCC 0.8 Units V V V
Transmitter LVTTL Input Characteristics
18 mA
0.4V to 4.6V GND
0.79
1.8
1.5
10.0
10.0
0
PA
'VOD
VOS
'VOS
IOS IOZ ICCWT
3.5 r1.0
31.0 32.0 37.0 42.0 10.0 32.5 MHz 29.0 30.0 35.0 39.0 40.0 MHz 65.0 MHz 85.0 MHz
5.0 r10.0
49.5 55.0 60.5 66.0 55.0 41.8 44.0 49.5 55.0
PA
Transmitter Supply Current 32.5 MHz 40.0 MHz 66.0 MHz 85.0 MHz ICCPDT ICCGT Powered Down Supply Current 28:4 Transmitter Supply Current for 16 Grayscale (Note 11) See Figure 21 (Note 12)
Note 9: All Typical values are at TA 25qC and with VCC 3.3V.
mA
PwrDn
0.8V
PA
mA
Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD). Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels. Note 12: The 16-grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.
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Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol tTCP tTCH tTCL tCLKT tJIT tXIT tTLH tTHL tSTC tHTC tTPDD tTCCD Parameter Transmit Clock Period Transmit Clock (TxCLKIn) HIGH Time Transmit Clock Low Time TxCLKIn Transition Time (Rising and Failing) TxCLKIn Cycle-to-Cycle Jitter TxIn Transition Time Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) TxIn Setup to TxCLNIn TxIn Holds to TCLKIn Transmitter Power-Down Delay Transmitter Clock Input to Clock Output Delay Transmitter Clock Input to Clock Output Delay Transmitter Output Data Jitter (f tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tJCC 40 MHz) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 65 MHz) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 85 MHz) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 FIN3385 Transmitter Clock Out Jitter (Cycle-to-Cycle) See Figure 20 tTPLLS Transmitter Phase Lock Loop Set Time (Note 15) f f f 40 MHz 65 MHz 85 MHz See Figure 16 a 1 fx7 See Figure 16 a 1 fx7 See Figure 16 a 1 fx7 1.5 0.75 0.75 85 MHz) 2.5 0 100 3.3V) 2.8 5.5 6.8 0 a 2a 3a 4a 5a 6a 0 a 2a 3a 4a 5a 6a 0 a 2a 3a 4a 5a 6a 350 210 110 0.25 a0.25 2a0.25 3a0.25 4a0.25 5a0.25 6a0.25 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 370 230 150 10.0 ms ps (10% to 90%) See Figure 6 See Figure 5 Test Conditions Min 11.76 0.35 0.35 1.0 Typ T 0.5 0.5 Max 50.0 0.65 0.65 6.0 3.0 6.0 1.5 1.5 Units ns T T ns ns ns ns ns ns ns ns ns
LVDS Transmitter Timing Characteristics See Figure 4 See Figure 5 (f
See Figure 12, (Note 13) (TA 25qC and with VCC See Figure 9
0.25
a0.25 2a0.25 3a0.25 4a0.25 5a0.25 6a0.25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Transmitter Output Data Jitter (f
0.2
a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2
Transmitter Output Data Jitter (f
0.2
a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2
See Figure 22, (Note 14)
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and Power-Down pin is above 1.5V. Note 14: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 14). Figure 16 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
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Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Symbol VIH VIL VOH VOL VIK IIN IOFF IOS VTH VTL VICM IIN Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Clamp Voltage Input Current Input/Output Power Off Leakage Current Output Short Circuit Current Differential Input Threshold HIGH Differential Input Threshold LOW Input Common Mode Range Input Current IOH IOL IIK VIN VCC VOUT Parameter Test Conditions Min 2.0 GND Typ Max VCC 0.8 3.3 0.06 0.3 Units V V V V V
LVTTL/CMOS DC Characteristics
0.4 mA
2mA
2.7
18 mA
0V to 4.6V 0V, 0V
0.79 10.0
1.5
10.0
PA PA
mA mV mV V
All LVTTL Inputs/Outputs 0V to 4.6V
r10.0 60.0 120
100
Receiver LVDS Input Characteristics Figure 2, Table 2 Figure 2, Table 2 Figure 2, Table 2 VIN VIN Receiver Supply Current ICCWR 4:28 Receiver Power Supply Current for Worst Case Pattern (With Load) (Note 17) ICCWR 3:21 Receiver Power Supply Current for Worst Case Pattern (With Load) (Note 17) CL 8 pF, See Figure 3 CL 8 pF, See Figure 3 32.5 MHz 40.0 MHz 66.0 MHz 85.0 MHz 32.5 MHz 40.0 MHz 66.0 MHz 85.0 MHz ICCPDT tRCOP tRCOL tRCOH tRSRC tRHRC tROLH tROHL tRCCD tRPDD tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSKM tRPLLS Powered Down Supply Current Receiver Clock Output (RxCLKOut) Period RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Receiver Clock Input to Clock Output Delay Receiver Power-Down Delay Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit 2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 RxIN Skew Margin Receiver Phase Lock Loop Set Time See Figure 17, (Note 19) See Figure 11 See Figure 17 (f 85MHz) CL 8 pF, See Figure 4 See Figure 20, (Note 18) TA 25qC and VCC 3.3V See Figure 13 0.49 2.17 3.85 5.53 7.21 8.89 10.57 290 10.0 0.84 2.52 4.20 5.88 7.56 9.24 10.92 3.5 See Figure 8 (f 85MHz) (Rising Edge Strobe) PwrDn 0.8V (RxOut stays LOW) 11.76 4.0 4.5 3.5 3.5 2.0 1.8 5.0 3.5 3.5 7.5 1.0 1.19 2.87 4.55 6.23 7.91 9.59 11.27 49.0 53.0 78.0 90.0 NA T 5.0 5.0 70.0 75.0 114 135 60.0 65.0 100 115 55.0 50.0 6.0 6.5 ns ns ns ns ns ns ns mA mA 2.4V, VCC 0V, VCC 3.6V or 0V 3.6V or 0V
100
0.05 2.35
r10.0 r10.0
PA PA
PA
Ps
ns ns ns ns ns ns ns ps ms
Note 16: All Typical values are at TA 25qC and with V CC 3.3V. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD). Note 17: The power supply current for the receiver can be different with the number of active I/O channels. Note 18: Total channel latency from Sewrializer to deserializer is (T tTCCD). There is the clock period. Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
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Receiver AC Electrical Characteristics (66MHz)
Symbol tRCOP tRCOL tRCOH tRSRC tRHRC tRCOL tRCOH tRSRC tRHRC tROLH tROHL tRCCD tRPDD tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSKM tRPLLS Parameter Receiver Clock Output (RxCLKOut) Period RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Receiver Clock Input to Clock Output Delay Receiver Power-Down Delay Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit 2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 RxIn Skew Margin See Figure 17, (Note 22) Receiver Phase Lock Loop Set Time f f 40 MHz 66 MHz See Figure 17 (f 65 MHz) See Figure 17 (f 40 MHz) See Figure 8, (Note 20) (Rising Edge Strobe) (f CL 66 MHz) 8 pF, (Note 20) See Figure 8 (Rising Edge Strobe) (f 40 MHz) Test Conditions See Figure 8 Min 15.0 10.0 10.0 6.5 6.0 5.0 5.0 4.5 4.0 Typ T 11.0 12.2 11.6 11.6 6.3 7.6 7.3 6.3 2.0 1.8 3.3V 3.5 5.0 5.0 5.0 7.5 1.0 1.0 4.5 8.1 11.6 15.1 18.8 22.5 0.7 2.9 5.1 7.3 9.5 11.7 13.9 490 400 10.0 1.4 5.0 8.5 11.9 15.6 19.2 22.9 1.1 3.3 5.5 7.7 9.9 12.1 14.3 2.15 5.8 9.15 12.6 16.3 19.9 23.6 1.4 3.6 5.8 8.0 10.2 12.4 14.6 9.0 9.0 Max 50.0 Units ns ns ns ns ns ns ns ns ns ns ns ns
See Figure 8 See Figure 10, (Note 21) TA 25qC and VCC See Figure 13
Ps
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ms
See Figure 11
Note 20: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through 0.8V. Note 21: Total channel latency from Sewrializer to deserializer is (T tTCCD) (2*T tRCCD). There is the clock period. Note 22: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
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FIGURE 1. Differential LVDS Output DC Test Circuit
Note A: For all input pulses, tR or tF 1 ns. Note B: CL includes all probe and jig capacitance.
FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 Resulting Differential Input Voltage Resulting Common Mode Input Voltage (mV) VID 100 (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3
100
100
100
100
100
600
600
600
600
600
600
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AC Loading and Waveforms
Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 3. "Worst Case" Test Pattern
FIGURE 4. Transmitter LVDS Output Load and Transition Times
FIGURE 5. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
FIGURE 6. Transmitter Input Clock Transition Time
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AC Loading and Waveforms
(Continued)
FIGURE 7. Transmitter Outputs Channel-to-Channel Skew
Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through 0.8V.
FIGURE 8. (Receiver) Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
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AC Loading and Waveforms
(Continued)
FIGURE 11. Receiver Phase Lock Loop Set Time
FIGURE 12. Transmitter Power-Down Delay
FIGURE 13. Receiver Power-Down Delay
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AC Loading and Waveforms
(Continued)
Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is output from the transmitter.
FIGURE 14. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs
Note: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference. All the information in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
FIGURE 15. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs
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AC Loading and Waveforms
(Continued)
FIGURE 16. Transmitter Output Pulse Bit Position
FIGURE 17. Receiver Input Bit Position
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AC Loading and Waveforms
(Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
FIGURE 18. Receiver LVDS Input Skew Margin
Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used if no M1 software is available, but the test methodology in Figure 20 should be followed.
FIGURE 19. Transmitter Clock Out Jitter Measurement Setup
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter r3ns (cycle-to-cycle) clock input. The specific test methodology is as follows: * * Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right 3ns when data is HIGH. The r3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise (VCC noise frequency 2 MHz).
FIGURE 20. Timing Diagram of Transmitter Clock Input with Jitter
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AC Loading and Waveforms
(Continued)
Note: The 16-grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.
FIGURE 21. "16 Grayscale" Test Pattern
FIGURE 22. Transmitter Phase Lock Loop Time
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FIN3385 * FIN3383 * FIN3384 * FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 18 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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