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| FP31QF 2-Watt HFET The Communications Edge TM Product Information Product Features * * * * * * * 50 - 4000 MHz 18 dB Gain @ 900 MHz +34 dBm P1dB +46 dBm Output IP3 High Drain Efficiency Pb-free 6mm 28-pin QFN package MTTF > 100 years Product Description The FP31QF is a high performance 2-Watt HFET (Heterostructure FET) in a low-cost lead-free 28-pin 6x6 mm QFN (Quad Flatpack, No-Lead) surface-mount package. This device works optimally at a drain bias of +9 V and 450 mA to achieve +46 dBm output IP3 performance and an output power of +34 dBm at 1-dB compression. The device conforms to WJ Communications' long history of producing high reliability and quality components. The FP31QF has an associated MTTF of a minimum of 100 years at a mounting temperature of 85C. All devices are 100% RF & DC tested. The product is targeted for use as driver amplifiers for wireless infrastructure where high performance and high efficiency are required. Functional Diagram GND GND GND GND 28 GND 1 GND 2 GATE / 3 RF IN GND 4 GND 5 GND 6 GND 7 8 GND 9 GND 10 GND 11 GND 12 GND 13 GND 14 GND 27 GND 23 GND 26 25 24 GND 22 21 GND 20 GND 19 DRAIN / RF OUT 18 GND 17 GND 16 GND 15 GND Applications * * * * * * Mobile Infrastructure CATV / DBS W-LAN / ISM RFID Defense / Homeland Security Fixed Wireless Function Gate / RF Input Drain / RF Output Ground Pin No. 3 19 All other pins & backside copper Specifications DC Parameter Saturated Drain Current, Idss Transconductance, Gm Pinch Off Voltage, Vp (1) Typical Performance (4) Units Min mA mS V Typ 1170 590 -2.0 Max Parameter Frequency Gain S11 S22 Output P1dB Output IP3 (3) Noise Figure IS-95 Channel Power @ -45 dBc ACPR Units MHz dB dB dB dBm dBm dB dBm dBm V mA 915 18 -20 -12 +34 +46 3.5 Typical 1960 2140 2450 13.5 13 12 -20 -18 -18 -11 -24 -15 +33.8 +33.2 +33.5 +46.8 +46.6 +46.8 4.5 4.6 4.6 RF Parameter (2) Operational Bandwidth Test Frequency Small Signal Gain Maximum Stable Gain Output P1dB Output IP3 (3) Noise Figure Units Min MHz MHz dB dB dBm dBm dB 50 Typ 800 18 24 +34 +46 3.5 Max 4000 +27.8 +27.3 +25 +9 450 W-CDMA Ch. Power @ -45 dBc ACLR Drain Voltage Drain Current (5) (5) 1. Pinch-off voltage is measured when Ids = 4.8 mA. 2. Test conditions unless otherwise noted: T = 25C, VDS = 9 V, IDQ = 450 mA, in a tuned application circuit with ZL = ZLOPT, ZS = ZSOPT (optimized for output power). 3. 3OIP measured with two tones at an output power of +18 dBm/tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule. 4. Typical parameters represent performance in an application circuit. 5. Empirical measurements showed optimal power performance at a drain voltage = 9 volts at 450 mA. Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million hours MTTF rating, the biasing condition should maintain a junction temperature below 160 C over all operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5 C/W + (maximum operating temperature). Absolute Maximum Rating Parameter Operating Case Temperature Storage Temperature DC Power RF Input Power (continuous) Drain to Gate Voltage, Vdg Junction Temperature -40 to +85 C -55 to +125 C 7.5 W 6 dB above Input P1dB +14 V +220 C Ordering Information Part No. FP31QF FP31QF-F FP31QF-PCB900 FP31QF-PCB1900 FP31QF-PCB2140 Rating Description 2-Watt HFET (Leaded QFN Pkg) 2-Watt HFET (lead-free/RoHS-compliant QFN Pkg) 870 - 960 MHz Application Circuit 1930 - 1990 MHz Application Circuit 2110 - 2170 MHz Application Circuit Operation of this device above any of these parameters may cause permanent damage. Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET The Communications Edge TM Product Information Typical Device Data S-Parameters (VDS = +9 V, IDS = 450 mA, T = 25C, calibrated to device leads) S21, Maximum Stable Gain vs. Frequency 6 0. S11 1.0 S22 1.0 6 0. 30 0. 4 Swp Max 6GHz 2. 0 Swp Max 6GHz 2. 0 4 S21, MSG (dB) 0 .2 0 3. 0 4. 5 .0 3 10.0 0.2 0.4 0.6 0.8 1.0 2.0 4.0 5.0 3.0 10 .0 2 1 0 10 - 5. 0 2 DB(|S[2,1]|) DB(MSG) - 0. 2 -1 0. 0 0 0 0.5 1 1.5 Frequency (GHz) 2 2.5 3 .4 -0 .4 -0 .0 -2 -0 .6 -0 .8 Note: Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines. The S-parameters shown are the de-embedded data down to the device leads and represents typical performance of the device. Freq (MHz) 50 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 S11 (mag) S11 (ang) S21 (mag) S21 (ang) S12 (mag) S12 (ang) S22 (mag) 0.985 -21.82 24.458 166.25 0.006 76.01 0.096 0.936 -88.63 17.968 128.52 0.020 43.34 0.329 0.913 -128.61 11.520 104.42 0.025 22.03 0.431 0.899 -148.43 8.132 90.03 0.026 10.75 0.465 0.900 -160.54 6.225 79.35 0.026 4.56 0.490 0.900 -169.15 4.988 70.50 0.025 0.35 0.514 0.900 -176.01 4.125 62.56 0.025 -2.975 0.532 0.905 178.53 3.504 55.28 0.024 -4.91 0.560 0.909 172.99 3.046 47.93 0.023 -5.54 0.587 0.910 168.27 2.656 41.65 0.022 -4.44 0.606 0.914 164.14 2.349 34.95 0.021 -1.12 0.629 0.914 160.09 2.117 28.98 0.021 5.24 0.656 0.915 156.76 1.897 23.31 0.022 12.75 0.671 0.922 153.22 1.721 17.69 0.026 23.36 0.695 0.926 149.22 1.563 11.97 0.034 32.54 0.720 0.941 144.67 1.433 6.20 0.058 34.08 0.734 0.943 140.45 1.318 0.98 0.102 23.74 0.768 Device S-parameters are available for download off of the website at: http://www.wj.com S22 (ang) -110.34 -135.13 -151.01 -158.3 -162.14 -163.92 -166.86 -168.72 -170.95 -172.86 -175.13 -177.13 -179.41 177.36 175.05 171.21 165.82 Load-Pull Data at 1.96 and 2.14 GHz (Vds = 8 V, Ids = 500 mA, 25C, ZS = 50 , calibrated to device pins) Freq (GHz) 1.96 2.14 1.0 0.8 ZS () 5 + j0 5 - j2 P1dB ZL () 8 - j2 8 - j3 Swp Max 1.96GHz 2. 0 Gain (dB) 18.5 18.0 P1dB (dBm) OIP3 (dBm) +34 +48 +34 +48 Output IP3 PAE (%) 49 50 Swp Max 1.96GHz 2. 0 3. 0 4. 0. 2 0 5. 0 0.2 10.0 10.0 48 47 33 31 0 0.2 44 41 .4 -0 30 -4 .0 27 .4 -0 .0 .6 -0 -0.8 -0 .6 P1dB max (1.96 GHz) = +34 dBm at ZL = 8 - j2 Swp Min 1e-009GHz -0.8 .0 -2 -2 OIP3 max (1.96 GHz) = +48 dBm at ZL = 8 - j2 Specifications and information are subject to change without notice Swp Min 1e-009GHz -1.0 WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com -1.0 -4 .0 28 0 -5. 0 -3 .0 - 5. 29 2 -0 . 43 42 -10.0 -1 0.0 32 46 45 10.0 0.8 3.0 4.0 0.2 0.4 0.6 1.0 2.0 5.0 0.8 3.0 4.0 0.2 0.4 0.6 1.0 2.0 5.0 0 0 0. 4 1.96 GHz r 8 Ohm x -2 Ohm 0. 4 1.96 GHz r 8 Ohm x -2 Ohm 6 6 0. 0. 0.8 1.0 0 3. 0 4. 5. 0 10.0 -1.0 Swp Min 0.01GHz -0 .6 -1.0 -0 .8 .0 -2 Swp Min 0.01GHz November 2004 - 5. -4 .0 0 2 - 0. -1 0. 0 1 10.0 -3 .0 0.2 0.4 0.6 0.8 1.0 2.0 4.0 5.0 3.0 0 0 .2 20 6 5 4 3 0. 4 5 6 0. 8 0. 8 0 3. 0 4. 5 .0 10 .0 -4 .0 -3 .0 -3 . FP31QF 2-Watt HFET The Communications Edge TM Product Information Application Circuit: 870 - 960 MHz (FP31QF-PCB900) The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25C Frequency S21 - Gain S11 - Input Return Loss S22 - Output Return Loss Output P1dB Output IP3 (+18 dBm / tone, 1 MHz spacing) MHz dB dB dB dBm dBm dB dBm 870 18.3 -15 -9.3 +33.9 3.4 915 18 -20 -12 +34 +46 3.5 +27.8 960 17.7 -16 -16 +33.7 3.5 Noise Figure IS-95 Channel Power @ -45 dBc ACPR Bill of Materials Ref. Desig. C1, C4, C8, C10 C2, C3 C6, C11 C7 C12 L1, L2 L3 R1 R2 Q1 C5 * * * * Value 100 pF 4.7 pF 0.018 F 1000 pF 0.1 F 27 nH 3.3 nH 10 51 FP31QF Part style Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Wirewound chip inductor Multilayer chip inductor Chip resistor Chip resistor WJ 2W HFET Do Not Place Size 0603 0603 0805 0603 1206 0805 0603 0603 0603 QFN 6x6 C2 C3 Circuit Board Material: .014" FR-4 (r = 4.6), 4 layers (other layers added for rigidity), .062" total thickness, 1 oz copper The main microstrip line has a line impedance of 50 . The C2 and C3 placements are at silk screen markers, "H" and "9.5", respectively. The via hole spacing along the main microstrip line is .040". The distance from the edge of the FP31QF to the closer edge of L3 is .305". The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CA P CA P CAP ID=C6 ID =C7 ID=C8 C=10 0 pF C =100 0 pF C=1.8e 4 pF -Vgg Vds=9V @ 450 mA CAP ID=C12 C=1e 5 pF RES ID=R2 R=51 Ohm CAP ID=C11 C=1.8e 4 pF CAP ID =C10 C =10 0 pF CAP ID=C5 C=DNP pF TL INP ID=TL1 Z0 =50 Ohm L =500 mil Eeff=3 .46 Loss=0 F0 =0 MHz P ORT P =1 Z=50 Ohm CAP ID=C1 C=10 0 pF IND ID=L3 L =3.3 nH IND ID=L1 L =2 7 nH 1 2 IND ID=L2 L =2 7 nH CAP P ORT ID=C4 P =2 C=10 0 pF Z=50 Ohm CAP ID=C2 C=4.7 pF RES ID=R1 R=10 Ohm SUB CKT ID=Q1 NET="FP31QF" TL INP ID=TL2 Z0 =50 Ohm L =520 mil Eeff=3 .46 Loss=0 F0 =0 MHz CAP ID=C3 C=4.7 pF Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET S11 vs. Frequency S21 vs. Frequency The Communications Edge TM Product Information FP31QF-PCB900 Application Circuit Performance Plots S22 vs. Frequency 0 -5 S11 (dB) -10 -15 -20 -25 -30 860 -40c +25c +85c 20 19 S21 (dB) 18 17 16 -40c +25c +85c 0 -5 S22 (dB) -10 -15 -20 -25 -30 860 -40c +25c +85c 880 900 920 940 960 15 860 880 900 920 940 960 880 900 920 940 960 Frequency (MHz) P1dB vs. Frequency Frequency (MHz) Noise Figure vs. Frequency Frequency (MHz) ACPR vs. Channel Power IS-95, 9 Ch. Forward, 885 kHz offset, 30 kHz Meas BW 36 34 P1dB (dBm) 32 30 28 -40c +25c +85c 6 5 NF (dB) 4 3 2 1 0 860 -40c +25c +85c -40 freq = 915 MHz ACPR (dBc) -50 -60 -40 C +25 C +85 C 26 860 -70 880 900 920 940 960 22 23 24 25 26 27 28 29 Frequency (MHz) IMD products vs. Output Power 880 900 920 940 960 Frequency (MHz) OIP3 vs. Temperature Output Channel Power (dBm) OIP3 vs. Output Power 50 45 40 35 30 fundamental frequency = 915 MHz, 916 MHz; Temp = +25 C 50 IMD products (dBm) -20 -40 -60 -80 -100 fundamental frequency = 915 MHz, 916 MHz; Temp = +25 C 48 OIP3 (dBm) 46 44 42 freq = 915, 916 MHz +18 dBm / tone IMD_Low IMD_High 40 -40 -15 10 35 60 85 4 8 Temperature (C) Output Power / Gain vs. Input Power 20 18 frequency = 915 MHz, Temp = -40 C 12 16 20 Output Power (dBm) 24 28 OIP3 (dBm) 4 8 12 16 20 Output Power (dBm) frequency = 915 MHz, Temp = +85 C 24 28 Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 28 24 20 18 Gain (dB) Gain 16 14 12 10 -4 0 4 8 12 Input Power (dBm) 16 20 Output Power 28 24 20 16 frequency = 915 MHz, Temp = +25 C Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 20 18 36 Output Power (dBm) 32 Gain Gain (dB) Gain (dB) Gain 16 14 12 10 -4 0 4 8 12 Input Power (dBm) 16 20 16 14 12 10 -4 0 4 8 12 Input Power (dBm) 16 20 28 24 Output Power 20 16 Output Power 20 16 Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET The Communications Edge TM Product Information Application Circuit: 1930 - 1960 MHz (FP31QF-PCB1900) The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25C Frequency S21 - Gain S11 - Input Return Loss S22 - Output Return Loss Output P1dB Output IP3 (+18 dBm / tone, 1 MHz spacing) MHz dB dB dB dBm dBm dB dBm 1930 14 -17 -11 +33.5 4.3 1960 13.8 -21 -11 +33.8 +46.8 4.5 +27.3 1990 13.8 -27 -13 +33.8 4.4 Noise Figure IS-95 Channel Power @ -45 dBc ACPR Bill of Materials Ref. Desig. C1, C4, C8, C10 C2 C3 C6, C11 C7 C12 L1, L2 L3 R1 R2 Q1 C5 * * * * Value 22 pF 2.2 pF 2.0 pF 0.018 F 1000 pF 0.1 F 12 nH 4.7 nH 5.1 51 FP31QF Part style Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Wirewound chip inductor Multilayer chip inductor Chip resistor Chip resistor WJ 2W HFET Do Not Place Size 0603 0603 0603 0805 0603 1206 0805 0603 0603 0603 QFN 6x6 C2 C3 Circuit Board Material: .014" FR-4 (r = 4.6), 4 layers (other layers added for rigidity), .062" total thickness, 1 oz copper The main microstrip line has a line impedance of 50 . The C2 and C3 placements are at silk screen markers, "B" and "3", respectively. The via hole spacing along the main microstrip line is .040". The distance from the edge of the FP31QF to the closer edge of L3 is .305". The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CA P CA P CAP ID=C6 ID =C7 ID=C8 C=2 2 pF C =100 0 pF C=1.8e 4 pF -Vgg Vds=9V @ 450 mA CAP ID=C12 C=1e 5 pF RES ID=R2 R=51 Ohm CAP ID=C11 C=1.8e 4 pF CAP ID =C10 C =2 2 pF CAP ID=C5 C=DNP pF TLINP ID =TL1 Z0 =50 Ohm L =190 mil Eeff =3 .46 Loss =0 F0 =0 MHz P ORT P =1 Z=50 Ohm CAP ID=C1 C=2 2 pF IND ID=L3 L =4.7 nH IND ID=L1 L =1 2 nH 1 2 IND ID=L2 L =1 2 nH CAP ID=C4 C=2 2 pF P ORT P =2 Z=50 Ohm CA P ID=C2 C=2.2 pF RES ID=R1 R=5 Ohm SUB CKT ID=Q1 NET="FP31QF" TL INP ID=TL2 Z0 =50 Ohm L =200 mil Eeff=3 .46 Loss=0 F0 =0 MHz CAP ID=C3 C=2 pF Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET S11 vs. Frequency S21 vs. Frequency The Communications Edge TM Product Information FP31QF-PCB1900 Application Circuit Performance Plots S22 vs. Frequency 0 -5 S11 (dB) -10 -15 -20 -25 -30 1930 -40C +25C +85C 16 15 S21 (dB) 14 13 12 -40C +25C +85C 0 -5 S22 (dB) -10 -15 -20 -25 -30 1930 -40C +25C +85C 1950 1970 1990 11 1930 1950 1970 1990 1950 1970 1990 Frequency (MHz) P1dB vs. Frequency Frequency (MHz) Noise Figure vs. Frequency Frequency (MHz) ACPR vs. Channel Power IS-95, 9 Ch. Forward, 885 kHz offset, 30 kHz Meas BW 36 34 P1dB (dBm) 32 30 28 -40c +25c +85c 6 5 NF (dB) 4 3 2 1 0 1930 -40c +25c +85c -35 -45 -55 -65 freq = 1960 MHz ACPR (dBc) -40 C +25 C +85 C 26 1930 -75 1950 1970 1990 22 23 24 25 26 27 28 29 Frequency (MHz) IMD products vs. Output Power fundamental frequency = 1960, 1961 MHz; Temp = +25 C 1950 1970 1990 Frequency (MHz) OIP3 vs. Temperature Output Channel Power (dBm) OIP3 vs. Output Power 50 45 40 35 30 fundamental frequency = 1960, 1961 MHz; Temp = +25 C 50 IMD products (dBm) -20 -40 -60 48 OIP3 (dBm) 46 44 42 freq = 1960, 1961 MHz +18 dBm / tone IMD_Low -80 -100 IMD_High 40 -40 -15 10 35 60 85 4 8 Temperature (C) Output Power / Gain vs. Input Power 16 14 Gain (dB) Gain 12 10 8 Output Power 6 2 6 10 14 18 Input Power (dBm) 22 26 16 6 2 6 frequency = 1960 MHz, Temp = -40 C 12 16 20 Output Power (dBm) 24 28 OIP3 (dBm) 4 8 12 16 20 Output Power (dBm) frequency = 1960 MHz, Temp = +85 C 24 28 Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 28 24 20 16 14 frequency = 1960 MHz, Temp = +25 C Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 16 14 36 Output Power (dBm) 32 Gain (dB) 12 10 8 Gain 28 24 Output Power 20 16 10 14 18 Input Power (dBm) 22 26 Gain (dB) 12 10 8 6 2 Gain 28 24 20 16 6 10 14 18 Input Power (dBm) 22 26 Output Power Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET The Communications Edge TM Product Information Application Circuit: 2110 - 2170 MHz (FP31QF-PCB2140) The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25C Frequency S21 - Gain S11 - Input Return Loss S22 - Output Return Loss Output P1dB Output IP3 (+18 dBm / tone, 1 MHz spacing) MHz dB dB dB dBm dBm dB dBm 2110 13.2 -17 -14 +33.6 4.7 2140 13.3 -19 -24 +33.2 +46.6 4.6 +25 2170 13.1 -16 -18 +33.3 4.9 Noise Figure IS-95 Channel Power @ -45 dBc ACPR Bill of Materials Ref. Desig. C1, C4, C8, C10 C2, C3 C6, C11 C7 C12 L1, L2 L3 R1 R2 Q1 C5 * * * * Value 22 pF 2 pF 0.018 F 1000 pF 0.1 F 12 nH 4.7 nH 5.1 51 FP31QF Part style Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Wirewound chip inductor Multilayer chip inductor Chip resistor Chip resistor WJ 2W HFET Do Not Place Size 0603 0603 0805 0603 1206 0805 0603 0603 0603 QFN 6x6 C2 C3 Circuit Board Material: .014" FR-4 (r = 4.6), 4 layers (other layers added for rigidity), .062" total thickness, 1 oz copper The main microstrip line has a line impedance of 50 . The C2 and C3 placements are at silk screen markers, "A" and "2.5", respectively. The via hole spacing along the main microstrip line is .040". The distance from the edge of the FP31QF to the closer edge of L3 is .305". The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CA P CA P CAP ID=C6 ID =C7 ID=C8 C=2 2 pF C =100 0 pF C=1.8e 4 pF -Vgg Vds=9V @ 450 mA CAP ID=C12 C=1e 5 pF RES ID=R2 R=51 Ohm CAP ID=C11 C=1.8e 4 pF CAP ID =C10 C =2 2 pF CAP ID=C5 C=DNP pF TLINP ID =TL1 Z0 =50 Ohm L =150 mil Eeff =3 .46 Loss =0 F0 =0 MHz P ORT P =1 Z=50 Ohm CAP ID=C1 C=2 2 pF IND ID=L3 L =4.7 nH IND ID=L1 L =1 2 nH 1 2 IND ID=L2 L =1 2 nH CAP ID=C4 C=2 2 pF P ORT P =2 Z=50 Ohm CA P ID=C2 C=2 pF RES ID=R1 R=5 Ohm SUB CKT ID=Q1 NET="FP31QF" TL INP ID=TL2 Z0 =50 Ohm L =180 mil Eeff=3 .46 Loss=0 F0 =0 MHz CAP ID=C3 C=2 pF Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET S11 vs. Frequency S21 vs. Frequency The Communications Edge TM Product Information FP31QF-PCB2140 Application Circuit Performance Plots S22 vs. Frequency 0 -5 S11 (dB) -10 -15 -20 -25 -30 2110 -40c +25c +85c 15 14 S21 (dB) 13 12 11 -40c +25c +85c 0 -5 S22 (dB) -10 -15 -20 -25 -30 2110 -40c +25c +85c 2130 2150 2170 10 2110 2130 2150 2170 2130 2150 2170 Frequency (MHz) P1dB vs. Frequency Frequency (MHz) Noise Figure vs. Frequency Frequency (MHz) ACPR vs. Channel Power 3GPP W-CDMA, Test Model 1 + 64 DPCH, 5 MHz offset 36 34 P1dB (dBm) 32 30 28 -40C +25C +85C 6 5 NF (dB) 4 3 2 1 0 2110 -40C +25C +85C -35 -40 ACPR (dBc) -45 -50 -55 freq = 2140 MHz -40 C +25 C +85 C 26 2110 -60 2130 2150 2170 2130 2150 2170 22 23 24 25 26 27 Frequency (MHz) OIP3 vs. Temperature Frequency (MHz) IMD products vs. Output Power -40 IMD products (dBm) fundamental frequency = 2140, 2141 MHz; Temp = +25 C Output Channel Power (dBm) OIP3 vs. Output Power 50 45 40 35 30 fundamental frequency = 2140, 2141 MHz; Temp = +25 C 50 48 OIP3 (dBm) 46 44 42 freq = 2140, 2141 MHz +18 dBm / tone -60 IMD_Low -80 IMD_High -100 40 -40 -15 10 35 60 85 3 6 Temperature (C) Output Power / Gain vs. Input Power 14 12 Gain (dB) 10 8 6 4 2 6 10 14 18 Input Power (dBm) 22 26 Output Power Gain frequency = 2140 MHz, Temp = -40 C 9 12 15 Output Power (dBm) 18 21 OIP3 (dBm) 3 6 9 12 15 Output Power (dBm) frequency = 2140 MHz, Temp = +85 C 18 21 Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 28 24 20 16 14 12 frequency = 2140 MHz, Temp = +25 C Output Power / Gain vs. Input Power 36 Output Power (dBm) 32 28 24 14 12 36 Output Power (dBm) 32 Gain Gain (dB) Gain (dB) 10 8 6 4 2 6 10 14 18 Input Power (dBm) 22 26 10 8 6 Gain 28 24 20 Output Power 16 Output Power 20 16 4 2 6 10 14 18 Input Power (dBm) 22 26 Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25C Frequency S21 - Gain S11 - Input Return Loss S22 - Output Return Loss Output P1dB Output IP3 (+18 dBm / tone, 1 MHz spacing) The Communications Edge TM Product Information Reference Design: 2400 - 2500 MHz The application circuit is matched for output power. Measured S-Parameters 15 10 5 0 (dB) -5 -10 -15 -20 DB(|S[1,1]|) DB(|S[2,1]|) DB(|S[2,2]|) MHz dB dB dB dBm dBm dB 2400 2500 12.1 12.0 -13 -16 -13 -17 +33.5 +46.8 4.6 Noise Figure The 2.4 - 2.5 GHz Reference Circuit is shown for design purposes only. An evaluation board is not readily available for this application. The reader can obtain any FP31QF evaluation board and modify it with the circuit shown to achieve the performance shown in this reference design. -25 2.3 2.35 2.4 2.45 2.5 Frequency (GHz) 2.55 2.6 Bill of Materials Ref. Desig. C1, C4, C8, C10 C2, C3 C6, C11 C7 C12 L1, L2 L3 R1 R2 Q1 C5 * * * * Circuit Board Material: .014" FR-4 (r = 4.6), 4 layers (other layers added for rigidity), .062" total thickness, 1 oz copper The main microstrip line has a line impedance of 50 . Value 22 pF 1.5 pF 0.018 F 1000 pF 0.1 F 12 nH 3.3 nH 5.1 50 FP31QF Part style Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Wirewound chip inductor Multilayer chip inductor Chip resistor Chip resistor WJ 2W HFET Do Not Place Size 0603 0603 0805 0603 1206 0805 0603 0603 0603 QFN 6x6 C2 C3 The C2 and C3 placements are at silk screen markers, "A" and "2", respectively. The via hole spacing along the main microstrip line is .040". The distance from the edge of the FP31QF to the closer edge of L3 is .305". The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CA P CA P CAP ID=C8 ID=C6 ID =C7 C=2 2 pF C =100 0 pF C=1.8e 4 pF -Vgg Vds=9V @ 450 mA CAP ID=C12 C=1e 5 pF RES ID=R2 R=51 Ohm CAP ID=C11 C=1.8e 4 pF CAP ID =C10 C =2 2 pF CAP ID=C5 C=DNP pF TLINP ID =TL1 Z0 =50 Ohm L =150 mil Eeff =3 .46 Loss =0 F0 =0 MHz IND ID=L1 L =1 2 nH 2 P ORT P =1 Z=50 Ohm CAP ID=C1 C=2 2 pF IND ID=L3 L =3.3 nH IND ID=L2 L =1 2 nH CAP ID=C4 C=2 2 pF P ORT P =2 Z=50 Ohm 1 CAP ID=C2 C=1.5 pF RES ID=R1 R=5.1 Ohm SUB CKT ID=Q1 NET="FP31QF" TL INP ID=TL2 Z0 =50 Ohm L =180 mil Eeff=3 .46 Loss=0 F0 =0 MHz CAP ID=C3 C=1.5 pF Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25C Frequency S21 - Gain S11 - Input Return Loss S22 - Output Return Loss Output P1dB Output IP3 (+18 dBm / tone, 1 MHz spacing) The Communications Edge TM Product Information Reference Design: 3500 MHz The application circuit is matched for output power. Measured S-Parameters 15 10 5 0 (dB) -5 -10 -15 -20 -25 3.3 3.35 3.4 3.45 3.5 3.55 Frequency (GHz) 3.6 3.65 3.7 DB(|S[1,1]|) DB(|S[2,1]|) DB(|S[2,2]|) MHz dB dB dB dBm dBm 3500 11.9 -16 -8.8 +33.5 +45 The 3.5 GHz Reference Circuit is shown for design purposes only. An evaluation board is not readily available for this application. The reader can obtain any FP31QF evaluation board and modify it with the circuit shown to achieve the performance shown in this reference design. Bill of Materials Ref. Desig. C1, C4, C8, C10 C2 C3 C6, C11 C7 C12 L1, L2 L3 R1 R2 Q1 C5 Value 22 pF 0.9 pF 1.0 pF 0.018 F 1000 pF 0.1 F 6.8 nH 3.3 nH 2.2 50 FP31QF Part style Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Wirewound chip inductor Multilayer chip inductor Chip resistor Chip resistor WJ 2W HFET Do Not Place Size 0603 0603 0603 0805 0603 1206 0805 0603 0603 0603 QFN 6x6 C3 C2 Circuit Board Material: .014" FR-4 (r = 4.6), 4 layers (other layers added for rigidity), .062" total thickness, 1 oz copper The main microstrip line has a line impedance of 50 . * Both the C2 and C3 placements are between the first and second via locations along the main microstrip line leading from the FP31QF device. Further descriptions are shown in the diagram on the left. * The via hole spacing along the main microstrip line is .040". * The distance from the edge of the FP31QF to the closer edge of L3 is .305". * The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CA P CA P CAP ID =C7 ID=C6 ID=C8 C=2 2 pF C =100 0 pF C=1.8e 4 pF -Vgg Vds=9V @ 450 mA CAP ID=C12 C=1e 5 pF RES ID=R2 R=51 Ohm CAP ID=C11 C=1.8e 4 pF CAP ID =C10 C =2 2 pF CAP ID=C5 C=DNP pF TL INP ID=TL1 Z0 =50 O hm L =30 mil Eeff=3.46 Loss=0 F0 =0 MHz IND ID=L1 L =6.8 nH 2 P ORT P =1 Z=50 Ohm CAP ID=C1 C=2 2 pF IND ID=L3 L =3.3 nH IND ID=L2 L =6.8 nH CAP ID=C4 C=2 2 pF P ORT P =2 Z=50 Ohm 1 RES I D=R1 R =2.2 O hm CAP ID=C2 C=0.9 pF SUB CKT ID=Q1 NET="FP31QF" TL INP ID=TL2 Z0 =50 Ohm L =65 mil Eeff=3 .46 Loss=0 F0 =0 MHz CAP ID=C3 C=1 pF Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Special attention should be taken to properly bias the FP31QF. Power supply sequencing is required to prevent the device from operating at 100% Idss for a prolonged period of time and possibly causing damage to the device. It is recommended that for the safest operation, the negative supply be "first on and last off." With a negative gate voltage present, the drain voltage can then be applied to the device. The gate voltage can then be adjusted to have the device be used at the proper quiescent bias condition. An optional active-bias current mirror is recommended for use with the application circuits shown this datasheet. Generally in a laboratory environment, the gate voltage is adjusted until the drain draws the recommended operating current. The gate voltage required can vary slightly from device to device because of device pinchoff variation, while also varying slightly over temperature. The active-bias circuit, shown on the right, uses dual PNP transistors to provide a constant drain current into the FP31QF, while also eliminating the effects of pinchoff variation. This configuration is best suited for applications where the intended output power level of the amplifier is backed off at least 6 dB away from its compression point. With the implementation of the circuit, lower P1dB values may be measured for a Class-AB amplifier, where the device will attempt to source more drain current while the circuit tries to provide a constant drain current. The circuit should be connected directly in line with where the voltage supplies would be normally connected with the amplifier circuit, as shown the diagram. Any required matching circuitry remains the same, although it is not shown in the diagram. This recommended active-bias constant-current circuit adds 7 components to the parts count for implementation, but should cost only an extra $0.144 to realize ($0.10 for U1, $0.0029 for R1, R3, R4, R5, $0.024 for R2, and $0.0085 for C1). Temperature compensation is achieved by tracking the voltage variation with the temperature of the emitter-to-base junction of the two PNP transistors. As a 1st order approximation, this is achieved by using matched transistors with approximately the same Ibe current. Thus the transistor emitter voltage adjusts the HFET gate voltage so that the device draws a constant current, regardless of the temperature. A Rohm dual transistor - UMT1N - is recommended for cost, minimal board space requirements, and to minimize the variation between the two transistors. Minimizing the variability between the base-to-emitter junctions allow more accuracy in setting the current draw. More details can be found in a separate application note "Active-bias Constant-current Source Recommended for HFETs" found on the WJ website. The Communications Edge TM Product Information Application Note: Constant-Current Active-Biasing +Vdd R1 R2 U1 4 Rohm UMT1N 1 2 5 C1 .01 F 3 6 R4 1 k R3 R5 RF IN M.N. RF OUT DUT M.N. -Vgg HFET Application Circuit Parameter Pos Supply, Vdd Neg Supply, Vgg Vds Ids R1 R2* R3 R4 R5 FP31QF +9 V -5 V +8.75. V 450 mA 62 0.56 2 k 1 k 1 k *R2 should be of size 1206 to dissipate 0.113 Watts. This should be of 1% tolerance. Two 1.1 resistors in parallel of size 0805 can also be used. Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET The Communications Edge TM Product Information FP31QF Mechanical Information This package may contain lead-bearing materials. The plating material on the pins is SnPb. Outline Drawing Product Marking The component will be lasermarked with a "FP31QF" product label with an alphanumeric lot code on the top surface of the package. Tape and reel specifications for this part will be located on the website in the "Application Notes" section. ESD / MSL Information ESD Rating: Value: Test: Standard: ESD Rating: Value: Test: Standard: Class 1C Passes 1000V to <2000V Human Body Model (HBM) JEDEC Standard JESD22-A114 Class IV Passes 1000V Charged Device Model (CDM) JEDEC Standard JESD22-C101 Mounting Configuration / Land Pattern MSL Rating: Level 1 at +250C convection reflow Standard: JEDEC Standard J-STD-020 Functional Pin Layout Pin 3 19 FUNCTION Gate / RF Input Drain / RF Output The backside paddle is the Source and should be grounded for thermal and electrical purposes. All other pins should be grounded on the PCB. Thermal Specifications Parameter Operating Case Temperature Thermal Resistance, Rth (1) Junction Temperature, Tjc (2) MTTF vs. GND Tab Temperature 100 Rating -40 to +85C 17.5 C/W 156 C 10 1. The thermal resistance is referenced from the hottest part of the junction to the ground copper on the backside. 2. This corresponds to the typical drain biasing condition of +9V, 450 mA at an 85C case temperature. A minimum MTTF of 1 million hours is achieved for junction temperatures below 160 C. 1 0 60 70 80 90 100 Tab Temperature (C) 110 120 Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 FP31QF 2-Watt HFET The Communications Edge TM Product Information FP31QF-F Mechanical Information This package is lead-free/RoHS-compliant. It is compatible with both lead-free (maximum 260C reflow temperature) and leaded (maximum 245C reflow temperature) soldering processes. The plating material on the pins is annealed matte tin over copper. Outline Drawing Product Marking The component will be lasermarked with a "FP31QFF" product label with an alphanumeric lot code on the top surface of the package. Tape and reel specifications for this part will be located on the website in the "Application Notes" section. ESD / MSL Information ESD Rating: Value: Test: Standard: ESD Rating: Value: Test: Standard: Class 1C Passes 1000V to <2000V Human Body Model (HBM) JEDEC Standard JESD22-A114 Class IV Passes 1000V Charged Device Model (CDM) JEDEC Standard JESD22-C101 Mounting Configuration / Land Pattern MSL Rating: Level 2 at +260C convection reflow Standard: JEDEC Standard J-STD-020 Functional Pin Layout Pin 3 19 FUNCTION Gate / RF Input Drain / RF Output The backside paddle is the Source and should be grounded for thermal and electrical purposes. All other pins should be grounded on the PCB. Thermal Specifications Parameter Operating Case Temperature Thermal Resistance, Rth (1) Junction Temperature, Tjc (2) MTTF vs. GND Tab Temperature 100 Rating -40 to +85C 17.5 C/W 156 C 10 1. The thermal resistance is referenced from the hottest part of the junction to the ground copper on the backside. 2. This corresponds to the typical drain biasing condition of +9V, 450 mA at an 85C case temperature. A minimum MTTF of 1 million hours is achieved for junction temperatures below 160 C. 1 0 60 70 80 90 100 Tab Temperature (C) 110 120 Specifications and information are subject to change without notice WJ Communications, Inc * Phone 1-800-WJ1-4401 * FAX: 408-577-6621 * e-mail: sales@wj.com * Web site: www.wj.com November 2004 |
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