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PRELIMINARY
* PERFORMANCE 20 dBm Output Power (P1dB) 21 dB Power Gain (G1dB) at 1.85 GHz 0.7 dB Noise Figure at 1.85 GHz 30 dBm Output IP3 50% Power-Added Efficiency at 1.85 GHz Useable Gain to 26 GHz Evaluation Boards Available
FPD200P70
HI-FREQUENCY PACKAGED PHEMT
GATE LEAD IS ANGLED
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DESCRIPTION AND APPLICATIONS The FPD200P70 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 200 m Schottky barrier Gate, defined by high-resolution stepper-based photolithography. . The FPD200P70 is also available in die form . Typical applications include gain blocks and medium power stages for applications to 26 GHz.
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ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Gain at 1dB Gain Compression Power-Added Efficiency Maximum Stable Gain (S21/S12) f = 12 GHz f = 18 GHz Noise Figure Output Third-Order Intercept Point POUT = 9 dBm SCL Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| JC VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.2 mA IGS = 0.2 mA IGD = 0.2 mA VDS > 3V 0.7 12 14.5 45 60 120 80 1 0.9 14 16 325 10 1.3 75 mA mA mS A V V V C/W NF IP3 VDS = 5 V; IDS = 25% IDSS VDS = 5V; IDS = 50% IDSS Symbol P1dB SSG PAE MSG Test Conditions VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS; POUT = P1dB VDS = 5 V; IDS = 50% IDSS 15 11 0.7 30 dB dBm Min Typ 20 21 45 Max Units dBm dB % RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL (except as noted)
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtrionic.co.uk/semis
Revised: 7/15/05 Email: sales@filcsi.com
PRELIMINARY
* ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
FPD200P70
HI-FREQUENCY PACKAGED PHEMT
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3
Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions
Min
Max 8 -3 IDSS 5 60 175
Units V V mA mA mW C C mW dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression
1
-40
150 470 5
Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 470mW - (3mW/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C source lead temperature: PTOT = 470mW - (3 x (65 - 22)) = 341mW
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HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (< 250V) per JESD22-A114-B, Human Body Model, and Class A (< 200V) per JESD22-A115-A, Machine Model. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.
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Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtrionic.co.uk/semis
Revised: 7/15/05 Email: sales@filcsi.com
PRELIMINARY
FPD200P70
HI-FREQUENCY PACKAGED PHEMT
*
BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD200P70. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT
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(DIMENSIONS IN mm)
All information and specifications subject to change without notice.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtrionic.co.uk/semis
Revised: 7/15/05 Email: sales@filcsi.com

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