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GENLINX TMII GS9025A
Serial Digital Receiver
PRELIMINARY DATA SHEET FEATURES * SMPTE 259M compliant * operational to 540Mb/s * automatic cable equalization (typically greater than 350m of high quality cable at 270Mb/s) * adjustment-free operation * auto-rate selection (5 rates) with manual override * single external VCO resistor for operation with five input data rates * data rate indication output * serial data outputs muted and serial clock remains active when input data is lost * operation independent of SAV/EAV sync signals * signal strength indicator output * carrier detect with programmable threshold level * power savings mode (output serial clock disable) APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M and other data standards. DESCRIPTION The GS9025A provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS9025A receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. The GS9025A operates in either auto or manual data rate selection mode. In both modes, the GS9025A requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS9025A has dedicated pins to indicate signal strength/carrier detect, LOCK and data rate. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS9025A provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also be disabled to reduce power. The GS9025A operates from a single +5 or -5 volt supply. ORDERING INFORMATION
PART NUMBER GS9025ACQM GS9025ACTM PACKAGE 44 pin MQFP Tray 44 pin MQFP Tape TEMPERATURE 0C to 70C 0C to 70C
GS9025A
A/D DDI DDI ANALOG DIGITAL MUX CARRIER DETECT PHASELOCK HARMONIC
COSC LOCK LOGIC MUTE SDO
SDI SDI
+ -
VARIABLE GAIN EQ STAGE
FREQUENCY ACQUISITION PHASE DETECTOR
SDO CLK_EN SCO SCO
OEM_TEST
EYE MONITOR DIVISION AUTO EQ CONTROL CHARGE PUMP 3 BIT COUNTER SMPTE AUTO/MAN SS0 SS1 SS2
+ AGC CAP CD_ADJ SSI/CD
VCO
DECODER
LF+ LFS LF-
CBG RVCO
BLOCK DIAGRAM
Revision Date: June 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 75 - 00
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VCC + 0.5 to VEE - 0.5V 0C TA 70C
GS9025A
-65C TS 150C 260C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Supply Voltage Supply Current
CONDITION
MIN 4.75
TYPICAL 5 115 125 2.5
1
MAX 5.25
UNITS V mA
NOTES
TEST LEVEL 1 1
CLK_EN = 0 CLK_EN = 1
VEE+(VDIFF/2) 200
SDI Common Mode Voltage DDI Common Mode Input Voltage Range DDI Differential Input Drive SSI/CD Output Current Source, CLMAX = 50pF, RL = open cct. Source, CLMAX = 50pF, RL=5K Sink AGC Common Mode Voltage OEM_TEST Bias Potential A/D, AUTO/MAN, SMPTE, SS[2:0] Input Voltage CLK_EN Input Voltage High Low High Low LOCK Output Sink Current SS[2:0] Output Voltage High Low SS[2:0] Source Current SS[2:0] Sink Current SS[2:0] Source Current Auto Mode Auto Mode Manual Mode
VCC-(VDIFF/2) 2000 18
V V 2
1 1
0.4 to 4.6
800 -
mV A
1 3
-
-
-
110
A
3
2.0 2.5 500 4.4 180 0.6 -
1.0 2.7 4.5 4.7 0.2 300 1.0 0
1.5 0.8 0.8 0.4 -
mA V V V 5
3 1 1 1
V
1
A V
3
1 1
A mA A 4
1
1
2
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DC ELECTRICAL CHARACTERISTICS (continued)
VCC = 5.0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER SS[2:0] Sink Current CLK_EN Source Current NOTES
CONDITION Manual Mode Low
MIN -
TYPICAL 0.8 26
1
MAX 5 55
UNITS A A
NOTES
TEST LEVEL
1
GS9025A
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
1. TYPICAL - measured on EB9025A board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pullup resistor. 4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode. 5. If OEM_TEST is permanently enabled, operating temperature range is limited from 0C to 60C inclusive.
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Serial Data Rate Maximum Equalizer Gain Additive Jitter [Pseudorandom (2
23
CONDITIONS SDI @ 200MHz 270Mb/s, 300m (Belden 8281) 540Mb/s, 100m (Belden 8281)
MIN 143 -
TYPICAL 40 300
1
MAX 540 -
UNITS Mb/s dB ps p-p
NOTES
TEST LEVEL 1 7
2, 8
3
-1)]
-
275
-
Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter [Pathological (SDI checkfield)]
23
270Mb/s -1)] 540Mb/s 270Mb/s 360Mb/s 540Mb/s
0.40 0.35 -
185 164 462 308 260 0.56 0.43 1 1 4 10
see Figure 12
ps p-p
2, 7
4
see Figure 13
ps p-p
2, 7
1
Input Jitter Tolerance
270Mb/s 540Mb/s
-
UI p-p
3, 7
1
Lock Time Synchronous Switch
tswitch < 0.5s, 270Mb/s 0.5s< tswitch <10ms tswitch > 10 ms
s ms ms ms
4
7
Lock Time Asynchronous Switch Carrier Loss Time SDO to SCO Synchronization
Loop Bandwidth = 6MHz @ 540Mb/s
5
7
0.5 -200
1 0
2 200
s ps
6
7 7
3
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AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER SDO, SCO Output Signal Swing SDO, SCO Rise & Fall times SDI/SDI Input Resistance SDI/SDI Input Capacitance SDI/SDI Input Return Loss Carrier Detect Response Time
CONDITIONS 75 DC load
MIN 600
TYPICAL 800
1
MAX 1000
UNITS mV p-p
NOTES
TEST LEVEL 1
GS9025A
20%-80%
200 -
300 10 1.0 20 3
400 -
ps k pF dB s 8 8 8 8
7 6 6 6 6
at 270MHz Carrier Applied, CL<50pF, RL=open cct. Carrier Removed, CL<50pF, RL=open cct.
15 -
-
30
-
NOTES 1. TYPICAL - measured on EB9025A board. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). 5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 6. Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. 7. Using the DDI input, A/D=0. 8. Using the SDI input, A/D=1.
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER
BELDEN 8281 CABLE
EB9025A BOARD
TEKTRONIX GigaBERT 1400 ANALYZER TRIGGER
CLOCK
Fig. 1 Test Setup for Figures 6 - 13
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PIN CONNECTIONS
OEM_TEST
VCC_75
SMPTE
SSI/CD
LOCK
COSC
CLK_EN
44 DDI DDI VCC_75 VCC VEE SDI SDI VCC VEE CD_ADJ AGC1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
A/D
40
39
38 37
36
35 34 33 32 31 30 VEE SDO SDO VEE SCO SCO VEE AUTO/MAN SS0 SS1 SS2
VCC
VEE
VEE
GS9025A
GS9025A
TOP VIEW
29 28 27 26 25 24 23
13
14
15
16
17
18 19
20
21 22
AGC+
LFS
LF-
CBG
VCC
VEE
LF+
PIN DESCRIPTIONS
NUMBER 1, 2 3, 44 4, 8, 13, 22, 35 5, 9, 14, 18, 27, 30, 33, 34, 37 6, 7 10 11, 12 15 16 17 19 20 21 23, 24, 25 SYMBOL DDI/DDI VCC_75 VCC VEE SDI/SDI CD_ADJ AGC-, AGC+ LF+ LFS LFRVCO_RTN RVCO CBG SS[2:0] TYPE I I I I DESCRIPTION Digital data inputs (Differential ECL/PECL). Power supply connection for internal 75 pullup resistors connected to DDI/DDI. Most positive power supply connection. Most negative power supply connection.
I I I I I I I I I I/O
Differential analog data inputs. Carrier detect threshold adjust. External AGC capacitor. Loop filter component connection. Loop filter component connection. Loop filter component connection. Frequency setting resistor return connection. Frequency setting resistor connection. Internal bandgap voltage filter capacitor. Data rate indication (auto mode) or data rate select (manual mode). TTL/CMOS compatible I/O. In auto mode, these pins can be left unconnected. Auto or manual mode select. TTL/CMOS compatible input.
26
AUTO/MAN
I
5
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RVCO_RTN
RVCO
VCC
VEE
PIN DESCRIPTIONS (continued)
NUMBER 28, 29 SYMBOL SCO/SCO TYPE O DESCRIPTION Serial clock output. SCO/SCO are differential current mode outputs and require external 75 pullup resistors. Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75 pullup resistors.
31, 32
SDO/SDO
O
GS9025A
36 38 39
CLK_EN COSC LOCK
I I O
Clock enable. When HIGH, the serial clock outputs are enabled. Timing control capacitor for internal system clock. Lock indication. When HIGH, the GS9025A is locked. LOCK is an open collector output and requires an external 10k pullup resistor. Signal strength indicator/Carrier detect. Analog/Digital select. SMPTE/Other data rate select. TTL/CMOS compatible input. Output `Eye' monitor test. Single-ended current mode output that requires an external 50 pullup resistor. This feature is recommended for debugging purposes only. If enabled during normal operation, the maximum operating temperature is rated to 60C.
40 41 42 43
SSI/CD A/D SMPTE OEM_TEST
O I I O
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TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25C unless otherwise shown)
j1 j0.5 j2
j0.2
5.00
j5
GS9025A
SSI/CD OUTPUT VOLTAGE (V)
4.50 270 4.00 3000 1620
3.50
-j0.2
-j5
810
3.00
-j0.5
2.50 0 50 100 150 200 250 300 350 400 450 500
-j2
CABLE LENGTH (m)
-j1 Frequencies in MHz, impedances normalized to 50
Fig. 2 SSI/CD Voltage vs. Cable Length (Belden 8281) (CD_ADJ = 0V)
50 45 40 450 400 350
Fig. 5 Input Impedance
(Characterized)
540Mb/s
30 25 20 15 10 5 0 1 10 100 1000
JITTER (ps p-p)
35
300 250 200 150 100 50 0 0 50 100 150 200 250
GAIN (dB)
270Mb/s
300
350
400
FREQUENCY (MHz)
CABLE LENGTH (m)
Fig. 3 Equalizer Gain vs. Frequency
Fig. 6 Typical Additive Jitter vs. Input Cable Length (Belden 8281) Pseudorandom (2 -1)
23
5.0
450
4.5
400
CD_ADJ VOLTAGE (V)
CABLE LENGTH (m)
4.0
350
3.5
300
3.0
250
200 2.5 150 2.0 200 250 300 350 400 100 200 300 400 500 600
CABLE LENGTH (m)
DATA RATE (Mb/s)
Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics
Fig. 7 Typical Error Free Cable Length
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GS9025A
Fig. 8 Intrinsic Jitter (2
23
- 1 Pattern) 30Mb/s
Fig. 11 Intrinsic Jitter (2
23
- 1 Pattern) 540Mb/s
2000 1800 1600 1400
JITTER (ps)
1200 1000 800 QA Output Jitter Limit, Sample Tested 600 Typical Range, Characterized 400 200 0 100 200 300 400 500 Max Typical Min 600
SDI DATA RATE (Mb/s)
TA=0 to 70C, VCC=4.75 to 5.25V for the typical range
Fig. 9 Intrinsic Jitter (2
23
- 1 Pattern) 143Mb/s
Fig. 12 Intrinsic Jitter - Pseudorandom (2
23
- 1)
2000 1800 1600 1400
JITTER (ps p-p)
1200 QA Output Jitter Limit, Sample Tested 1000 800 600 400 200 Typical Range, Characterized 0 100 200 300 400 500 600 Max Typical Min
SDI DATA RATE (Mb/s)
TA = 0 to 70C, VCC = 4.75 to 5.25V for the typical range
Fig. 10 Intrinsic Jitter (2
23
- 1 Pattern) 270Mb/s
Fig. 13 Intrinsic Jitter - Pathological SDI Checkfield
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GENNUM CORPORATION 522 - 75 - 00
0.6
0.5
0.4
0.3
signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its corrective level irrespective of shifts due to AC coupling.
1-1. Signal Strength Indication/carrier Detect
IJT (UI)
GS9025A
0.2
0.1
0
100
200
300
400
500
600
DATA RATE (Mb/s)
TA = 0 to 70C, VCC = 4.75 to 5.25V
Fig. 14 Typical Input Jitter Tolerance (Characterized)
0.600 143Mb/s 0.550 0.500 0.450 177Mb/s 270Mb/s 360Mb/s
IJT (UI)
0.400 0.350 0.300 0.250 0.200
540Mb/s
0
10
20
30
40
50
60
70
The GS9025A incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure 2 and Figure 16. With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length.
5
TEMPERATURE (C)
Fig. 15 Typical IJT vs. Temperature (VCC = 5.0V) (Characterized)
DETAILED DESCRIPTION The GS9025A Serial Digital Receiver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker.
SSI/CD OUTPUT VOLTAGE (V)
Serial digital signals are applied to either the analog SDI/SDI or digital DDI/DDI inputs. Signals applied to the SDI/SDI inputs are equalized and then passed to a multiplexer. Signals applied to the DDI/DDI inputs bypass the equalizer and go directly to the multiplexer. The analog/digital select pin (A/D) determines which signal is then passed to the reclocker. Packaged in a 44 pin MQFP, the receiver operates from a single 5V supply to data rates of 540Mb/s. Typical power consumption is 575mW.
1. CABLE EQUALIZER
4
3 CD_ADJ CONTROL RANGE 2
1
0
0
50
100
150
200
250
300
350
400
450
500
CABLE LENGTH (m)
The automatic cable equalizer is designed to equalize serial digital data signals from 143Mb/s to 540Mb/s. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single-ended. The input 9
GENNUM CORPORATION
Fig. 16 SSI/CD Voltage vs. Cable Length
When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8 V) and can be used to drive
522 - 75 - 00
other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected, the SDO/SDO outputs are muted (set to a known static state).
1-2. Carrier Detect Threshold Adjust
SDO
This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. To alleviate this problem, the GS9025A provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings have also been provided to give the user total flexibility. The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin. The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit (see Typical Application Circuit). The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. In noisy environments, it is not recommended to leave this pin floating. Connecting this pin to VEE disables the SDO/SDO muting function and allows for maximum possible cable length equalization.
1-3. Output Eye Monitor Test
SCO
GS9025A
50%
Fig. 17 Output and Clock Signal Timing
The reclocker contains four main functional blocks: the Phase Locked Loop, Auto/Manual Data Rate Select, Frequency Acquisition, and Logic Circuit.
2-1. Phase Locked Loop (PLL)
The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter.
2
DDI/DDI
PHASE DETECTOR INTERNAL PLL CLOCK DIVISION
The GS9025A also provides an 'Output Eye Monitor Test' (OEM_TEST) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM_TEST pin is an open collector current output that requires an external 50 pullup resistor. When the pullup resistor is not used, the OEM_TEST block is disabled and the internal OEM_TEST circuit is powered down. The OEM_TEST provides a 100mVp-p signal when driving a 50 oscilloscope input. Due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation.
2. RECLOCKER
CHARGE PUMP LF+ LFS LF-
VCO
RVCO LOOP FILTER
RLF CLF1 CLF2
Fig. 18 Simplified Block Diagram of the PLL 2-2. VCO
The reclocker receives a differential serial data stream from the internal multiplexer. It locks an internal clock to the incoming data. It outputs the differential PECL retimed data signal on SDO/SDO. It outputs the recovered clock on SCO/ SCO. The timing between the output and clock signals is shown in Figure 17.
The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO operates between 30 and 540Mb/s and has a pull range of 15% about the centre frequency. A single low impedance external resistor, RVCO, sets the VCO centre frequency (see Figure 19). The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. For a given RVCO value, the VCO can oscillate at one of two frequencies. When SMPTE = SS0 = logic 1, the VCO centre frequency corresponds to the L curve. For all other SMPTE/SS0 combinations, the VCO centre frequency corresponds to the H curve (H is approximately 1.5 x L).
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800 700
for SMPTE 259M applications where pathological signals have data transition densities of 0.05.
2-5. Loop Filter
VCO FREQUENCY (MHz)
600 500 400 300 200 100 00 200 400 600
H
L
SMPTE=1 SSO=1
The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS9025A increased immunity to PCB board noise.
1000 1200 1400 1600 1800
GS9025A
800
RVCO ()
Fig. 19 RVCO vs. VCO Centre Frequency
The recommended RVCO value for auto rate SMPTE 259M applications is 365. The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143Mb/s to 540Mb/s. The divider modulus is set by the AUTO/MAN, SMPTE, and SS[2:0] pins (for further details, see section 4, Auto/Manual Data Rate Select). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30Mb/s. When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the previously locked frequency to the limits shown in Table1.
TABLE 1: Frequency Drift Range (when PLL loses lock) LOSES LOCK FROM 143Mb/s lock 177Mb/s lock 270Mb/s lock 360 Mb/s lock 540 Mb/s lock MIN (%) -21 -12 -13 -13 -13 MAX(%) 21
The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL DESIGN GUIDELINES section. Recommended values for SMPTE259M applications are shown in the Typical Application Circuit.
3. FREQUENCY ACQUISITION
The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock to data rates outside of the capture range, the GS9025A uses a frequency acquisition circuit. The frequency acquisition circuit sweeps the VCO control voltage so that the VCO frequency changes from -10% to +10% of the centre frequency. Figure 20 shows a typical sweep waveform.
tswp tsys
VLF
A
26
Tcycle
28 24
Tcycle = tswp + tsys
Fig. 20 Typical Sweep Waveform 28
2-3. Phase Detector
The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the PLL.
2-4. Charge Pump
The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. In manual mode, the divider modulus is fixed for all cycles. In auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter.
The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. This makes the GS9025A ideal
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The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, CP: 4C LF1 t SWP = ---------------3I CP The nominal sweep time is approximately 121s when CLF1 = 15nF and CP = 165A (RVCO = 365). An internal system clock determines tsys (see section 3-1, Logic Circuit).
3-1. Logic Circuit
TABLE 2. AUTO/MAN = 1 (AUTO MODE) H, L = VCO centre frequency as per Figure 19. SMPTE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SS[2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 DIVIDER MODULI 4 2 2 1 1 4 4 2 2 1 PLL CLOCK H/4
GS9025A
L/2 H/2 L H H/4 H/4 H/2 H/2 H -
The GS9025A is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: t sys = 9.6 x 10 x C OSC [ sec onds ] The recommended value for tsys is 450s (COSC = 4.7nF)
4. AUTO/MANUAL DATA RATE SELECT
4
0
The GS9025A can operate in either auto or manual data rate select mode. The mode of operation is selected by a single input pin (AUTO/MAN).
4-1. Auto Mode (AUTO/MAN = 1)
TABLE 3. AUTO/MAN = 1 (MANUAL MODE) H, L = VCO centre frequency as per Figure 19. SMPTE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SS[2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 DIVIDER MODULI 4 2 2 1 1 8 8 4 4 2 2 1 1 8 PLL CLOCK H/4 L/2 H/2 L H L/8 H/8 H/4 H/4 H/2 H/2 H H H/8 -
In auto mode, the GS9025A uses a 3-bit counter to automatically cycle through five (SMPTE=1) or three (SMPTE=0) different divider moduli as it attempts to acquire lock. In this mode, the SS[2:0] pins are outputs and indicate the current value of the divider moduli according Table 2. NOTE: For SMPTE = 0 and divider moduli of 2 and 4, the PLL can correctly lock for two values of SS[2:0].
4-2. Manual Mode (AUTO/MAN = 0)
In manual mode, the GS9025A divider moduli is fixed. In this mode, the SS[2:0] pins are inputs and set the divider moduli according to Table 3.
5. LOCKING
The GS9025A indicates lock when three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked. 3. The system is not locked to a harmonic.
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The GS9025A defines the presence of input data when at least one data transition occurs every 1s. The GS9025A assumes that it is NOT locked to a harmonic if the pattern `101' or `010' (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150s. In a harmonically locked system, all bit cells are double clocked and the above patterns become `110011' and `001100', respectively.
5-1. Lock Time
6. OUTPUT DATA MUTING
The GS9025A internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 21.
NO DATA TRANSITIONS
GS9025A
DDI
The lock time of the GS9025A depends on whether the input data is switching synchronously or asynchronously. Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). Asynchronous switching refers to the case where the input data is changed from one source to another source which is at a different data rate. When input data to the GS9025A is removed, the GS9025A latches the current state of the counter (divider modulus). Therefore, when data is reapplied, the GS9025A begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS9025A locks very quickly. The nominal lock time depends on the switching time and is summarized in the Table 4.
TABLE 4. SWITCHING TIME <0.5s 0.5s - 10ms >10ms LOCK TIME 10s 2tsys 2Tcycle + 2tsys
LOCK
SDO
VALID DATA
OUTPUTS MUTED
VALID DATA
Fig. 21 Output Data Muting Timing 7. CLOCK ENABLE
When CLK_EN is high, the GS9025A SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are tri-stated and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC.
8. STRESSFULL DATA PATTERNS
In asynchronous switching applications, including power up, the lock time is determined by the frequency acquisition circuit (see section 3, Frequency Acquisition Circuit). To acquire lock in manual mode, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys. To acquire lock in auto tune mode, the frequency acquisition circuit may have to cycle through 5 possible counter states depending on initial conditions. Maximum lock time is 6Tcycle + 2tsys. The nominal value of Tcycle for the GS9025A operating in a typical SMPTE 259M application is approximately 1.3ms. The GS9025A has a dedicated LOCK output (pin 39) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5s, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted. 13
GENNUM CORPORATION
All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). The GS9025A is designed to operate with low data transition densities such as the SMPTE 259M pathological signal (data transition density = 0.05).
9. PLL DESIGN GUIDELINES
The reclocking performance of the GS9025A is primarily determined by the PLL. Thus, it is important that the system designer is familiar with the basic PLL design equations. A model of the GS9025A PLL is shown in Figure 22. The main components are the phase detector, the VCO, and the external loop filter components.
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PHASE DETECTOR Oi + KPD LOOP FILTER RLF CLF1 CLF2 CP VCO Oo AMPLITUDE 2 K Ns
GS9025A
Fig. 22 Model of the GS9025A 9-1. Transfer Function
WZ
WP1
WBW
WP2
FREQUENCY
The transfer function of the PLL is defined as Oo/Oi and can be approximated as: sC LF1 R LF + 1 Oo 1 ------ = --------------------------------------------------------------- --------------------------------------------------------L L 2 Oi C s LF1 R LF - --------- + 1 s C LF2 L + s --------- + 1 R LF R LF
Equation 1
Fig. 23 Transfer Function Bode Plot
The 3dB bandwidth approximately:
of
the
transfer
function
is
where
N L = ------------------DICP K
and
w BW wBW w 3dB = --------------------------------------------------------------------- ----------2 0.78 w BW ( w BW w P2 ) 1 - 2 ----------- + --------------------------------w P2 w BW 1 - 2 ----------wP2
N is the divider modulus D is the data density (=0.5 for NRZ data) ICP is the charge pump current in amps K is the VCO gain in Hz/V This response has (wP1,wBW,wP2) where: 1 zero (wZ) and three poles
9-2. Transfer Function Peaking
There are two causes of peaking in the PLL transfer function given by Equation 1. The first is quadratic: L 2 s C LF2 L + s --------- + 1 R LF which has:
1 w Z = ---------------------C LF1 R LF 1 w P1 = -------------------------------------L C LF1 R LF - --------R LF RLF w BW = --------L 1w P2 = ---------------------C LF2 RLF The bode plot for this transfer function is plotted in Figure 23.
1 w o = -------------------C LF2 L
R LF2 Q = R LF ----------L and
This response is critically damped for Q = 0.5. Thus, to avoid peaking: CLF2 1 R LF ------------ < --2 L Therefore, wP2 > 4 wBW To reduce the high frequency content on the loop filter, keep wP2 as low as possible. The second is the zero-pole combination: s ------ + 1 sC LF1 R LF + 1 wZ --------------------------------------------------------- = ------------------s1 --------- + 1 s C LF1 RLF - --------- + 1 w P1 R LF 14 L 1 ------------------------- --------- > 4 R LF2 C LF2 RLF
or
GENNUM CORPORATION
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This causes lift in the transfer function given by: w P1 1 20 LOG --------- = 20 LOG --------------------wZ wZ 1 - ----------w BW To keep peaking to less than 0.05dB: wZ < 0.0057wBW
9.3 Selection of Loop Filter Components
9-4. SPICE Simulations
More detailed analysis of the GS9025A PLL can be done using SPICE. A SPICE model of the PLL is shown below:
PHII IN+ INRLF 1 CLF1 R2
G1 LF PHIO E1 2 K Ns
GS9025A
V1
Based on the above analysis, the loop filter components should be selected for a given PLL bandwidth, 3dB, as follows: 1. Calculate 2N L = -------------ICP K where: ICP is the charge pump current and is a function of the RVCO resistor and is obtained from Figure 24. K = 90MHz/V for VCO frequencies corresponding to the L curve. K = 140MHz/V for VCO frequencies corresponding to the H curve. N is the divider modulus (L, H and N can be obtained from Table 2 or Table 3) 2. Choose RLF = 2(3.14)3dB(0.78)L 3. Choose CLF1 = 174L/(RLF) 4. Choose CLF2 = L/4(RLF)
400
CLF2
NOTE: PHII, PHIO, LF, and 1 are node names in the SPICE netlist.
Fig. 25 SPICE Model of the PLL
The model consists of a voltage controlled current source (G1), the loop filter components (RLF, CLF1, and CLF2), a voltage controlled voltage source (E1), and a voltage source (V1). R2 is necessary to create a DC path to ground for Node 1. V1 is used to generate the input phase waveform. G1 compares the input and output phase waveforms and generates the charge pump current, CP. The loop filter components integrate the charge pump current to establish the loop filter voltage. E1 creates the output phase waveform (PHIO) by multiplying the loop filter voltage by the value of the Laplace transform (2K/Ns). The net list for the model is given below. The .PARAM statements are used to set values for CP, K, N, and D. CP is determined by the RVCO resistor and is obtained from Figure 24.
2
2
350 300 250 200 150 100 50 0
0
200
400
600
800
1000
1200
1400
1600
1800
RVCO ()
Fig. 24 RVCO vs. Charge Pump Current
SPICE NETLIST * GS9025A PLL Model .PARAM ICP = 165E-6 KF= 90E+6 .PARAM N = 1 D = 0.5 .PARAM PI = 3.14 .IC V(Phio) = 0 .ac dec 30 1k 10meg RLF 1 LF 1000 CLF1 1 0 15n CLF2 0 LF 15p E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)} G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)} V1 2 0 DC 0V AC 1V R2 0 1 1g .END
CHANGE PUMP CURRENT (A)
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10. I/O DESCRIPTION
RSOURCE ZO DDI RLOAD DDI ZO GS9025
10-1. High Speed Analog Inputs (SDI/SDI)
SDI/SDI are high impedance inputs differential or single-ended input drive.
which
accept
RSOURCE
Figure 26 shows the recommended interface when a singleended serial digital signal is used.
75 75 113 10nF SDI 10nF GS9025 SDI
Fig. 28
Figure 29 shows the recommended interface when the GS9025A digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used.
DDI
GS9025A
Fig. 26 10-2. High Speed Digital Inputs (DDI/DDI)
ZO DDI
GS9025
DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: 1. Input signal amplitudes are between 200 and 2000 mV 2. The common mode input voltage range is as specified in the DC Characteristics table. Commonly used interface examples are shown in Figures 27 to 29. Figure 27 illustrates the simplest interface to the GS9025A digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry.
Fig. 29
When the DDI and the DDI inputs are not used, saturate one input of the differential amplifier for improved noise immunity. To saturate, connect either pins 44 and 1 or pins 2 and 3 to VCC. Leave the other pair floating.
10-3. High Speed Outputs (SDO/SDO and SCO/SCO)
SDO/SDO and SCO/SCO are current mode outputs that require external pullups (see Figure 30). The output signal swings are 800mV when 75 resistors are used. To shift the signal levels down by approximately 0.7 volts, place a diode between VCC and the pullups. When the output traces are longer than 1in, use controlled impedance traces. Place the pullup resistors at the end of the output traces as they terminate the trace in its characteristic impedance (75).
VCC
DDI DDI
GS9025 SDO SDO GS9025 SCO SCO
75
75
Fig. 27
75 VCC
75
When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 29. In this case, a parallel resistor (RLOAD) is placed near the GS9025A inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. In addition, place series resistors (RSOURCE) near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100, RSOURCE = 50 and ZO = 50.
Fig. 30
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TYPICAL APPLICATION CIRCUIT
VCC VCC VCC VCC 10k
4.7n VCC VCC VCC VCC
44
43
42
41
40
39
38
37
36
35
34
GS9025A
OEM_TEST
SMPTE
SSI/CD
LOCK
A/D
CLK_EN
VCC
VCC_75
COSC
VEE
VEE
From GS9024 see Note 1 VCC VCC
1 2 3 4 5 6
DDI DDI
VEE SDO SDO VEE
33 32 31 30 29 28 27 26 25 24 23
4 x 75 see Note 2
VCC_75 VCC VEE SDI SDI VCC VEE RVCO_RTN CD_ADJ AGC+ AGC-
To GS9020
GS9025A TOP VIEW
SCO SCO VEE AUTO/MAN SS0 SS1
RVCO
75
75 37.5 VCC
10n
7
75 10n VCC
8 9 10 11
VCC
100k Pot (Optional)
SS2
CBG VCC
}
To LED Driver (optional)
VCC
VEE
LF+
LFS
12 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. Power supply decoupling capacitors are not shown.
13
14
15
16
17
18
VEE
LF-
19
20
21
22
0.1
VCC
1.8k 15n 3.3p
365 (1%)
VCC 0.1 0.1
NOTES 1. It is recommended that the DDI/DDI inputs are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used.
TABLE 5. RVCO = 365, H = 540MHz, L = 360MHz SMPTE 1 1 1 1 1 SS[2:0] 000 001 010 011 100 DATA RATE (Mb/s) 143 177 270 360 540 LOOP BANDWIDTH (MHz) 1.2 1.9 3.0 4.5 6.0
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PACKAGE DIMENSIONS
13.20 0.25 10.00 0.10
GS9025A
13.20 0.25 10.00 0.10
PIN 1
0.80 BSC
0.45 MAX 0.30 MIN
5 to 16
0.20 MIN 0 MIN 0.3 MAX. RADIUS 7 MAX 0 MIN
2.20 MAX 1.85 MIN 0.23 MAX. All dimensions in millimetres
2.55 MAX 5 to 16 0.13 MIN. RADIUS 1.60 REF 0.88 NOM.
0.35 MAX 0.15 MIN
44 pin MQFP
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice.
REVISION NOTES: New document.
For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright June 2000 Gennum Corporation. All rights reserved. Printed in Canada.
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