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HCS373MS
September 1995
Radiation Hardened Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW
OE Q0 D0 D1 Q1 Q2 D2 D3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 LE
Features
* 3 Micron Radiation Hardened CMOS SOS * Total Dose 200K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s * Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min * Input Current Levels Ii 5A at VOL, VOH
Q3
GND 10
Description
The Intersil HCS373MS is a Radiation Hardened octal transparent three-state latch with an active-low output enable. The HCS373MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS373MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
Ordering Information
PART NUMBER HCS373DMSR HCS373KMSR HCS373D/Sample HCS373K/Sample HCS373HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack DB NA Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
346
518845 2135.2
HCS373MS Functional Diagram
1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) D COMMON CONTROLS LE (11) LATCH OE D Q LE Q (2, 5, 6, 9, 12, 15, 16, 19)
OE (1)
TRUTH TABLE OE L L L L H LE H H L L X D H L I h X Q H L L H Z
H = High Level, L = Low Level X = Immaterial, Z = High Impedance I = Low voltage level prior to the high-to-low latch enable transition h = High voltage level prior to the high-to-low latch enable transition
Spec Number 347
518845
Specifications HCS373MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .100ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, IOH = -50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOH = -50A, VIL = 1.65V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 7.2 6.0 -7.2 -6.0 MAX 40 750 0.1 UNITS A A mA mA mA mA V Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
PARAMETER Quiescent Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC
0.5 5.0 1.0 50
A A A A -
Output Three-State Leakage
IOZ
VCC = 5.5V, VO = 0V or VCC
1 2, 3
Noise Immunity Functional Test
FN
VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 2)
7, 8A, 8B
-
-
NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 348
518845
Specifications HCS373MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 LE to Qn TPLH, TPHL TPZL VCC = 4.5V 9 10, 11 Enable to Output VCC = 4.5V 9 10, 11 TPZH VCC = 4.5V 9 10, 11 Disable to Output TPLZ, TPHZ VCC = 4.5V 9 10, 11 NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. LIMITS TEMPERATURE +25oC +125oC, -55oC +25 C +125oC, -55oC +25 C +125oC, -55oC +25 C +125oC, -55oC +25 C +125oC, -55oC
o o o o
PARAMETER Data to Qn
SYMBOL TPLH, TPHL
(NOTES 1, 2) CONDITIONS VCC = 4.5V
MIN 2 2 2 2 2 2 2 2 2 2
MAX 20 24 24 29 25 31 20 24 25 30
UNITS ns ns ns ns ns ns ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation SYMBOL CPD (NOTE 1) CONDITIONS VCC = 5.0V, f = 1MHz TEMPERATURE +25oC +125oC, -55oC Input Capacitance CIN VCC = 5.0V, f = 1MHz +25oC +125oC, -55oC Output Transition Time TTHL TTLH TSU VCC = 4.5V +25oC +125oC, -55oC VCC = 4.5V +25oC +125oC, -55oC Hold Time Data to LE TH VCC = 4.5V +25oC +125oC, -55oC Pulse Width LE TW VCC = 4.5V +25oC +125oC, -55oC NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. MIN 10 15 5 5 16 24 MAX 57 60 10 10 12 18 UNITS pF pF pF pF ns ns ns ns ns ns ns ns
Setup Time Data to LE
Spec Number 349
518845
Specifications HCS373MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 6.0 -6.0 VCC -0.1 2 2 2 2 2 MAX 0.75 0.1 5 50 24 29 31 24 30 UNITS mA mA mA V V A A ns ns ns ns ns
PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Three-State Output Leakage Current Noise Immunity Functional Test Data to Qn LE to Qn Enable to Output
SYMBOL ICC IOL IOH VOL VOH IIN IOZ FN TPLH, TPHL TPLH, TPHL TPZL TPZH
(NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V VCC = 4.5V and 5.5V, VIH = 0.70(VCC) VIL = 0.30(VCC), IOL = 50A VCC = 4.5V and 5.5V, VIH = 0.70(VCC) VIL = 0.30(VCC), IOH = -50A VCC = 5.5V, VIN = VCC or GND Applied Voltage = 0V or VCC, VCC = 5.5V VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V
Disable to Output NOTES:
TPLZ, TPHZ
1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5 5
PARAMETER ICC IOL/IOH IOZL/IOZH
DELTA LIMIT 12A -15% of 0 Hour 200nA
Spec Number 350
518845
Specifications HCS373MS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz TEST METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1) METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11, (Note 2) ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
STATIC BURN-IN I TEST CONNECTIONS (Note 1) 2, 5, 6, 9, 12, 15, 16, 19 1, 3, 4, 7, 8, 10, 11, 13, 14, 17, 18 20 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 2, 5, 6, 9, 12, 15, 16, 19 10 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10k 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 680 5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 2, 5, 6, 9, 12, 15, 16, 19 GROUND 10 VCC = 5V 0.5V 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20 1, 10 2, 5, 6, 9, 12, 15, 16, 19 20 11 3, 4, 7, 8, 13, 14, 17, 18
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 351
518845
HCS373MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 352
518845
HCS373MS AC Timing Diagrams
INPUT LEVEL LE VS TW INPUT LEVEL DATA DATA VS TPLH TPLH Qn VS TPHL VS LE VS VS VS TH(H) TPHL TH(L) TSU(H) TSU(L) VS VS VS VS VS VS
FIGURE 1. LATCH ENABLE PROPAGATION DELAYS
FIGURE 2. LATCH ENABLE PREREQUISITE TIMES (DATA SET-UP AND HOLD)
AC VOLTAGE LEVELS PARAMETER VCC
TTLH 80% VOL 20% 80% 20% TTHL
HCS 4.50 4.50 2.25 0 0
UNITS V V V V V
VIH VS VIL GND
VOH
OUTPUT
FIGURE 3. OUTPUT TRANSITION TIMES
AC Load Circuit
DUT TEST POINT CL RL
CL = 50pF RL = 500
Spec Number 353
518845
HCS373MS Three-State Low Timing Diagram
VIH OE VIL TPZL TPLZ VOZ VT VOL OUTPUT VW CL = 50pF RL = 500 DUT CL VS INPUT RL TEST POINT
Three-State Load Circuit
VCC
THREE-STATE LOW VOLTAGE LEVELS PARAMETER VCC VIH VS VT VW GND VIL HCS 4.50 4.50 2.25 2.25 0.90 0 0 UNITS V V V V V V V
Three-State High Timing Diagram
VIH OE VIL TPHZ TPZH VOH VW VOZ OUTPUT VT VS INPUT
Three-State Load Circuit
DUT TEST POINT CL RL
CL = 50pF RL = 500
THREE-STATE HIGH VOLTAGE LEVELS PARAMETER VCC VIH VS VT VW GND VIL HCS 4.50 4.50 2.25 2.25 3.60 0 0 UNITS V V V V V V V
Spec Number 354
518845
HCS373MS Die Characteristics
DIE DIMENSIONS: 2747 x 2693m METALLIZATION: Type: SiAl Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 x 4 mils
Metallization Mask Layout
HCS373MS
D0 (3) Q0 (2) OE (1) VCC (20) Q7 (19)
(18) D7 D1 (4)
(17) D6 Q1 (5)
(16) Q6
Q2 (6)
(15) Q5
D2 (7)
(14) D5
(8) D3
(9) Q3
(10) GND
(11) LE
(12) Q4
(13) D4
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS373 is TA14303A.
Spec Number 355
518845

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