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HP4936DY
Data Sheet December 2001
5.8A, 30V, 0.037 Ohm, Dual N-Channel, Logic Level Power MOSFET
This power MOSFET is manufactured using an innovative process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products.
Features
* Logic Level Gate Drive * 5.8A, 30V * rDS(ON) = 0.037 at ID = 5.8A, VGS = 10V * rDS(ON) = 0.055 at ID = 4.7A, VGS = 4.5V * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D1(8) D1(7)
Ordering Information
PART NUMBER HP4936DY PACKAGE SO-8 BRAND P4936DY
S1(1) G1(2)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HP4936DYT.
D2(6) D2(5) S2(3) G2(4)
Packaging
SO-8
(c)2001 Fairchild Semiconductor Corporation
HP4936DY Rev. B
HP4936DY
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HP4936DY Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (10s Pulse Width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 16 5.8 30 2 0.02 -55 to 150 300 260 UNITS V V V A A W W/oC
oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TA = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A (Figure 9) VDS = 30V, VGS = 0V VDS = 30V, VGS = 0V, TA = 55oC MIN 30 1 VDS = 15V, VGS = 10V, ID 5.8A (Figures 14, 15) VDS = 25V, VGS = 0V, f = 1MHz (Figure 4) Pulse Width <10s (Figure 11) Device Mounted on FR-4 Material TYP 0.042 0.030 10 10 27 24 18 4.5 2.5 625 270 50 MAX 1 25 100 0.055 0.037 16 16 40 35 25 62.5 UNITS V V A A nA ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance
IGSS rDS(ON)
VGS = 16V ID = 4.7A, VGS = 4.5V (Figures 6, 8) ID = 5.8A, VGS = 10V (Figures 6, 8)
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
td(ON) tr td(OFF) tf Qg Qgs Qgd CISS COSS CRSS RJA
VDD = 15V, ID 1A, RL = 15, VGEN = 10V, RGS = 6 (Figures 12, 13)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 1.7A (Figure 7) ISD = 1.7A, dISD/dt = 100A/s MIN TYP 0.8 45 MAX 1.2 80 UNITS V ns
(c)2001 Fairchild Semiconductor Corporation
HP4936DY Rev. B
HP4936DY Typical Performance Curves
30 VGS = 10, 9, 8, 7, 6, 5V 4V ID, DRAIN CURRENT (A)
Unless Otherwise Specified
30
ID, DRAIN CURRENT (A)
24
24
PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX TA = -55oC 125oC
25oC
18 PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX 12 3V 6 2, 1V 0
18
12
6
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 2 3 4 5 6 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 1. OUTPUT CHARACTERISTICS
FIGURE 2. TRANSFER CHARACTERISTICS
0.10 PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX rDS(ON), DRAIN TO SOURCE ON STATE RESISTANCE (W) 0.08 C, CAPACITANCE (pF)
1250 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD CISS COSS
1000
0.06 VGS = 4.5V 0.04 VGS = 10V
750
500
0.02
250
CRSS
0 0 6 12 18 24 30 36 ID, DRAIN CURRENT (A)
0 0 6 12 18 24 VDS , DRAIN TO SOURCE VOLTAGE (V) 30
FIGURE 3. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 4.
CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDS = 15V ID = 5.8A
2.00 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX VGS = 10V ID = 5.8A 1.75
8
1.50 1.25 1.00 0.75 0.5 -50
6
4
2
0 0 4 8 12 16 20 Qg, GATE CHARGE (nC)
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 5.
GATE TO SOURCE VOLTAGE vs GATE CHARGE
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HP4936DY Rev. B
HP4936DY Typical Performance Curves
100 ISD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX 10 TJ = 150oC 1 TJ = 25oC 0.1
Unless Otherwise Specified (Continued)
0.09 0.08 rDS(ON), DRAIN TO SOURCE ON STATE RESISTANCE (W) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 ID = 5.8A PULSE DURATION = 80s DUTY CYCLE = 0.8% MAX
0.01
0.001 0.2
0.4
0.6
0.8
1.0
1.2
0 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 7. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE TO SOURCE VOLTAGE
0.4 0.2 VGS(TH) VARIANCE (V) 0 ID = 250A -0.2 -0.4 -0.6 -0.8 -50
50
40 POWER (W) 125 150
30
20
10
0 -25 0 25 50 75 100 0.01 0.10 1.00 t, PULSE WIDTH (s) 10.00 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. GATE THRESHOLD VOLTAGE VARIANCE vs JUNCTION TEMPERATURE
FIGURE 10. SINGLE PULSE POWER CAPABILITY vs PULSE WIDTH
2 1 THERMAL IMPEDANCE DUTY CYCLE = 0.5 0.2 0.1 0.1 0.05 0.02 SINGLE PULSE 0.01 10-4 10-3 10-1 10-2 t, RECTANGULAR PULSE DURATION (s) 1 t1 t2 NOTES: DUTY CYCLE, D = t1/t2 TJ = PD x ZJA x RJA + TA SURFACE MOUNTED 10 30 PDM ZJA, NORMALIZED
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
(c)2001 Fairchild Semiconductor Corporation
HP4936DY Rev. B
HP4936DY Test Circuits and Waveforms
VDS tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 12. SWITCHING TIME TEST CIRCUIT
FIGURE 13. SWITCHING TIME WAVEFORM
VDS RL
VDD Qg Qgd Qgs VGS
VGS
+
VDD DUT Ig(REF) Ig(REF) 0 0
VDS
FIGURE 14. GATE CHARGE TEST CIRCUIT
FIGURE 15. GATE CHARGE WAVEFORMS
(c)2001 Fairchild Semiconductor Corporation
HP4936DY Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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