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HUF75829D3, HUF75829D3S
Data Sheet February 2000 File Number 4795.1
18A, 150V, 0.110 Ohm, N-Channel, UltraFET Power MOSFET Packaging
JEDEC TO-251AA JEDEC TO-252AA
DRAIN (FLANGE)
Features
* Ultra Low On-Resistance - rDS(ON) = 0.110, VGS = 10V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.intersil.com * Peak Current vs Pulse Width Curve
SOURCE DRAIN GATE
DRAIN (FLANGE)
GATE SOURCE
HUF75829D3
HUF75829D3S * UIS Rating Curve
Symbol
D
Ordering Information
PART NUMBER HUF75829D3
G
PACKAGE TO-251AA TO-252AA
BRAND 75829D 75829D
HUF75829D3S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF75829D3ST.
S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified HUF75829D3, HUF75829D3S UNITS V V V A A 150 150 20 18 13 Figure 4 Figures 6, 14, 15 110 0.73 -55 to 175 300 260 W W/oC
oC oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2000.
HUF75829D3, HUF75829D3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 140V, VGS = 0V VDS = 135V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-251 and TO-252 1.36 100
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
150 -
-
1 250 100
V A A nA
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 18A, VGS = 10V (Figure 9)
2 -
0.0925
4 0.110
V
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 1080 260 90 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 75V, ID = 18A, Ig(REF) = 1.0mA (Figures 13, 16, 17) 58 31 2.1 4.6 11 70 37 2.5 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 75V, ID = 18A VGS = 10V, RGS = 10 (Figures 18, 19) 8.5 30 53 30 58 125 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 18A ISD = 9A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 18A, dISD/dt = 100A/s ISD = 18A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 155 800 UNITS V V ns nC
2
HUF75829D3, HUF75829D3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
20
ID, DRAIN CURRENT (A)
15 VGS = 10V 10
5
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 I = I25 175 - TC 150 VGS = 10V
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
3
HUF75829D3, HUF75829D3S Typical Performance Curves
100 IAS, AVALANCHE CURRENT (A) SINGLE PULSE TJ = MAX RATED TC = 25oC
(Continued)
100
ID, DRAIN CURRENT (A)
100s 10
STARTING TJ = 25oC 10 STARTING TJ = 150oC
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
1ms
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.001 0.01 0.1 1 10
10ms 300
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
35 30 ID, DRAIN CURRENT (A) 25 20 15 10 5 0 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 6 TJ = 175oC TJ = -55oC TJ = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
35 30 ID, DRAIN CURRENT (A) 25 VGS =5V 20 15 10 5 0 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 VGS = 10V VGS = 6V
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE
1.2 VGS = VDS, ID = 250A
2.5
1.0
2.0
1.5
0.8
1.0 VGS = 10V, ID = 18A 0.5 -80 -40 160 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 200 0.6 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
4
HUF75829D3, HUF75829D3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1000 CISS = CGS + CGD COSS CDS + CGD
(Continued)
3000 VGS = 0V, f = 1MHz
1.1
1.0
C, CAPACITANCE (pF)
100 CRSS = CGD
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
20 0.1
1.0
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 75V 8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 18A ID = 9A
2
0 0 5 10 15 25 20 Qg, GATE CHARGE (nC) 30 35
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
5
HUF75829D3, HUF75829D3S Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
6
HUF75829D3, HUF75829D3S PSPICE Electrical Model
.SUBCKT HUF75829 2 1 3 ;
CA 12 8 1.70e-9 CB 15 14 1.70e-9 CIN 6 8 9.90e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 4 January 2000
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 3.11e-9 LSOURCE 3 7 3.72e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 6.22e-2 RGATE 9 20 2.13 RLDRAIN 2 5 10 RLGATE 1 9 31.1 RLSOURCE 3 7 37.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.88e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*36),3))} .MODEL DBODYMOD D (IS = 8.80e-13 RS = 1.05e-2 XTI = 5 TRS1 = 2.20e-3 TRS2 = 3.70e-6 CJO = 1.04e-9 TT = 9.90e-8 M = 0.55) .MODEL DBREAKMOD D (RS = 1.05 TRS1 = 1.80e-3 TRS2 = 3.00e-6) .MODEL DPLCAPMOD D (CJO = 1.30e-9 IS = 1e-30 M = 0.82) .MODEL MMEDMOD NMOS (VTO = 3.22 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.13) .MODEL MSTROMOD NMOS (VTO = 3.67 KP = 53 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.78 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.3 ) .MODEL RBREAKMOD RES (TC1 =1.10e-3 TC2 = -3.00e-7) .MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.70e-5) .MODEL RSLCMOD RES (TC1 = 4.10e-3 TC2 = 4.00e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.40e-3 TC2 = -7.50e-6) .MODEL RVTEMPMOD RES (TC1 = -2.60e-3 TC2 =-1.00e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.8 VOFF= -2.4) VON = -2.4 VOFF= -5.8) VON = -1.8 VOFF= 0.5) VON = 0.5 VOFF= -1.8)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
+
-
EBREAK 11 7 17 18 156.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF75829D3, HUF75829D3S SABER Electrical Model
REV 4 January 2000 template huf75829 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 8.80e-13, rs=1.05e-2, xti=5, trs1=2.20e-3, trs2=3.70e-6, cjo = 1.04e-9, tt = 9.90e-8, m = 0.55) dp..model dbreakmod = (rs=1.05, trs1=1.80e-3, trs2=3.00e-6) dp..model dplcapmod = (cjo = 1.30e-9, is = 1e-30, m = 0.82) m..model mmedmod = (type=_n, vto = 3.22, kp = 5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.67, kp = 53, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.78, kp = 0.10, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -2.4) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -5.8) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8) RSLC1 c.ca n12 n8 = 1.70e-9 c.cb n15 n14 = 1.70e-9 c.cin n6 n8 = 9.90e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 3.11e-9 l.lsource n3 n7 = 3.72e-9
GATE 1 RLGATE CIN LGATE 51 RSLC2 ISCL
LDRAIN DRAIN 2 RLDRAIN
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 MWEAK MMED EBREAK + 17 18
DBODY
MSTRO 8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.10e-3, tc2 = -3.00e-7 res.rdrain n50 n16 = 6.22e-2, tc1 = 9.40e-3, tc2 = 2.70e-5 res.rgate n9 n20 = 2.13 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 31.1 res.rlsource n3 n7 = 37.2 res.rslc1 n5 n51 = 1e-6, tc1 = 4.10e-3, tc2 = 4.00e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.88e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.60e-3, tc2 = -1.00e-6 res.rvthres n22 n8 = 1, tc1 = -2.40e-3, tc2 = -7.50e-6 spe.ebreak n11 n7 n17 n18 = 156.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/36))** 3)) } }
S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B
-
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 14 IT 19
15
VBAT +
-
-
8 RVTHRES
22
8
HUF75829D3, HUF75829D3S SPICE Thermal Model
REV 5 November 1999 HUF75829T CTHERM1 th 6 2.45e-3 CTHERM2 6 5 8.15e-3 CTHERM3 5 4 7.40e-3 CTHERM4 4 3 7.45e-3 CTHERM5 3 2 1.01e-2 CTHERM6 2 tl 7.49e-2 RTHERM1 th 6 9.00e-3 RTHERM2 6 5 1.80e-2 RTHERM3 5 4 9.15e-2 RTHERM4 4 3 2.43e-1 RTHERM5 3 2 3.50e-1 RTHERM6 2 tl 3.62e-1
RTHERM1 CTHERM1 th JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF75829T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.45e-3 ctherm.ctherm2 6 5 = 8.15e-3 ctherm.ctherm3 5 4 = 7.40e-3 ctherm.ctherm4 4 3 = 7.45e-3 ctherm.ctherm5 3 2 = 1.01e-2 ctherm.ctherm6 2 tl = 7.49e-2 rtherm.rtherm1 th 6 = 9.00e-3 rtherm.rtherm2 6 5 = 1.80e-2 rtherm.rtherm3 5 4 = 9.15e-2 rtherm.rtherm4 4 3 = 2.43e-1 rtherm.rtherm5 3 2 = 3.50e-1 rtherm.rtherm6 2 tl = 3.62e-1 }
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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