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HUFA75645P3, HUFA75645S3S
Data Sheet December 2001
75A, 100V, 0.014 Ohm, N-Channel, UltraFET(R) Power MOSFETs Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-263AB
Features
DRAIN (FLANGE)
* Ultra Low On-Resistance - rDS(ON) = 0.014, VGS = 10V * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and Saber Thermal Impedance Models - www.fairchild.com * Peak Current vs Pulse Width Curve
DRAIN (FLANGE)
HUFA75645P3
HUFA75645S3S
Symbol
D
* UIS Rating Curve
Ordering Information
PART NUMBER PACKAGE TO-220AB TO-263AB BRAND 75645P 75645S HUFA75645P3 HUFA75645S3S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUFA75645S3ST.
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified HUFA75645P3, HUFA75645S3S 100 100 20 75 65 Figure 4 Figures 6, 14, 15 310 2.07 -55 to 175 300 260 UNITS V V V A A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 150oC.
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absol24ute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.mtp.fairchild.com/automotive.html. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-220 and TO-263 0.48 62
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
100 -
-
1 250 100
V A A nA
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 75A, VGS = 10V (Figure 9)
2 -
0.0115
4 0.014
V
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 3790 810 230 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 50V, ID = 75A, Ig(REF) = 1.0mA (Figures 13, 16, 17) 198 106 6.8 14 41 238 127 8.2 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 50V, ID = 75A VGS = 10V, RGS = 2.5 (Figures 18, 19) 14 117 41 97 197 207 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 75A ISD = 35A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 145 360 UNITS V V ns nC
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0
80
ID, DRAIN CURRENT (A)
60
VGS = 10V
0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
40
20
0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 175 - TC 150
IDM, PEAK CURRENT (A)
1000
100 50
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
10-5
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S Typical Performance Curves
600
(Continued)
500
100 100s
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 10
1ms
STARTING TJ = 150oC
10ms
1
100
300
10 0.001
0.01
0.1
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
150 VGS = 20V VGS = 10V 120 VGS =5V 90 VGS = 7V VGS = 6V
ID, DRAIN CURRENT (A)
120
90
60
TJ = 175oC TJ = -55oC TJ = 25oC
60
30
30
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 4
0 2 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 3 6
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.5
VGS = 10V, ID = 75A
1.2 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
1.0
2.0
0.8
1.5
0.6
1.0 0.4 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.5
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 10000 C, CAPACITANCE (pF) CISS = CGS + CGD
(Continued)
20000 VGS = 0V, f = 1MHz
1.1
1000
COSS CDS + CGD
1.0
CRSS = CGD 100 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) 50 0.1 1.0 10 100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 50V 8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 50A ID = 25A 0 30 60 90 Qg, GATE CHARGE (nC) 120
2
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S PSPICE Electrical Model
.SUBCKT HUFA75645 2 1 3 ;
CA 12 8 5.31e-9 CB 15 14 5.31e-9 CIN 6 8 3.56e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 21 May 1999
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.1e-9 LSOURCE 3 7 4.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.80e-3 RGATE 9 20 0.83 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.65e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*205),3.5))} .MODEL DBODYMOD D (IS = 3.00e-12 IKF = 19 RS = 1.78e-3 XTI = 5 TRS1 = 2.25e-3 TRS2 = 1.00e-5 CJO = 5.32e-9 TT = 7.4e-8 M = 0.68) .MODEL DBREAKMOD D (RS = 2.15e-1 IKF = 1 TRS1 = 8e-4 TRS2 = 3e-6) .MODEL DPLCAPMOD D (CJO = 5.55e-9 IS = 1e-30 M = 0.98) .MODEL MMEDMOD NMOS (VTO = 3.13 KP = 10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.83) .MODEL MSTROMOD NMOS (VTO = 3.51 KP = 93 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.11 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.33 ) .MODEL RBREAKMOD RES (TC1 = 9.9e-4 TC2 = -1.3e-6) .MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5) .MODEL RSLCMOD RES (TC1 = 2.63e-3 TC2 = 1.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.57e-3 TC2 = -7.05e-6) .MODEL RVTEMPMOD RES (TC1 = -2.87e-3 TC2 = -2.21e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.2 VOFF= -2.4) VON = -2.4 VOFF= -6.2) VON = -1.8 VOFF= 0.5) VON = 0.5 VOFF= -1.8)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
EBREAK 11 7 17 18 115.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S SABER Electrical Model
REV 21 May 1999 template ta75645 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.00e-12, cjo = 5.32e-9, tt = 7.4e-8, xti = 5, m = 0.68) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.55e-9, is = 1e-30, vj=1.0, m = 0.8) m..model mmedmod = (type=_n, vto = 3.13, kp = 10, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.51, kp = 93, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.65, kp = 0.11, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4) DPLCAP sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8) c.ca n12 n8 = 5.31e-9 c.cb n15 n14 = 5.31e-9 c.cin n6 n8 = 3.56e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9
GATE 1 RLGATE CIN LGATE RSLC2 ISCL
LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.9e-4, tc2 = -1.3e-6 res.rdbody n71 n5 = 1.78e-3, tc1 = 2.25e-3, tc2 = 1.e-5 res.rdbreak n72 n5 = 2.15e-1, tc1 = 8e-4, tc2 = 3e-6 res.rdrain n50 n16 = 7.8e-3, tc1 = 9.4e-3, tc2 = 2.93e-5 res.rgate n9 n20 = 0.83 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 2.63e-3, tc2 = 1.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.65e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.87e-3, tc2 = -2.21e-6 res.rvthres n22 n8 = 1, tc1 = -2.57e-3, tc2 = -7.05e-6 spe.ebreak n11 n7 n17 n18 = 115.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/205))** 3.5)) } }
S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B
-
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 14 IT 19
15
VBAT +
-
-
8 RVTHRES
22
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S SPICE Thermal Model
REV 28 July 1999 HUFA75645T CTHERM1 th 6 8.80e-3 CTHERM2 6 5 2.50e-2 CTHERM3 5 4 2.70e-2 CTHERM4 4 3 3.70e-2 CTHERM5 3 2 4.40e-2 CTHERM6 2 tl 3.40e-1 RTHERM1 th 6 1.20e-2 RTHERM2 6 5 3.00e-2 RTHERM3 5 4 4.30e-2 RTHERM4 4 3 8.80e-2 RTHERM5 3 2 9.90e-2 RTHERM6 2 tl 1.10e-1
RTHERM1 CTHERM1 th JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUFA75645T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 8.80e-3 ctherm.ctherm2 6 5 = 2.50e-2 ctherm.ctherm3 5 4 = 2.70e-2 ctherm.ctherm4 4 3 = 3.70e-2 ctherm.ctherm5 3 2 = 4.40e-2 ctherm.ctherm6 2 tl = 3.40e-1 rtherm.rtherm1 th 6 = 1.20e-2 rtherm.rtherm2 6 5 = 3.00e-2 rtherm.rtherm3 5 4 = 4.30e-2 rtherm.rtherm4 4 3 = 8.80e-2 rtherm.rtherm5 3 2 = 9.90e-2 rtherm.rtherm6 2 tl = 1.10e-1 }
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
TRADEMARKS
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Rev. H4

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