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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FEATURES
* 24 LVCMOS outputs, 7 typical output impedance * Output frequency up to 167MHz * 275ps output skew, 600ps part to part skew * Translates any differential input signal (PECL, HSTL, LVDS) to LVCMOS without external bias networks * Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input * Translates and inverts any single-ended input signal to LVCMOS with resistor bias on CLK input * Multiple differential clock input pairs for redundant clock applications * LVCMOS control inputs * Multiple output enable pins for disabling unused outputs in reduced fanout applications * 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes * 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch * 0C to 70C ambient operating temperature * Industrial temperature versions available upon request
GENERAL DESCRIPTION
The ICS8344 is a low voltage, low skew fanout buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8344 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. ICS8344 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes.
,&6
Guaranteed output and part-to-part skew characteristics make the ICS8344 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15
CLK_SEL CLK0 nCLK0 CLK1 nCLK1 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23
0
1
Q0 - Q7 OE1 O8 - Q15 OE2 O16 - Q23 OE3
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8344
Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8344 www.icst.com REV. B FEBRUARY 2, 2001
1
OE1 OE2 OE3 CLK0 nCLK0 VDDI GND CLK1 nCLK1 VDDI GND CLK_SEL
48-Lead LQFP Y Package Top View
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 5, 6 7, 8, 11, 12 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 15, 19 16 17 20 21 22 23 24 25, 26, 29, 30 31, 32, 35, 36 37, 38, 41, 42 43, 44, 47, 48 Name Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 VDDO GND CLK_SEL VDDI nCLK1 CLK1 nCLK0 CLK0 OE3 OE2 OE1 Q0, Q1, Q2, Q3 Q4, Q5, Q6, Q7 Q8, Q9, Q10, Q11 Q12, Q13, Q14, Q15 Type Output Power Power Input Power Input Input Input Input Input Input Input Output Output Pullup Pullup Pulldown Description Q15 thru Q23 outputs. 7 typical output impedance. Output power supply. Connect 3.3V or 2.5V. Power supply ground. Connect to ground. Clock select input. Selects between CLK0, nCLK0 and CLK1, nCLK1 as the differential pair that controls the output. Input power supply. Connect 3.3V or 2.5V. Inver ting input of secondar y differential clock input pair. Inver ting input of primar y differential clock input pair.
Pulldown Non-inver ting input of secondar y differential clock input pair. Pulldown Non-inver ting input of primar y differential clock input pair. Output enable. Controls enabling and disabling of outputs Pullup Q16 thru Q23. Output enable. Controls enabling and disabling of outputs Pullup Q8 thru Q15. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q7. Q0 thru Q7 outputs. 7 typical output impedance. Q8 thru Q15 outputs. 7 typical output impedance.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance CLK0, nCLK0, CLK1, nCLK1 CLK_SEL, OE1, OE2, OE3 VDDI, VDDO = 3.465V VDDI = 3.465V, VDDO = 2.625V VDDI, VDDO = 2.625V 51 51 7 Test Conditions Minimum Typical Maximum Units pF pF pF pF pF K K
CPD
Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance
RPULLUP RPULLDOWN ROUT
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Bank 1 Input OE1 0 1 Output Q0-Q7 Hi-Z Active Input OE2 0 1 Bank 2 Output Q8-Q15 Hi-Z Active Input OE3 0 1 Bank 3 Output Q16-Q23 Hi-Z Active
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 CLK0, nCLK0 Selected De-selected Clock CLK1, nCLK1 De-selected Selected
TABLE 3C. CLOCK INPUTS FUNCTION TABLE
Inputs OE1, OE2, OE3 1 1 1 1 1 CLK 0 1 0 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Q0 thru Q23 LOW HIGH LOW HIGH HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to VDDI, a resistor of equal value to ground and a 0.1F capacitor from the input to ground. The resulting switch point is VDDI/2.
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0C to 70C -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDDI VDDO IDDI Parameter Input Power Supply Voltage Output Power Supply Voltage Quiescent Power Supply Current VDDI = VIH = 3.465V VIL = 0V Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 120 Units V V mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 Test Conditions Minimum Typical Maximum 5 150 Units A A A A
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4C. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions VDDI = 3.465V VDDI = 3.135V VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465, VIN = 0V VDDI = 3.465, VIN = 0 VDDI = VDDO = 3.135V IOH = -36mA VDDI = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.6 Minimum 2 -0.3 Typical Maximum 3.8 0.8 5 150 Units V V A A A A V V
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum Typical Maximum Units 167 f = 167MHz f = 167MHz 0MHz f 167MHz 0MHz f 167MHz Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 30% to 70% 30% to 70% 0MHz f 167MHz f = 167MHz 200 200 tCYCLE/2- 0.65 2.35 tCYCLE/2 2.5 0.3 0.9 2.6 2.4 1.3 2 4.3 4.3 150 275 600 1000 1000 tCYCLE/2 + 0.65 3.65 5 4 MHz V V ns ns ps ps ps ps ps ns ns ns ns
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX VPP VCMR tpLH tpHL tsk(b) tsk(o) tsk(pp) tR tF tPW tEN tDIS Maximum Input Frequency Peak-to-Peak Input Voltage Common Mode Input Voltage Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 Output Skew; NOTE 3 Par t-to-Par t Skew; NOTE 4 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Pulse Width Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5
f = 66.7MHz f = 66.7MHz
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50 to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 VDDI = VIH = 3.465V VIL = 0V Typical 3.3 2.5 Maximum 3.465 2.625 120 Units V V mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDDI VDDO IDDI Parameter Input Power Supply Voltage Output Power Supply Voltage Quiescent Power Supply Current
TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDDI = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 Test Conditions Minimum Typical Maximum 5 150 Units A A A A
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4F. LVCMOS DC CHARACTERISTICS, VDDI = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions VDDI = 3.465V VDDI = 3.465V VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465, VIN = 0V VDDI = 3.465, VIN = 0 VDDI = 3.135V, VDDO = 2.375V IOH = -36mA VDDI = 3.135V, VDDO = 2.365V IOL = 27mA -150 -5 1.8 Minimum 2 -0.3 Typical Maximum Units 3.8 .8 5 150 V V A A A A V
VOH
Output High Voltage
VOL
Output Low Voltage
0.63
V
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX VPP VCMR tpLH tpHL tsk(b) tsk(o) tsk(pp) tR tF tP W tEN tDIS Parameter Maximum Input Frequency Peak-to-Peak Input Voltage Common Mode Input Voltage Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 Output Skew; NOTE 3 Par t-to-Par t Skew; NOTE 4 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Pulse Width Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5 f = 167MHz f = 167MHz 0MHz f 167MHz 0MHz f 167MHz Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 30% to 70% 30% to 70% 0MHz f 167MHz f = 167MHz f = 66.7MHz f = 66.7MHz 300 300 tCYCLE/2 tCYCLE/2 - 0.65 2.35 0.3 0.9 2.6 2.6 Test Conditions Minimum Typical Maximum 167 1.3 2 4.5 4.2 150 275 600 1700 1400 tCYCLE/2 + 0.65 3.65 6 6 Units MHz V V ns ns ps ps ps ps ps ns ns ns ns
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50 to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 2.375 2.375 VDDI = VIH = 3.465V VIL = 0V Typical 2.5 2.5 Maximum 2.625 2.625 120 Units V V mA
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDDI VDDO IDDI Parameter Input Power Supply Voltage Output Power Supply Voltage Quiescent Power Supply Current
TABLE 4H. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 -5 Test Conditions Minimum Typical Maximum 5 150 Units A A A A
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4I. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL OE1, OE2, OE3 CLK_SEL Test Conditions VDDI = 2.625V VDDI = 2.375V VDDI = VIN = 2.625V VDDI = VIN = 2.625V VDDI = 2.625, VIN = 0V VDDI = 2.625, VIN = 0 VDDI = VDDO = 2.375V IOH = -27mA VDDI = VDDO = 2.375V IOL = 27mA -150 -5 1.77 0.6 Minimum 2 -0.3 Typical Maximum 2.9 0.8 5 150 Units V V A A A A V V
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5C. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX VPP VCMR tpLH tpHL tsk(b) tsk(o) tsk(pp) tR tF tPW tEN tDIS Maximum Input Frequency Peak-to-Peak Input Voltage Common Mode Input Voltage Propagation Delay, Low-to-High Propagation Delay, High-to-Low Bank Skew; NOTE 2 Output Skew; NOTE 3 Par t-to-Par t Skew; NOTE 4 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Pulse Width Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5 f = 167MHz f = 167MHz 0MHz f 167MHz 0MHz f 167MHz Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 30% to 70% 30% to 70% 0MHz f 167MHz f = 167MHz f = 66.7MHz f = 66.7MHz 300 300 tCYCLE/2 - 0.65 2.35 tCYCLE/2 0.3 0.9 2.7 2.7 Test Conditions Minimum Typical Maximum 167 1.3 2 4.3 4.3 150 275 600 1700 1400 tCYCLE/2 + 0.65 3.65 6 6 Units MHz V V ns ns ps ps ps ps ps ns ns ns ns
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50 to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS
VDDI
CLK
VPP
CROSS POINTS VCMR
nCLK
GND
FIGURE 1A - LVDS, HSTL DIFFERENTIAL INPUT LEVELS
VDDI
CLK
VPP
CROSS POINTS
VCMR
nCLK
GND
FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL
VDDI CLK or nCLK GND
FIGURE 1C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
VPP
nCLK tPHL Q tPLH
VDDO/2
FIGURE 2A - PROPAGATION DELAYS
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
OEx
3.3V
OEx
0V tPHZ tPZH VOH - 300mV VDDO/2 tPLZ VDDO/2 VOL + 300mV tPZL
Q
VOH
Q
VOL
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
VPP
nCLK Q0, Q8, Q16

VDDO/2
VDDO/2

tsk(b)
tsk(b)
Q7, Q15, Q23
VDDO/2
VDDO/2
FIGURE 3A - BANK SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
VPP
nCLK
Q0 - Q7
VDDO/2
VDDO/2
tsk(o) Q8 - Q15 Q16 - Q23 VDDO/2
tsk(o)
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 4A - SKEW DEFINITIONS & WAVEFORMS
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
VPP
nCLK PART 1 Q0 - Q7 Q8 - Q15 Q16 - Q23 VDDO/2 VDDO/2
tsk(p) PART 2 Q0 - Q7 Q8 - Q15 Q16 - Q23 VDDO/2
tsk(p)
VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
D
D2
1 2 3
52
40 39
L
E
E1
E2
N
13 14
27 26
e
A
A2
D1 -CSEATING PLANE
ccc C
A1
b
c
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 0.05 1.35 0.17 0.09 9.00 BASIC 7.00 BASIC 5.50 9.00 BASIC 7.00 BASIC 5.50 0.5 BASIC 0.60 0.75 7 0.08 1.40 0.22 MINIMUM NOMINAL 48 1.60 0.15 1.45 0.27 0.20 MAXIMUM
q
ccc
Reference Document: JEDEC Publication 95, MS-026
8344
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REV. B FEBRUARY 2, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS8344BY ICS8344BYT Marking ICS8344BY ICS8344BY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 2000 Temperature 0C to 70C 0C to 70C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344
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REV. B FEBRUARY 2, 2001

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