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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
FEATURES
* One Differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (23.2MHz - 30MHz) * Output frequency ranges: 116MHz - 150MHz and 580MHz - 750MHz * VCO range: 580MHz - 750MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.46ps (typical) * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS844251I-15 is an Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS844251I-15 uses an 18pF parallel resonant crystal over the range of 23.2MHz 30MHz. For Ethernet applications, a 25MHz crystal is used. The device has excellent <1ps phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS844251I-15 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
IC S
COMMON CONFIGURATION TABLE
Inputs Crystal Frequency (MHz) 25 26.667 25 26.667 FREQ_SEL 1 1 0 0 M 25 25 25 25 N 1 1 5 5 Multiplication Value M/N 25 25 5 5 Output Frequency (MHz) 625 666.67 125 133.33
BLOCK DIAGRAM
FREQ_SEL
Pulldown
PIN ASSIGNMENT
FREQ_SEL N 0 /1 1 /5
VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
580MHz - 750MHz
Q nQ
ICS844251I-15
8-Lead TSSOP 4.4mm x 3.0mm x 0.925mm package body G Package Top View
M = /25 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844251BGI-15
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1
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VDDA GND XTAL_OUT, XTAL_IN FREQ_SEL nQ, Q VDD Power Power Input Input Output Power Type Description Analog supply pin. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. Power supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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2
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V 10mA 15mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Power Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 100 8 Maximum 3.465 3.465 Units V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Power Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 95 8 Maximum 2.625 2.625 Units V V mA mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A A
844251BGI-15
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REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
Minimum Typical 400 TBD 1.4 TBD Maximum Units mV mV V mV
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 400 TBD 1.15 TBD Maximum Units mV mV V mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 23.2 Test Conditions Minimum Typical Fundamental 30 50 7 1 MHz pF mW Maximum Units
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency Test Conditions f_SEL = 0 f_SEL = 1 125MHz @ Integration Range: 1.875MHz - 20MHz 625MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 11 6 580 0.46 0.35 300 50 Typical Maximum 150 750 Units MHz MHz ps ps ps %
t jit(O) t R / tF
RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency Test Conditions f_SEL = 0 f_SEL = 1 125MHz @ Integration Range: 1.875MHz - 20MHz 625MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 11 6 580 0.46 0.35 300 50 Typical Maximum 150 750 Units MHz MHz ps ps ps %
tjit(O) t R / tF
RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
844251BGI-15
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4
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
TYPICAL PHASE NOISE
AT
125MHZ @ 3.3V
0
-10 -20 -30 -40 -50
Ethernet Filter 125MHz
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.46ps (typical)
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 100 1k
10k
Phase Noise Result by adding Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50
AT
625MHZ @ 3.3V
Ethernet Filter 625MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
844251BGI-15
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Phase Noise Result by adding Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
Qx
3.3V5% POWER SUPPLY
SCOPE
2.5V5% POWER SUPPLY
Qx
+ Float GND -
SCOPE
+ Float GND -
LVDS
nQx
LVDS
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
80% Clock Outputs 80% VSW I N G 20% tR tF 20%
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
Phase Noise Plot
Noise Power
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD VDD
out
Phase Noise Mask
out
VOS/ VOS
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
VDD VDD
OFFSET VOLTAGE SETUP
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844251BGI-15
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6
out
REV. A NOVEMBER 23, 2005
DC Input
LVDS
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844251I-15 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844251I-15 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 X1 Crystal XTAL_OUT C2
Figure 2. CRYSTAL INPUt INTERFACE
844251BGI-15
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7
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input.
2.5V or 3.3V VDD LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844251BGI-15
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8
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS844251I-15 is: 2398
844251BGI-15
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9
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
FOR
8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
844251BGI-15
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10
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844251I-15
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
Marking 4BI15 4BI15 TB D TBD Package 8 Lead TSSOP 8 Lead TSSOP 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS844251BGI-15 ICS844251BGI-15T ICS844251BGI-15LF ICS844251BGI-15LFT
NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844251BGI-15
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11
REV. A NOVEMBER 23, 2005

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