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Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
FEATURES
* Two differential LVPECL / ECL bank outputs * Two differential LVPECL clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz (typical) * Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input * Output skew: 40ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 570ps (maximum) * Additive phase jitter, RMS: 0.03ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS853013 is a low skew, high performance dual 1-to-3 Differential-to-2.5V/3.3V/5V HiPerClockSTM LVPECL/ECL Fanout Buffer and a member of the HiperclocksTM family of High Performance Clock Solutions from ICS. The ICS853013 operates with a positive or negative power supply at 2.5V, 3.3V, or 5V. Guaranteed output and part-to-par t skew characteristics make the ICS853013 ideal for those clock distribution applications demanding well defined performance and repeatability.
IC S
BLOCK DIAGRAM
PCLKA nPCLKA QA0 nQA0 QA1 nQA1 QA2 nQA2
PIN ASSIGNMENT
nQA0 QA0 VCC PCLKA nPCLKA PCLKB nPCLKB VCC nQB0 QB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VCC QB2 nQB2 QB1 nQB1 VEE
PCLKB nPCLKB
QB0 nQB0 QB1 nQB1 QB2 nQB2
ICS853013
20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View
853013AM
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1
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Power supply pins. Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Differential output pair. LVPECL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 8, 16 4 5 6 7 9, 10 11 12, 13 14, 15 17, 18 19, 20 Name nQA0, QA0 VCC PCLKA nPCLKA PCLKB nPCLKB nQB0, QB0 VEE nQB1, QB1 nQB2, QB2 nQA2, QA2 nQA1, QA1 Power Input Input Input Input Output Power Output Output Output Output Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs PCLKA or PCLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLKA or nPCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs QA0:QA2, nQA0:nQA2, QB0:QB2 nQB0:nQB2 HIGH LOW HIGH LOW HIGH HIGH LOW LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853013AM
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2
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -5.5V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA -65C to 150C 46.2C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 5.25V; VEE = 0V
Symbol VCC IEE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 5.25 60 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB PCLKA, PCLKB Input Low Current nPCLKA, nPCLKB Min
2.175 1.405 2.075 1.43 150 1.2 800
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1200 3.3 150
Min
2.225 1.425 2.075 1.43 150 1.2
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765
Min
2.295 1.44 2.075 1.43 150 1.2
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765
Units
V V V V
800
1200 3.3 15 0
800
1200 3. 3 150
mV
V A A A
-10
-1 0
-10
-150 -150 -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V.
853013AM
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3
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
-40C Min
1.375 0.605 1.275 0.63 150 1.2 800
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB Input Low Current PCLKA, PCLKB 25C Max
1.58 0.88 1.56 0.965 1200 2.5 150 -10 -10
85C Max
1.57 0.815 1.56 0.965
Typ
1.475 0.745
Min
1.425 0.625 1.275 0.63 15 0 1.2
Typ
1.495 0.72
Min
1.495 0.64 1.275 0.63 150 1.2
Typ
1.53 0.735
Max
1.565 0.83
Units
V V V V
-0.83
0.965 800 1200 2.5 150
800
1200 2.5 150
mV
V A A A
-10
-150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB Input Low Current PCLKA, PCLKB -40C Min
-1.125 -1.895 -1.225 -1.87 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535
Units
V V V V
800
1200 0 150
800
1200 0 150
mV
V A A A
-10
-10
-10
-150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V.
853013AM
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4
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
-40C Min
-1.125 -1.895 -1.225 -1.87 150 VEE+1.2V 800
TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB Input Low Current PCLKA, PCLKB 25C Max
-0.92 -1.62 -0.94 -1.535 1200 0 150 -10 -10
85C Max
-0.93 -1.685 -0.94 -1.535
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535
Units
V V V V
800
1200 0 150
800
1200 0 150
mV
V A A A
-10
-150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol fMAX tP LH tP HL tsk(o) tsk(odc) tsk(pp) tjit tR/tF Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Output Duty Cycle Skew Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time 20% to 80% 120 -40C Min Typ >2 300 300 410 410
OR
VCC = 2.375V TO 5.25V; VEE = 0V
25C 85C Max Min Typ >2 520 520 40 40 250 0.03 0.03 150 190 230 360 360 465 465 57 0 57 0 40 40 250 Max Units GH z ps ps ps ps ps ps ps
Max
Min
Typ >2
510 51 0 40 40 250
330 330
42 5 42 5
0.03 18 0 250 140
180
All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853013AM
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5
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 156.25MHz
= 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
853013AM
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REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
LVPECL
nQx
nPCLKA, nPCLKB
V
PP
VEE
Cross Points
V
CMR
PCLKA, PCLKB V EE
-0.375V to -3.25V
OUTPUT LOAD AC TEST CIRCUIT
nQx PART 1 Qx nQy PART 2 Qy tsk(pp)
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
nPCLKA, nPCLKB PCLKA, PCLKB
OUTPUT SKEW
nPCLKA, nPCLKB PCLKA, PCLKB
nQA0:nQA2, nQB0:nQB2, QA0:QA2, QB0:QB2,
nQA0:nQA2, nQB0:nQB2, QA0:QA2, QB0:QB2,
tpLH
tpHL
tpLH
tpHL
tsk(odc) = tpLH - tpHL
OUTPUT DUTY CYCLE SKEW
PROPAGATION DELAY
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
853013AM
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8
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2
3.3V 3.3V
R4 125
3.3V Zo = 50 Ohm LVDS C1 R3 1K R4 1K PCLK
nPCLK
HiPerClockS PC L K /n PC LK
R1 1K
R2 1K
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched imped-
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853013. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.25V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (5.25V, with all outputs switching) = 315mW + 185.64mW = 500.64mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.500W * 39.7C/W = 104.85C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN SOIC, FORCED CONVECTION
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A OCTOBER 19, 2005
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3. Calculations and Equations.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50 VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853013AM
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
20 LEAD SOIC
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853013 is: 226 Pin compatible with MC100LVEL13, MC100EL13
853013AM
www.icst.com/products/hiperclocks.html
14
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
20 LEAD SOIC
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119 www.icst.com/products/hiperclocks.html
15
853013AM
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Marking Package 20 Lead SOIC 20 Lead SOIC 20 Lead "Lead-Free" SOIC 20 Lead "Lead-Free" SOIC Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853013AM ICS853013AMT ICS853013AMLF ICS853013AMLFT ICS853013AM ICS853013AM ICS853013AMLF ICS853013AMLF
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853013AM
www.icst.com/products/hiperclocks.html
16
REV. A OCTOBER 19, 2005
Integrated Circuit Systems, Inc.
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free marking. Date 10/19/05
Rev A
Table T8
Page 8 16
853013AM
www.icst.com/products/hiperclocks.html
17
REV. A OCTOBER 19, 2005

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