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Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
* Fully integrated PLL * 6 LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications * Maximum output frequency: 150MHz * VCO range: 220MHz to 480MHz * External feedback for "zero delay" clock regeneration * Output skew, Same Frequency: 300ps (maximum) * Output skew, Different Frequency: 400ps (maximum) * Cycle-to-cycle jitter: 100ps (maximum) * 3.3V supply voltage * -40C to 85C ambient operating temperature * Pin compatible with MPC931
GENERAL DESCRIPTION
The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay HiPerClockSTM Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. With output frequencies up to 150MHz, the ICS87931I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87931I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
,&6
Selectable clock inputs, CLK1 and differential CLK0, nCLK0 support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A, B and C are controlled by the DIV_SELA, DIV_SELB and DIV_SELC, respectively. For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When LOW, the nMR input resets the internal dividers and forces the outputs to the high impedance state. The effective fanout of the ICS87931I can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines.
PIN ASSIGNMENT
DIV_SELC DIV_SELB DIV_SELA GND VDDO QA0 QA1 nc
32 31 30 29 28 27 26 25 nc VDDA POWER_DN CLK1 nMR CLK0 nCLK0 GND 1 2 3 4 5 6 7 8 24 23 GND QB0 QB1 VDDO EXTFB_SEL CLK_SEL PLL_SEL nc
ICS87931I
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
9 10 11 12 13 14 15 16
nc CLK_EN0 CLK_EN1 EXT_FB VDDO QC0 QC1 GND
22 21 20 19 18 17
BLOCK DIAGRAM
POWER_DN Pullup PLL_SEL Pullup CLK_SEL Pulldown CLK1 Pullup
CLK0
Pullup
1 0 PHASE DETECTOR LPF 1 0 /8 VCO
0 0 1 /2 1 QA1 /2//4 QB0 QB1 /2//4 QA0
nCLK0 None EXTFB_SEL Pulldown EXT_FB Pullup
DIV_SELA Pulldown DIV_SELB Pulldown CLK_EN0 Pullup CLK_EN1 Pullup DIV_SELC Pulldown nMR Pullup POWER-ON RESET /4//6 DISABLE LOGIC
QC0 QC1
87931BYI
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description No connect. Analog supply pin. Controls the frequency being fed to the output dividers. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. Active LOW Master reset. When logic LOW, the internal dividers are reset causing the outputs to go low. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 9, 17, 32 2 3 4 5 6 7 8, 16, 24,25 10, 11 12 13, 21, 28 14, 15 18 Name nc VDDA POWER_DN CLK1 nMR CLK0 nCLK0 GND CLK_EN0, CLK_EN1 EXT_FB VDDO QC0, QC1 PLL_SEL Power Input Input Input Input Input Power Input Input Power Output Input Pullup Pullup Pullup Unused
19 20 22, 23 26, 27 29 30 31
CLK_SEL EXTFB_SEL QB1, QB0 QA1, QA0 DIV_SELA DIV_SELB DIV_SELC
Input Input Output Output Input Input Input
Pullup Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Power supply ground. Controls the enabling and disabling of the clock outputs. See Table 3B. Pullup LVCMOS / LVTTL interface levels. External feedback. When LOW, selects internal feedback. Pullup When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels. Output supply pins. Bank C clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Selects between the PLL and reference clocks as the input to the Pullup output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels. Clock select input. Selects the Phase Detector Reference. Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Pulldown External feedback select. LVCMOS / LVTTL interface levels. Bank B clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock outputs.7 typical output impedance. LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank B as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank C as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 51 VDDA, VDDO = 3.465V 12 7 Maximum Units pF K K pF
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Function Logic 0 CLK0, nCLK0 Bypass PLL Logic 1 CLK1 PLL Enabled EXT_FB VCO/2 Enable Outputs QA(/4); QB(/4); QC(/6)
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs Control Pin CLK_SEL PLL_SEL EXTFB_SEL POWER_DN nMR DIV_SELA:DIV_SELC
Internal Feedback VCO/1 Master Reset/Output Hi Z QA(/2); QB(/2); QC(/4)
TABLE 3B. CLK_ENX FUNCTION TABLE
Inputs CLK_EN1 0 0 1 1 CLK_EN0 0 1 0 1 DIV_SELA:DIVSELC QAx Toggle LOW Toggle Toggle QBx LOW LOW LOW Toggle QCx LOW Toggle Toggle Toggle
TABLE 4A. VCO FREQUENCY FUNCTION TABLE
Inputs DIV_ SELA 0 0 0 0 1 1 1 1 DIV_ SELB 0 0 1 1 0 0 1 1 DIV_ SELC 0 1 0 1 0 1 0 1 QAx POWER_DN = 0 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4
TO
Outputs QBx VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/2 VCO/2 VCO/4 VCO/4 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/6 VCO/4 VCO/6 VCO/4 VCO/6 VCO/4 VCO/6 QCx POWER_DN = 1 VCO/8 VCO/12 VCO/8 VCO/12 VCO/8 VCO/12 VCO/8 VCO/12 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0
TABLE 4B. INPUT REFERENCE FREQUENCY
Inputs DIV_ SELA 0 0 0 0 1 1 1 1
87931BYI
OUTPUT FREQUENCY FUNCTION TABLE (INTERNAL FEEDBACK ONLY)
Outputs QBx 2x 2x 2x 2x x x x x
3
DIV_ SELB 0 0 1 1 0 0 1 1
DIV_ SELC 0 1 0 1 0 1 0 1
QAx POWER_DN = 0 4x 4x 4x 4x 2x 2x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x
QCx POWER_DN = 1 x 2/3x x 2/3x x 2/3x x 2/3x
REV. A JUNE 23, 2003
POWER_DN = 1 POWER_DN = 0
POWER_DN = 1 POWER_DN = 0 2x 2x x x 2x 2x x x 2x 4/3x 2x 4/3x 2x 4/3x 2x 4/3x
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Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
VCO VCO/2 POWER_DN QA(/2) QB(/4) QC(/6)
FIGURE 1A. POWER_DN TIMING DIAGRAM
QA
QB
QC CLK_EN0
CLK_EN1
QA(/2)
QB(/4)
QC(/6) CLK_EN0
CLK_EN1
FIGURE 1B. CLK_ENX TIMING DIAGRAMS
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDDA + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDDA VDDO IDDA IDDO Parameter Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 20 100 Maximum 3.465 3.465 Units V V mA mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Input High Voltage DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB IOH = -20mA IOL = 20mA Test Conditions Minimum Typical 2 2 -0.3 -0.3 2.4 0.5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 120 Units V V V V A V V
VIH
VIL
Input Low Voltage Input Current
IIN VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol IIN VPP Parameter Input Current Test Conditions Minimum Typical Maximum 120 1.3 VDD - 0.85 Units A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDDA + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
87931BYI
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical Maximum 150 Units MHz
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Input Reference Frequency fREF NOTE: Input reference frequency is limited by the divider selection and the VCO lock range.
TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fMAX Parameter QAx, QBx Output Frequency Propagation Delay; NOTE 1 QAx, QBx, QCx QCx tPD CLK1 to EXT_FB CLK0, nCLK0 to EXT_FB Test Conditions /2 /4 /6 fref = 50MHz, FB = / 8 Same Frequency Different Frequency 220 0.8V to 2.0V 0.1 45 2 -375 -100 -200 50 Minimum Typical Maximum 150 120 80 -50 200 300 400 100 480 1 55 10 10 8 Units MHz MHz MHz ps ps ps ps ps MHz ns % ms ns ns
tsk(o) tjitter(cc)
fVCO tR/tF odc tLOCK tPZL, tPZH
Output Skew; NOTE 2, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL VCO Lock Range Output Rise Time; NOTE 3 Output Duty Cycle PLL Lock Time Output Enable Time; NOTE 3
Output Disable Time; NOTE 3 2 tPLZ, tPHZ All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87931BYI
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
VDDA, VDDO = 1.65V5%
SCOPE LVCMOS
Qx
VDDA
nCLK0
V
PP
Cross Points
V
CMR
CLK0
GND = -1.165V5%
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
DDO
V
DDO
V
DDO
V
DDO
Qx
2
V
DDO
Qy
2 tsk(o)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
2V
2V
0.8V Clock Outputs t
R
0.8V t
CLK1
F
VDD 2
nCLK0 CLK0
OUTPUT RISE/FALL TIME
V
DDO
EXT_FB
VDDO 2
QAx, QBx, QCx
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
odc & tPERIOD
87931BYI
PROPAGATION DELAY
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REV. A JUNE 23, 2003
QAx, QBx, QCx
2
2
2
tcycle
n
tcycle n+1
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
WIRING
THE
DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
sible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible.
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS87931I. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as pos-
VDD R7 10 - 15
DIV_SELC DIV_SELB DIV_SELA
R1 VDD
43
Zo = 50
Receiv er 32 31 30 29 28 27 26 25 VDD
U1 C16 10u 3.3V POWER_DN Zo = 50 Ohm C11 0.01u 1 2 3 4 5 6 7 8
nc DIV_SELC DIV_SELB DIV_SELA VDDO QA0 QA1 GND
Zo = 50 Ohm 3.3V PECL Driv er R8 50 R9 50
nc CLK_EN0 CLK_EN1 EXT_FB VDDO QC0 QC1 GND
nc VDDA POWER_DN CLK1 nMR CLK0 nCLK0 GND
GND QB0 QB1 VDDO EXTFB_SEL CLK_SEL PLL_SEL nc
24 23 22 21 20 19 18 17
R3 1K
R4 1K
R5 1K
Logic Input Pin Examples
VDD VDD CLK_EN0 CLK_EN1
Set Logic Input to '1'
RU1 1K
Set Logic Input to '0'
RU2 Not Install
R10 50
9 10 11 12 13 14 15 16
ICS87931I
Zo = 50 R2 43 Receiv er
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
(U1-13)
VDD
(U1-21)
(U1-28)
VDD=3.3V
C1 0.1uF
C2 0.1uF
C3 0.1uF
SP = Space (i.e. not intstalled)
FIGURE 4A. ICS87931I SCHEMATIC EXAMPLE
87931BYI
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The series termination resistors should be located as close to the driver pins as possible.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
50 Ohm Trace
GND
C3
R1
VCC
VCCA
R7
U1
Pin 1
VIA
Other signals
C11
C16
C2
C1
R2
50 Ohm Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS87931I
87931BYI
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87931I is: 2942
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A JUNE 23, 2003
Integrated Circuit Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking ICS87931BI ICS87931BI Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS87931BYI ICS87931BYIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87931BYI
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REV. A JUNE 23, 2003

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